Release 4.10 drivers/gpu/drm/i915/intel_hdmi.c

Directory: drivers/gpu/drm/i915
/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright Â© 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Eric Anholt <eric@anholt.net>
 *      Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"



static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 25 100.00% 2 100.00%
Total 25 100.00% 2 100.00%


static void

assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
	struct drm_i915_private *dev_priv = to_i915(dev);
	uint32_t enabled_bits;

	enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;

	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
	     "HDMI port enabled, expecting disabled\n");
}

Contributors
Person Tokens Prop Commits CommitProp
daniel vetter daniel vetter 50 84.75% 1 16.67%
paulo zanoni paulo zanoni 5 8.47% 3 50.00%
chris wilson chris wilson 3 5.08% 1 16.67%
tvrtko ursulin tvrtko ursulin 1 1.69% 1 16.67%
Total 59 100.00% 6 100.00%



struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	struct intel_digital_port *intel_dig_port =
		container_of(encoder, struct intel_digital_port, base.base);
	return &intel_dig_port->hdmi;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 23 65.71% 2 66.67%
paulo zanoni paulo zanoni 12 34.29% 1 33.33%
Total 35 100.00% 3 100.00%



static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 22 88.00% 1 50.00%
paulo zanoni paulo zanoni 3 12.00% 1 50.00%
Total 25 100.00% 2 100.00%



static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_SELECT_AVI;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_SELECT_SPD;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_SELECT_VENDOR;
	default:
		MISSING_CASE(type);
		return 0;
	}
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 20 46.51% 1 14.29%
damien lespiau damien lespiau 11 25.58% 2 28.57%
paulo zanoni paulo zanoni 6 13.95% 1 14.29%
david hardeman david hardeman 4 9.30% 1 14.29%
ville syrjala ville syrjala 1 2.33% 1 14.29%
daniel vetter daniel vetter 1 2.33% 1 14.29%
Total 43 100.00% 7 100.00%



static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VENDOR;
	default:
		MISSING_CASE(type);
		return 0;
	}
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 14 32.56% 1 12.50%
paulo zanoni paulo zanoni 14 32.56% 2 25.00%
damien lespiau damien lespiau 11 25.58% 2 25.00%
david hardeman david hardeman 2 4.65% 1 12.50%
ville syrjala ville syrjala 1 2.33% 1 12.50%
daniel vetter daniel vetter 1 2.33% 1 12.50%
Total 43 100.00% 8 100.00%



static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD_HSW;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VS_HSW;
	default:
		MISSING_CASE(type);
		return 0;
	}
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 31 72.09% 1 25.00%
damien lespiau damien lespiau 11 25.58% 2 50.00%
ville syrjala ville syrjala 1 2.33% 1 25.00%
Total 43 100.00% 4 100.00%


static i915_reg_t

hsw_dip_data_reg(struct drm_i915_private *dev_priv,
		 enum transcoder cpu_transcoder,
		 enum hdmi_infoframe_type type,
		 int i)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
	case HDMI_INFOFRAME_TYPE_SPD:
		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
	default:
		MISSING_CASE(type);
		return INVALID_MMIO_REG;
	}
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 34 48.57% 1 12.50%
ville syrjala ville syrjala 20 28.57% 3 37.50%
damien lespiau damien lespiau 11 15.71% 2 25.00%
rodrigo vivi rodrigo vivi 4 5.71% 1 12.50%
antti koskipaa antti koskipaa 1 1.43% 1 12.50%
Total 70 100.00% 8 100.00%



static void g4x_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 val = I915_READ(VIDEO_DIP_CTL);
	int i;

	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

	val &= ~g4x_infoframe_enable(type);

	I915_WRITE(VIDEO_DIP_CTL, val);

	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VIDEO_DIP_DATA, 0);
	mmiowb();

	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;

	I915_WRITE(VIDEO_DIP_CTL, val);
	POSTING_READ(VIDEO_DIP_CTL);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 70 38.04% 9 52.94%
david hardeman david hardeman 63 34.24% 1 5.88%
jesse barnes jesse barnes 29 15.76% 1 5.88%
damien lespiau damien lespiau 12 6.52% 1 5.88%
daniel vetter daniel vetter 5 2.72% 3 17.65%
chris wilson chris wilson 3 1.63% 1 5.88%
ville syrjala ville syrjala 2 1.09% 1 5.88%
Total 184 100.00% 17 100.00%



static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	u32 val = I915_READ(VIDEO_DIP_CTL);

	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 49 55.06% 2 50.00%
ville syrjala ville syrjala 40 44.94% 2 50.00%
Total 89 100.00% 4 100.00%



static void ibx_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	int i;

	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

	val &= ~g4x_infoframe_enable(type);

	I915_WRITE(reg, val);

	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();

	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 190 87.96% 5 41.67%
damien lespiau damien lespiau 11 5.09% 1 8.33%
ville syrjala ville syrjala 6 2.78% 2 16.67%
daniel vetter daniel vetter 4 1.85% 2 16.67%
chris wilson chris wilson 3 1.39% 1 8.33%
jesse barnes jesse barnes 2 0.93% 1 8.33%
Total 216 100.00% 12 100.00%



static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
	u32 val = I915_READ(reg);

	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 57 49.14% 3 60.00%
jesse barnes jesse barnes 39 33.62% 1 20.00%
jani nikula jani nikula 20 17.24% 1 20.00%
Total 116 100.00% 5 100.00%



static void cpt_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	int i;

	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

	/* The DIP control register spec says that we need to update the AVI
         * infoframe without clearing its enable bit */
	if (type != HDMI_INFOFRAME_TYPE_AVI)
		val &= ~g4x_infoframe_enable(type);

	I915_WRITE(reg, val);

	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();

	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 118 52.91% 3 16.67%
paulo zanoni paulo zanoni 80 35.87% 9 50.00%
damien lespiau damien lespiau 12 5.38% 1 5.56%
ville syrjala ville syrjala 6 2.69% 2 11.11%
daniel vetter daniel vetter 4 1.79% 2 11.11%
chris wilson chris wilson 3 1.35% 1 5.56%
Total 223 100.00% 18 100.00%



static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));

	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 47 56.63% 3 75.00%
jesse barnes jesse barnes 36 43.37% 1 25.00%
Total 83 100.00% 4 100.00%



static void vlv_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	int i;

	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);

	val &= ~g4x_infoframe_enable(type);

	I915_WRITE(reg, val);

	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();

	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

Contributors
Person Tokens Prop Commits CommitProp
shobhit kumar shobhit kumar 121 56.02% 1 6.67%
paulo zanoni paulo zanoni 71 32.87% 8 53.33%
damien lespiau damien lespiau 11 5.09% 1 6.67%
ville syrjala ville syrjala 6 2.78% 2 13.33%
daniel vetter daniel vetter 4 1.85% 2 13.33%
chris wilson chris wilson 3 1.39% 1 6.67%
Total 216 100.00% 15 100.00%



static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));

	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 60 54.05% 3 60.00%
jesse barnes jesse barnes 51 45.95% 2 40.00%
Total 111 100.00% 5 100.00%



static void hsw_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
	i915_reg_t data_reg;
	int i;
	u32 val = I915_READ(ctl_reg);

	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);

	val &= ~hsw_infoframe_enable(type);
	I915_WRITE(ctl_reg, val);

	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
					    type, i >> 2), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
					    type, i >> 2), 0);
	mmiowb();

	val |= hsw_infoframe_enable(type);
	I915_WRITE(ctl_reg, val);
	POSTING_READ(ctl_reg);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 134 62.62% 3 23.08%
ville syrjala ville syrjala 40 18.69% 3 23.08%
damien lespiau damien lespiau 17 7.94% 1 7.69%
eugeni dodonov eugeni dodonov 16 7.48% 1 7.69%
chris wilson chris wilson 3 1.40% 1 7.69%
daniel vetter daniel vetter 1 0.47% 1 7.69%
ander conselvan de oliveira ander conselvan de oliveira 1 0.47% 1 7.69%
antti koskipaa antti koskipaa 1 0.47% 1 7.69%
rodrigo vivi rodrigo vivi 1 0.47% 1 7.69%
Total 214 100.00% 13 100.00%



static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));

	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 39 66.10% 1 20.00%
ville syrjala ville syrjala 19 32.20% 3 60.00%
ander conselvan de oliveira ander conselvan de oliveira 1 1.69% 1 20.00%
Total 59 100.00% 5 100.00%

/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */


static void intel_write_infoframe(struct drm_encoder *encoder,
				  union hdmi_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
	ssize_t len;

	/* see comment above for the reason for this offset */
	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
	if (len < 0)
		return;

	/* Insert the 'hole' (see big comment above) at position 3 */
	buffer[0] = buffer[1];
	buffer[1] = buffer[2];
	buffer[2] = buffer[3];
	buffer[3] = 0;
	len++;

	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
}

Contributors
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damien lespiau damien lespiau 81 68.07% 3 75.00%
jesse barnes jesse barnes 38 31.93% 1 25.00%
Total 119 100.00% 4 100.00%



static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
					 const struct drm_display_mode *adjusted_mode)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	union hdmi_infoframe frame;
	int ret;

	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
						       adjusted_mode);
	if (ret < 0) {
		DRM_ERROR("couldn't fill AVI infoframe\n");
		return;
	}

	if (intel_hdmi->rgb_quant_range_selectable) {
		if (intel_crtc->config->limited_color_range)
			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_LIMITED;
		else
			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_FULL;
	}

	intel_write_infoframe(encoder, &frame);
}

Contributors
Person Tokens Prop Commits CommitProp
damien lespiau damien lespiau 37 32.74% 2 18.18%
ville syrjala ville syrjala 27 23.89% 2 18.18%
jesse barnes jesse barnes 19 16.81% 2 18.18%
paulo zanoni paulo zanoni 15 13.27% 3 27.27%
daniel vetter daniel vetter 14 12.39% 1 9.09%
ander conselvan de oliveira ander conselvan de oliveira 1 0.88% 1 9.09%
Total 113 100.00% 11 100.00%



static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
{
	union hdmi_infoframe frame;
	int ret;

	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
	if (ret < 0) {
		DRM_ERROR("couldn't fill SPD infoframe\n");
		return;
	}

	frame.spd.sdi = HDMI_SPD_SDI_PC;

	intel_write_infoframe(encoder, &frame);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 34 54.84% 1 25.00%
damien lespiau damien lespiau 27 43.55% 2 50.00%
paulo zanoni paulo zanoni 1 1.61% 1 25.00%
Total 62 100.00% 4 100.00%


static void

intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
			      const struct drm_display_mode *adjusted_mode)
{
	union hdmi_infoframe frame;
	int ret;

	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
							  adjusted_mode);
	if (ret < 0)
		return;

	intel_write_infoframe(encoder, &frame);
}

Contributors
Person Tokens Prop Commits CommitProp
damien lespiau damien lespiau 52 98.11% 1 50.00%
ville syrjala ville syrjala 1 1.89% 1 50.00%
Total 53 100.00% 2 100.00%



static void g4x_set_infoframes(struct drm_encoder *encoder,
			       bool enable,
			       const struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	i915_reg_t reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);

	assert_hdmi_port_disabled(intel_hdmi);

	/* If the registers were not initialized yet, they might be zeroes,
         * which means we're selecting the AVI DIP and we're setting its
         * frequency to once. This seems to really confuse the HW and make
         * things stop working (the register spec says the AVI always needs to
         * be sent every VSync). So here we avoid writing to the register more
         * than we need and also explicitly select the AVI DIP and explicitly
         * set its frequency to every VSync. Avoiding to write it twice seems to
         * be enough to solve the problem, but being defensive shouldn't hurt us
         * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!enable) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		if (port != (val & VIDEO_DIP_PORT_MASK)) {
			DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
				      (val & VIDEO_DIP_PORT_MASK) >> 29);
			return;
		}
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}

	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
				      (val & VIDEO_DIP_PORT_MASK) >> 29);
			return;
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);

	I915_WRITE(reg, val);
	POSTING_READ(reg);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 155 63.27% 7 43.75%
ville syrjala ville syrjala 71 28.98% 5 31.25%
daniel vetter daniel vetter 9 3.67% 2 12.50%
damien lespiau damien lespiau 7 2.86% 1 6.25%
chris wilson chris wilson 3 1.22% 1 6.25%
Total 245 100.00% 16 100.00%



static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_connector *connector;

	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

	/*
         * HDMI cloning is only supported on g4x which doesn't
         * support deep color or GCP infoframes anyway so no
         * need to worry about multiple HDMI sinks here.
         */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		if (connector->encoder == encoder)
			return connector->display_info.bpc > 8;

	return false;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 68 100.00% 1 100.00%
Total 68 100.00% 1 100.00%

/*
 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 *
 * From HDMI specification 1.4a:
 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 *   phase of 0
 */


static bool gcp_default_phase_possible(int pipe_bpp,
				       const struct drm_display_mode *mode)
{
	unsigned int pixels_per_group;

	switch (pipe_bpp) {
	case 30:
		/* 4 pixels in 5 clocks */
		pixels_per_group = 4;
		break;
	case 36:
		/* 2 pixels in 3 clocks */
		pixels_per_group = 2;
		break;
	case 48:
		/* 1 pixel in 2 clocks */
		pixels_per_group = 1;
		break;
	default:
		/* phase information not relevant for 8bpc */
		return false;
	}

	return mode->crtc_hdisplay % pixels_per_group == 0 &&
		mode->crtc_htotal % pixels_per_group == 0 &&
		mode->crtc_hblank_start % pixels_per_group == 0 &&
		mode->crtc_hblank_end % pixels_per_group == 0 &&
		mode->crtc_hsync_start % pixels_per_group == 0 &&
		mode->crtc_hsync_end % pixels_per_group == 0 &&
		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
		 mode->crtc_htotal/2 % pixels_per_group == 0);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 128 100.00% 1 100.00%
Total 128 100.00% 1 100.00%



static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	i915_reg_t reg;
	u32 val = 0;

	if (HAS_DDI(dev_priv))
		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
	else if (HAS_PCH_SPLIT(dev_priv))
		reg = TVIDEO_DIP_GCP(crtc->pipe);
	else
		return false;

	/* Indicate color depth whenever the sink supports deep color */
	if (hdmi_sink_is_deep_color(encoder))
		val |= GCP_COLOR_INDICATION;

	/* Enable default_phase whenever the display mode is suitably aligned */
	if (gcp_default_phase_possible(crtc->config->pipe_bpp,
				       &crtc->config->base.adjusted_mode))
		val |= GCP_DEFAULT_PHASE_ENABLE;

	I915_WRITE(reg, val);

	return val != 0;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 145 94.77% 3 60.00%
wayne boyer wayne boyer 5 3.27% 1 20.00%
chris wilson chris wilson 3 1.96% 1 20.00%
Total 153 100.00% 5 100.00%



static void ibx_set_infoframes(struct drm_encoder *encoder,
			       bool enable,
			       const struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);

	assert_hdmi_port_disabled(intel_hdmi);

	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!enable) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}

	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		WARN(val & VIDEO_DIP_ENABLE,
		     "DIP already enabled on port %c\n",
		     (val & VIDEO_DIP_PORT_MASK) >> 29);
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

	I915_WRITE(reg, val);
	POSTING_READ(reg);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 172 68.80% 7 41.18%
ville syrjala ville syrjala 59 23.60% 6 35.29%
daniel vetter daniel vetter 9 3.60% 2 11.76%
damien lespiau damien lespiau 7 2.80% 1 5.88%
chris wilson chris wilson 3 1.20% 1 5.88%
Total 250 100.00% 17 100.00%



static void cpt_set_infoframes(struct drm_encoder *encoder,
			       bool enable,
			       const struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

	assert_hdmi_port_disabled(intel_hdmi);

	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!enable) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}

	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

	I915_WRITE(reg, val);
	POSTING_READ(reg);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 151 78.24% 5 38.46%
ville syrjala ville syrjala 23 11.92% 4 30.77%
daniel vetter daniel vetter 9 4.66% 2 15.38%
damien lespiau damien lespiau 7 3.63% 1 7.69%
chris wilson chris wilson 3 1.55% 1 7.69%
Total 193 100.00% 13 100.00%



static void vlv_set_infoframes(struct drm_encoder *encoder,
			       bool enable,
			       const struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);

	assert_hdmi_port_disabled(intel_hdmi);

	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!enable) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}

	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		WARN(val & VIDEO_DIP_ENABLE,
		     "DIP already enabled on port %c\n",
		     (val & VIDEO_DIP_PORT_MASK) >> 29);
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

	I915_WRITE(reg, val);
	POSTING_READ(reg);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 144 57.60% 5 33.33%
jesse barnes jesse barnes 50 20.00% 2 13.33%
ville syrjala ville syrjala 37 14.80% 4 26.67%
daniel vetter daniel vetter 9 3.60% 2 13.33%
damien lespiau damien lespiau 7 2.80% 1 6.67%
chris wilson chris wilson 3 1.20% 1 6.67%
Total 250 100.00% 15 100.00%



static void hsw_set_infoframes(struct drm_encoder *encoder,
			       bool enable,
			       const struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
	u32 val = I915_READ(reg);

	assert_hdmi_port_disabled(intel_hdmi);

	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);

	if (!enable) {
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}

	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP_HSW;

	I915_WRITE(reg, val);
	POSTING_READ(reg);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 105 66.46% 4 26.67%
ville syrjala ville syrjala 31 19.62% 4 26.67%
daniel vetter daniel vetter 10 6.33% 3 20.00%
damien lespiau damien lespiau 7 4.43% 1 6.67%
chris wilson chris wilson 3 1.90% 1 6.67%
ander conselvan de oliveira ander conselvan de oliveira 1 0.63% 1 6.67%
rodrigo vivi rodrigo vivi 1 0.63% 1 6.67%
Total 158 100.00% 15 100.00%



void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
	struct i2c_adapter *adapter =
		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);

	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
		return;

	DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
		      enable ? "Enabling" : "Disabling");

	drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
					 adapter, enable);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 75 100.00% 1 100.00%
Total 75 100.00% 1 100.00%



static void intel_hdmi_prepare(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
	u32 hdmi_val;

	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);

	hdmi_val = SDVO_ENCODING_HDMI;
	if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
		hdmi_val |= HDMI_COLOR_RANGE_16_235;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;

	if (crtc->config->pipe_bpp > 24)
		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
	else
		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;

	if (crtc->config->has_hdmi_sink)
		hdmi_val |= HDMI_MODE_SELECT_HDMI;

	if (HAS_PCH_CPT(dev_priv))
		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
	else if (IS_CHERRYVIEW(dev_priv))
		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
	else
		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);

	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
	POSTING_READ(intel_hdmi->hdmi_reg);
}

Contributors
Person Tokens Prop Commits CommitProp
eric anholt eric anholt 69 31.36% 1 4.00%
daniel vetter daniel vetter 28 12.73% 4 16.00%
jesse barnes jesse barnes 24 10.91% 3 12.00%
paulo zanoni paulo zanoni 24 10.91% 4 16.00%
adam jackson adam jackson 20 9.09% 1 4.00%
chon ming lee chon ming lee 16 7.27% 1 4.00%
ville syrjala ville syrjala 15 6.82% 3 12.00%
chris wilson chris wilson 10 4.55% 3 12.00%
zhenyu wang zhenyu wang 6 2.73% 1 4.00%
ander conselvan de oliveira ander conselvan de oliveira 5 2.27% 2 8.00%
tvrtko ursulin tvrtko ursulin 3 1.36% 2 8.00%
Total 220 100.00% 25 100.00%



static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	enum intel_display_power_domain power_domain;
	u32 tmp;
	bool ret;

	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
		return false;

	ret = false;

	tmp = I915_READ(intel_hdmi->hdmi_reg);

	if (!(tmp & SDVO_ENABLE))
		goto out;

	if (HAS_PCH_CPT(dev_priv))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else if (IS_CHERRYVIEW(dev_priv))
		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);

	ret = true;

out:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
}

Contributors
Person Tokens Prop Commits CommitProp
daniel vetter daniel vetter 60 37.27% 1 10.00%
imre deak imre deak 48 29.81% 2 20.00%
eric anholt eric anholt 29 18.01% 1 10.00%
ville syrjala ville syrjala 15 9.32% 1 10.00%
chris wilson chris wilson 6 3.73% 2 20.00%
tvrtko ursulin tvrtko ursulin 2 1.24% 2 20.00%
paulo zanoni paulo zanoni 1 0.62% 1 10.00%
Total 161 100.00% 10 100.00%



static void intel_hdmi_get_config(struct intel_encoder *encoder,
				  struct intel_crtc_state *pipe_config)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 tmp, flags = 0;
	int dotclock;

	tmp = I915_READ(intel_hdmi->hdmi_reg);

	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;

	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	if (tmp & HDMI_MODE_SELECT_HDMI)
		pipe_config->has_hdmi_sink = true;

	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
		pipe_config->has_infoframe = true;

	if (tmp & SDVO_AUDIO_ENABLE)
		pipe_config->has_audio = true;

	if (!HAS_PCH_SPLIT(dev_priv) &&
	    tmp & HDMI_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

	pipe_config->base.adjusted_mode.flags |= flags;

	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;

	if (pipe_config->pixel_multiplier)
		dotclock /= pipe_config->pixel_multiplier;

	pipe_config->base.adjusted_mode.crtc_clock = dotclock;

	pipe_config->lane_count = 4;
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 109 48.23% 2 13.33%
ville syrjala ville syrjala 77 34.07% 4 26.67%
daniel vetter daniel vetter 23 10.18% 2 13.33%
ander conselvan de oliveira ander conselvan de oliveira 11 4.87% 3 20.00%
chris wilson chris wilson 3 1.33% 1 6.67%
tvrtko ursulin tvrtko ursulin 1 0.44% 1 6.67%
damien lespiau damien lespiau 1 0.44% 1 6.67%
jani nikula jani nikula 1 0.44% 1 6.67%
Total 226 100.00% 15 100.00%



static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
				    struct intel_crtc_state *pipe_config,
				    struct drm_connector_state *conn_state)
{
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	WARN_ON(!crtc->config->has_hdmi_sink);
	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
			 pipe_name(crtc->pipe));
	intel_audio_codec_enable(encoder, pipe_config, conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 52 78.79% 1 33.33%
maarten lankhorst maarten lankhorst 14 21.21% 2 66.67%
Total 66 100.00% 3 100.00%



static void g4x_enable_hdmi(struct intel_encoder *encoder,
			    struct intel_crtc_state *pipe_config,
			    struct drm_connector_state *conn_state)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);

	temp |= SDVO_ENABLE;
	if (pipe_config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;

	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	if (pipe_config->has_audio)
		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
eric anholt eric anholt 39 34.82% 1 9.09%
ville syrjala ville syrjala 31 27.68% 1 9.09%
maarten lankhorst maarten lankhorst 16 14.29% 2 18.18%
daniel vetter daniel vetter 9 8.04% 2 18.18%
fengguang wu fengguang wu 8 7.14% 1 9.09%
chris wilson chris wilson 7 6.25% 2 18.18%
ander conselvan de oliveira ander conselvan de oliveira 1 0.89% 1 9.09%
paulo zanoni paulo zanoni 1 0.89% 1 9.09%
Total 112 100.00% 11 100.00%



static void ibx_enable_hdmi(struct intel_encoder *encoder,
			    struct intel_crtc_state *pipe_config,
			    struct drm_connector_state *conn_state)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);

	temp |= SDVO_ENABLE;
	if (crtc->config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;

	/*
         * HW workaround, need to write this twice for issue
         * that may result in first write getting masked.
         */
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	/*
         * HW workaround, need to toggle enable bit off and on
         * for 12bpc with pixel repeat.
         *
         * FIXME: BSpec says this should be done at the end of
         * of the modeset sequence, so not sure if this isn't too soon.
         */
	if (pipe_config->pipe_bpp > 24 &&
	    pipe_config->pixel_multiplier > 1) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);

		/*
                 * HW workaround, need to write this twice for issue
                 * that may result in first write getting masked.
                 */
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}

	if (pipe_config->has_audio)
		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 124 57.94% 2 18.18%
daniel vetter daniel vetter 57 26.64% 2 18.18%
maarten lankhorst maarten lankhorst 17 7.94% 2 18.18%
paulo zanoni paulo zanoni 7 3.27% 2 18.18%
jani nikula jani nikula 5 2.34% 1 9.09%
chris wilson chris wilson 3 1.40% 1 9.09%
ander conselvan de oliveira ander conselvan de oliveira 1 0.47% 1 9.09%
Total 214 100.00% 11 100.00%



static void cpt_enable_hdmi(struct intel_encoder *encoder,
			    struct intel_crtc_state *pipe_config,
			    struct drm_connector_state *conn_state)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	enum pipe pipe = crtc->pipe;
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);

	temp |= SDVO_ENABLE;
	if (pipe_config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;

	/*
         * WaEnableHDMI8bpcBefore12bpc:snb,ivb
         *
         * The procedure for 12bpc is as follows:
         * 1. disable HDMI clock gating
         * 2. enable HDMI with 8bpc
         * 3. enable HDMI with 12bpc
         * 4. enable HDMI clock gating
         */

	if (pipe_config->pipe_bpp > 24) {
		I915_WRITE(TRANS_CHICKEN1(pipe),
			   I915_READ(TRANS_CHICKEN1(pipe)) |
			   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		temp &= ~SDVO_COLOR_FORMAT_MASK;
		temp |= SDVO_COLOR_FORMAT_8bpc;
	}

	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	if (pipe_config->pipe_bpp > 24) {
		temp &= ~SDVO_COLOR_FORMAT_MASK;
		temp |= HDMI_COLOR_FORMAT_12bpc;

		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);

		I915_WRITE(TRANS_CHICKEN1(pipe),
			   I915_READ(TRANS_CHICKEN1(pipe)) &
			   ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
	}

	if (pipe_config->has_audio)
		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 189 83.63% 1 16.67%
maarten lankhorst maarten lankhorst 18 7.96% 2 33.33%
jani nikula jani nikula 15 6.64% 1 16.67%
chris wilson chris wilson 3 1.33% 1 16.67%
ander conselvan de oliveira ander conselvan de oliveira 1 0.44% 1 16.67%
Total 226 100.00% 6 100.00%



static void vlv_enable_hdmi(struct intel_encoder *encoder,
			    struct intel_crtc_state *pipe_config,
			    struct drm_connector_state *conn_state)
{
}

Contributors
Person Tokens Prop Commits CommitProp
maarten lankhorst maarten lankhorst 10 50.00% 1 33.33%
jani nikula jani nikula 7 35.00% 1 33.33%
jesse barnes jesse barnes 3 15.00% 1 33.33%
Total 20 100.00% 3 100.00%



static void intel_disable_hdmi(struct intel_encoder *encoder,
			       struct intel_crtc_state *old_crtc_state,
			       struct drm_connector_state *old_conn_state)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);

	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	/*
         * HW workaround for IBX, we need to move the port
         * to transcoder A after disabling it to allow the
         * matching DP port to be enabled on transcoder A.
         */
	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
		/*
                 * We get CPU/PCH FIFO underruns on the other pipe when
                 * doing the workaround. Sweep them under the rug.
                 */
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

		temp &= ~SDVO_PIPE_B_SELECT;
		temp |= SDVO_ENABLE;
		/*
                 * HW workaround, need to write this twice for issue
                 * that may result in first write getting masked.
                 */
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);

		temp &= ~SDVO_ENABLE;
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);

		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
	}

	intel_hdmi->set_infoframes(&encoder->base, false, NULL);

	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 101 40.40% 5 33.33%
daniel vetter daniel vetter 95 38.00% 2 13.33%
jani nikula jani nikula 14 5.60% 1 6.67%
zhenyu wang zhenyu wang 13 5.20% 1 6.67%
maarten lankhorst maarten lankhorst 10 4.00% 1 6.67%
paulo zanoni paulo zanoni 7 2.80% 1 6.67%
chris wilson chris wilson 5 2.00% 2 13.33%
eric anholt eric anholt 4 1.60% 1 6.67%
tvrtko ursulin tvrtko ursulin 1 0.40% 1 6.67%
Total 250 100.00% 15 100.00%



static void g4x_disable_hdmi(struct intel_encoder *encoder,
			     struct intel_crtc_state *old_crtc_state,
			     struct drm_connector_state *old_conn_state)
{
	if (old_crtc_state->has_audio)
		intel_audio_codec_disable(encoder);

	intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 26 63.41% 1 33.33%
maarten lankhorst maarten lankhorst 15 36.59% 2 66.67%
Total 41 100.00% 3 100.00%



static void pch_disable_hdmi(struct intel_encoder *encoder,
			     struct intel_crtc_state *old_crtc_state,
			     struct drm_connector_state *old_conn_state)
{
	if (old_crtc_state->has_audio)
		intel_audio_codec_disable(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 21 65.62% 1 33.33%
maarten lankhorst maarten lankhorst 11 34.38% 2 66.67%
Total 32 100.00% 3 100.00%



static void pch_post_disable_hdmi(struct intel_encoder *encoder,
				  struct intel_crtc_state *old_crtc_state,
				  struct drm_connector_state *old_conn_state)
{
	intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 16 53.33% 1 50.00%
maarten lankhorst maarten lankhorst 14 46.67% 1 50.00%
Total 30 100.00% 2 100.00%



static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
{
	if (IS_G4X(dev_priv))
		return 165000;
	else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
		return 300000;
	else
		return 225000;
}

Contributors
Person Tokens Prop Commits CommitProp
daniel vetter daniel vetter 31 68.89% 1 33.33%
damien lespiau damien lespiau 8 17.78% 1 33.33%
ville syrjala ville syrjala 6 13.33% 1 33.33%
Total 45 100.00% 3 100.00%



static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
				 bool respect_downstream_limits)
{
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));

	if (respect_downstream_limits) {
		struct intel_connector *connector = hdmi->attached_connector;
		const struct drm_display_info *info = &connector->base.display_info;

		if (hdmi->dp_dual_mode.max_tmds_clock)
			max_tmds_clock = min(max_tmds_clock,
					     hdmi->dp_dual_mode.max_tmds_clock);

		if (info->max_tmds_clock)
			max_tmds_clock = min(max_tmds_clock,
					     info->max_tmds_clock);
		else if (!hdmi->has_hdmi_sink)
			max_tmds_clock = min(max_tmds_clock, 165000);
	}

	return max_tmds_clock;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 121 100.00% 2 100.00%
Total 121 100.00% 2 100.00%


static enum drm_mode_status

hdmi_port_clock_valid(struct intel_hdmi *hdmi,
		      int clock, bool respect_downstream_limits)
{
	struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));

	if (clock < 25000)
		return MODE_CLOCK_LOW;
	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
		return MODE_CLOCK_HIGH;

	/* BXT DPLL can't generate 223-240 MHz */
	if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
		return MODE_CLOCK_RANGE;

	/* CHV DPLL can't generate 216-240 MHz */
	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
		return MODE_CLOCK_RANGE;

	return MODE_OK;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 57 60.00% 4 44.44%
eric anholt eric anholt 20 21.05% 1 11.11%
tvrtko ursulin tvrtko ursulin 7 7.37% 1 11.11%
clint taylor clint taylor 7 7.37% 1 11.11%
damien lespiau damien lespiau 2 2.11% 1 11.11%
daniel vetter daniel vetter 2 2.11% 1 11.11%
Total 95 100.00% 9 100.00%


static enum drm_mode_status

intel_hdmi_mode_valid(struct drm_connector *connector,
		      struct drm_display_mode *mode)
{
	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
	struct drm_i915_private *dev_priv = to_i915(dev);
	enum drm_mode_status status;
	int clock;
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	clock = mode->clock;

	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
		clock *= 2;

	if (clock > max_dotclk)
		return MODE_CLOCK_HIGH;

	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		clock *= 2;

	/* check if we can do 8bpc */
	status = hdmi_port_clock_valid(hdmi, clock, true);

	/* if we can't do 8bpc we may still be able to do 12bpc */
	if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
		status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);

	return status;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 101 61.96% 1 25.00%
mika kahola mika kahola 37 22.70% 1 25.00%
eric anholt eric anholt 14 8.59% 1 25.00%
tvrtko ursulin tvrtko ursulin 11 6.75% 1 25.00%
Total 163 100.00% 4 100.00%



static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
{
	struct drm_device *dev = crtc_state->base.crtc->dev;

	if (HAS_GMCH_DISPLAY(to_i915(dev)))
		return false;

	/*
         * HDMI 12bpc affects the clocks, so it's only possible
         * when not cloning with other encoder types.
         */
	return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 36 76.60% 2 40.00%
ander conselvan de oliveira ander conselvan de oliveira 7 14.89% 1 20.00%
tvrtko ursulin tvrtko ursulin 3 6.38% 1 20.00%
sonika jindal sonika jindal 1 2.13% 1 20.00%
Total 47 100.00% 5 100.00%



bool intel_hdmi_compute_config(struct intel_encoder *encoder,
			       struct intel_crtc_state *pipe_config,
			       struct drm_connector_state *conn_state)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
	int clock_12bpc = clock_8bpc * 3 / 2;
	int desired_bpp;

	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;

	if (pipe_config->has_hdmi_sink)
		pipe_config->has_infoframe = true;

	if (intel_hdmi->color_range_auto) {
		/* See CEA-861-E - 5.1 Default Encoding Parameters */
		pipe_config->limited_color_range =
			pipe_config->has_hdmi_sink &&
			drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_hdmi->limited_color_range;
	}

	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
		pipe_config->pixel_multiplier = 2;
		clock_8bpc *= 2;
		clock_12bpc *= 2;
	}

	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
		pipe_config->has_pch_encoder = true;

	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
		pipe_config->has_audio = true;

	/*
         * HDMI is either 12 or 8, so if the display lets 10bpc sneak
         * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
         * outputs. We also need to check that the higher clock still fits
         * within limits.
         */
	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
	    hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
	    hdmi_12bpc_possible(pipe_config)) {
		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		desired_bpp = 12*3;

		/* Need to adjust the port link by 1.5x for 12bpc. */
		pipe_config->port_clock = clock_12bpc;
	} else {
		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		desired_bpp = 8*3;

		pipe_config->port_clock = clock_8bpc;
	}

	if (!pipe_config->bw_constrained) {
		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		pipe_config->pipe_bpp = desired_bpp;
	}

	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
				  false) != MODE_OK) {
		DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
		return false;
	}

	/* Set user selected PAR to incoming mode's member */
	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;

	pipe_config->lane_count = 4;

	return true;
}

Contributors
Person Tokens Prop Commits CommitProp
daniel vetter daniel vetter 164 49.40% 7 25.00%
ville syrjala ville syrjala 100 30.12% 10 35.71%
clint taylor clint taylor 16 4.82% 1 3.57%
eric anholt eric anholt 14 4.22% 1 3.57%
jesse barnes jesse barnes 12 3.61% 1 3.57%
ander conselvan de oliveira ander conselvan de oliveira 12 3.61% 4 14.29%
tvrtko ursulin tvrtko ursulin 7 2.11% 1 3.57%
maarten lankhorst maarten lankhorst 5 1.51% 1 3.57%
thierry reding thierry reding 1 0.30% 1 3.57%
damien lespiau damien lespiau 1 0.30% 1 3.57%
Total 332 100.00% 28 100.00%


static void

intel_hdmi_unset_edid(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);

	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	intel_hdmi->rgb_quant_range_selectable = false;

	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;

	kfree(to_intel_connector(connector)->detect_edid);
	to_intel_connector(connector)->detect_edid = NULL;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 52 70.27% 1 25.00%
ville syrjala ville syrjala 16 21.62% 1 25.00%
ling ma ling ma 5 6.76% 1 25.00%
eric anholt eric anholt 1 1.35% 1 25.00%
Total 74 100.00% 4 100.00%


static void

intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
	enum port port = hdmi_to_dig_port(hdmi)->port;
	struct i2c_adapter *adapter =
		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
	enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);

	/*
         * Type 1 DVI adaptors are not required to implement any
         * registers, so we can't always detect their presence.
         * Ideally we should be able to check the state of the
         * CONFIG1 pin, but no such luck on our hardware.
         *
         * The only method left to us is to check the VBT to see
         * if the port is a dual mode capable DP port. But let's
         * only do that when we sucesfully read the EDID, to avoid
         * confusing log messages about DP dual mode adaptors when
         * there's nothing connected to the port.
         */
	if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
		if (has_edid &&
		    intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
			DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
			type = DRM_DP_DUAL_MODE_TYPE1_DVI;
		} else {
			type = DRM_DP_DUAL_MODE_NONE;
		}
	}

	if (type == DRM_DP_DUAL_MODE_NONE)
		return;

	hdmi->dp_dual_mode.type = type;
	hdmi->dp_dual_mode.max_tmds_clock =
		drm_dp_dual_mode_max_tmds_clock(type, adapter);

	DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
		      drm_dp_get_dual_mode_type_name(type),
		      hdmi->dp_dual_mode.max_tmds_clock);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 151 99.34% 2 66.67%
chris wilson chris wilson 1 0.66% 1 33.33%
Total 152 100.00% 3 100.00%


static bool

intel_hdmi_set_edid(struct drm_connector *connector)
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct edid *edid;
	bool connected = false;

	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);

	edid = drm_get_edid(connector,
			    intel_gmbus_get_adapter(dev_priv,
			    intel_hdmi->ddc_bus));

	intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);

	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);

	to_intel_connector(connector)->detect_edid = edid;
	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
		intel_hdmi->rgb_quant_range_selectable =
			drm_rgb_quant_range_selectable(edid);

		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				intel_hdmi->force_audio == HDMI_AUDIO_ON;

		if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink =
				drm_detect_hdmi_monitor(edid);

		connected = true;
	}

	return connected;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 66 40.49% 6 30.00%
ling ma ling ma 29 17.79% 1 5.00%
ville syrjala ville syrjala 19 11.66% 4 20.00%
keith packard keith packard 11 6.75% 1 5.00%
zhenyu wang zhenyu wang 10 6.13% 2 10.00%
damien lespiau damien lespiau 7 4.29% 1 5.00%
fengguang wu fengguang wu 6 3.68% 1 5.00%
imre deak imre deak 6 3.68% 1 5.00%
daniel kurtz daniel kurtz 4 2.45% 1 5.00%
eric anholt eric anholt 3 1.84% 1 5.00%
paulo zanoni paulo zanoni 2 1.23% 1 5.00%
Total 163 100.00% 20 100.00%


static enum drm_connector_status

intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	enum drm_connector_status status;
	struct drm_i915_private *dev_priv = to_i915(connector->dev);

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);

	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);

	intel_hdmi_unset_edid(connector);

	if (intel_hdmi_set_edid(connector)) {
		struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);

		hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		status = connector_status_connected;
	} else
		status = connector_status_disconnected;

	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);

	return status;
}

Contributors
Person Tokens Prop Commits CommitProp
daniel vetter daniel vetter 29 27.10% 1 9.09%
chris wilson chris wilson 28 26.17% 2 18.18%
imre deak imre deak 18 16.82% 2 18.18%
sonika jindal sonika jindal 14 13.08% 2 18.18%
eric anholt eric anholt 8 7.48% 1 9.09%
keith packard keith packard 5 4.67% 1 9.09%
paulo zanoni paulo zanoni 4 3.74% 1 9.09%
ling ma ling ma 1 0.93% 1 9.09%
Total 107 100.00% 11 100.00%


static void

intel_hdmi_force(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);

	intel_hdmi_unset_edid(connector);

	if (connector->status != connector_status_connected)
		return;

	intel_hdmi_set_edid(connector);
	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 35 53.03% 3 50.00%
imre deak imre deak 17 25.76% 1 16.67%
eric anholt eric anholt 12 18.18% 1 16.67%
zhenyu wang zhenyu wang 2 3.03% 1 16.67%
Total 66 100.00% 6 100.00%



static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct edid *edid;

	edid = to_intel_connector(connector)->detect_edid;
	if (edid == NULL)
		return 0;

	return intel_connector_update_modes(connector, edid);
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 33 78.57% 3 75.00%
imre deak imre deak 9 21.43% 1 25.00%
Total 42 100.00% 4 100.00%


static bool

intel_hdmi_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
	struct edid *edid;

	edid = to_intel_connector(connector)->detect_edid;
	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
		has_audio = drm_detect_monitor_audio(edid);

	return has_audio;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 49 98.00% 2 66.67%
imre deak imre deak 1 2.00% 1 33.33%
Total 50 100.00% 3 100.00%


static int

intel_hdmi_set_property(struct drm_connector *connector,
			struct drm_property *property,
			uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	int ret;

	ret = drm_object_property_set_value(&connector->base, property, val);
	if (ret)
		return ret;

	if (property == dev_priv->force_audio_property) {
		enum hdmi_force_audio i = val;
		bool has_audio;

		if (i == intel_hdmi->force_audio)
			return 0;

		intel_hdmi->force_audio = i;

		if (i == HDMI_AUDIO_AUTO)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = (i == HDMI_AUDIO_ON);

		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;

		intel_hdmi->has_audio = has_audio;
		goto done;
	}

	if (property == dev_priv->broadcast_rgb_property) {
		bool old_auto = intel_hdmi->color_range_auto;
		bool old_range = intel_hdmi->limited_color_range;

		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_hdmi->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_hdmi->color_range_auto = false;
			intel_hdmi->limited_color_range = false;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_hdmi->color_range_auto = false;
			intel_hdmi->limited_color_range = true;
			break;
		default:
			return -EINVAL;
		}

		if (old_auto == intel_hdmi->color_range_auto &&
		    old_range == intel_hdmi->limited_color_range)
			return 0;

		goto done;
	}

	if (property == connector->dev->mode_config.aspect_ratio_property) {
		switch (val) {
		case DRM_MODE_PICTURE_ASPECT_NONE:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
			break;
		case DRM_MODE_PICTURE_ASPECT_4_3:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
			break;
		case DRM_MODE_PICTURE_ASPECT_16_9:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
			break;
		default:
			return -EINVAL;
		}
		goto done;
	}

	return -EINVAL;

done:
	if (intel_dig_port->base.base.crtc)
		intel_crtc_restore_mode(intel_dig_port->base.base.crtc);

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 176 51.92% 6 46.15%
vandana kannan vandana kannan 58 17.11% 1 7.69%
ville syrjala ville syrjala 48 14.16% 2 15.38%
daniel vetter daniel vetter 28 8.26% 1 7.69%
fengguang wu fengguang wu 13 3.83% 1 7.69%
paulo zanoni paulo zanoni 12 3.54% 1 7.69%
rob clark rob clark 4 1.18% 1 7.69%
Total 339 100.00% 13 100.00%



static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
				  struct intel_crtc_state *pipe_config,
				  struct drm_connector_state *conn_state)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	intel_hdmi_prepare(encoder);

	intel_hdmi->set_infoframes(&encoder->base,
				   pipe_config->has_hdmi_sink,
				   adjusted_mode);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 44 64.71% 1 12.50%
maarten lankhorst maarten lankhorst 12 17.65% 2 25.00%
daniel vetter daniel vetter 7 10.29% 2 25.00%
ander conselvan de oliveira ander conselvan de oliveira 4 5.88% 2 25.00%
ville syrjala ville syrjala 1 1.47% 1 12.50%
Total 68 100.00% 8 100.00%



static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
				struct intel_crtc_state *pipe_config,
				struct drm_connector_state *conn_state)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct intel_hdmi *intel_hdmi = &dport->hdmi;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	vlv_phy_pre_encoder_enable(encoder);

	/* HDMI 1.0V-2dB */
	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
				 0x2b247878);

	intel_hdmi->set_infoframes(&encoder->base,
				   pipe_config->has_hdmi_sink,
				   adjusted_mode);

	g4x_enable_hdmi(encoder, pipe_config, conn_state);

	vlv_wait_port_ready(dev_priv, dport, 0x0);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 72 54.96% 2 11.76%
ander conselvan de oliveira ander conselvan de oliveira 20 15.27% 4 23.53%
maarten lankhorst maarten lankhorst 16 12.21% 2 11.76%
jani nikula jani nikula 10 7.63% 1 5.88%
chris wilson chris wilson 5 3.82% 2 11.76%
ville syrjala ville syrjala 4 3.05% 3 17.65%
chon ming lee chon ming lee 2 1.53% 2 11.76%
daniel vetter daniel vetter 2 1.53% 1 5.88%
Total 131 100.00% 17 100.00%



static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
				    struct intel_crtc_state *pipe_config,
				    struct drm_connector_state *conn_state)
{
	intel_hdmi_prepare(encoder);

	vlv_phy_pre_pll_enable(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 11 35.48% 1 16.67%
maarten lankhorst maarten lankhorst 10 32.26% 1 16.67%
daniel vetter daniel vetter 5 16.13% 1 16.67%
chris wilson chris wilson 2 6.45% 1 16.67%
ander conselvan de oliveira ander conselvan de oliveira 2 6.45% 1 16.67%
chon ming lee chon ming lee 1 3.23% 1 16.67%
Total 31 100.00% 6 100.00%



static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
				    struct intel_crtc_state *pipe_config,
				    struct drm_connector_state *conn_state)
{
	intel_hdmi_prepare(encoder);

	chv_phy_pre_pll_enable(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 20 64.52% 3 60.00%
maarten lankhorst maarten lankhorst 10 32.26% 1 20.00%
ander conselvan de oliveira ander conselvan de oliveira 1 3.23% 1 20.00%
Total 31 100.00% 5 100.00%



static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
				      struct intel_crtc_state *old_crtc_state,
				      struct drm_connector_state *old_conn_state)
{
	chv_phy_post_pll_disable(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 15 57.69% 2 50.00%
maarten lankhorst maarten lankhorst 10 38.46% 1 25.00%
ander conselvan de oliveira ander conselvan de oliveira 1 3.85% 1 25.00%
Total 26 100.00% 4 100.00%



static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
				  struct intel_crtc_state *old_crtc_state,
				  struct drm_connector_state *old_conn_state)
{
	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
	vlv_phy_reset_lanes(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
maarten lankhorst maarten lankhorst 10 37.04% 1 16.67%
jesse barnes jesse barnes 9 33.33% 1 16.67%
ville syrjala ville syrjala 5 18.52% 2 33.33%
ander conselvan de oliveira ander conselvan de oliveira 2 7.41% 1 16.67%
chon ming lee chon ming lee 1 3.70% 1 16.67%
Total 27 100.00% 6 100.00%



static void chv_hdmi_post_disable(struct intel_encoder *encoder,
				  struct intel_crtc_state *old_crtc_state,
				  struct drm_connector_state *old_conn_state)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);

	mutex_unlock(&dev_priv->sb_lock);
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 53 80.30% 4 66.67%
maarten lankhorst maarten lankhorst 10 15.15% 1 16.67%
chris wilson chris wilson 3 4.55% 1 16.67%
Total 66 100.00% 6 100.00%



static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
				struct intel_crtc_state *pipe_config,
				struct drm_connector_state *conn_state)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct intel_hdmi *intel_hdmi = &dport->hdmi;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;

	chv_phy_pre_encoder_enable(encoder);

	/* FIXME: Program the support xxx V-dB */
	/* Use 800mV-0dB */
	chv_set_phy_signal_level(encoder, 128, 102, false);

	intel_hdmi->set_infoframes(&encoder->base,
				   intel_crtc->config->has_hdmi_sink,
				   adjusted_mode);

	g4x_enable_hdmi(encoder, pipe_config, conn_state);

	vlv_wait_port_ready(dev_priv, dport, 0x0);

	/* Second common lane will stay alive on its own now */
	chv_phy_release_cl2_override(encoder);
}

Contributors
Person Tokens Prop Commits CommitProp
chon ming lee chon ming lee 76 49.35% 1 6.67%
clint taylor clint taylor 38 24.68% 1 6.67%
maarten lankhorst maarten lankhorst 14 9.09% 1 6.67%
ville syrjala ville syrjala 13 8.44% 7 46.67%
ander conselvan de oliveira ander conselvan de oliveira 10 6.49% 4 26.67%
chris wilson chris wilson 3 1.95% 1 6.67%
Total 154 100.00% 15 100.00%



static void intel_hdmi_destroy(struct drm_connector *connector)
{
	kfree(to_intel_connector(connector)->detect_edid);
	drm_connector_cleanup(connector);
	kfree(connector);
}

Contributors
Person Tokens Prop Commits CommitProp
eric anholt eric anholt 20 64.52% 1 25.00%
chris wilson chris wilson 10 32.26% 2 50.00%
zhenyu wang zhenyu wang 1 3.23% 1 25.00%
Total 31 100.00% 4 100.00%


static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = drm_atomic_helper_connector_dpms,
	.detect = intel_hdmi_detect,
	.force = intel_hdmi_force,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.atomic_get_property = intel_connector_atomic_get_property,
	.late_register = intel_connector_register,
	.early_unregister = intel_connector_unregister,
	.destroy = intel_hdmi_destroy,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};


static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
};


static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};


static void

intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
	intel_hdmi->color_range_auto = true;
	intel_attach_aspect_ratio_property(connector);
	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
}

Contributors
Person Tokens Prop Commits CommitProp
chris wilson chris wilson 26 60.47% 3 60.00%
vandana kannan vandana kannan 11 25.58% 1 20.00%
ville syrjala ville syrjala 6 13.95% 1 20.00%
Total 43 100.00% 5 100.00%



static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
			     enum port port)
{
	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[port];
	u8 ddc_pin;

	if (info->alternate_ddc_pin) {
		DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
			      info->alternate_ddc_pin, port_name(port));
		return info->alternate_ddc_pin;
	}

	switch (port) {
	case PORT_B:
		if (IS_BROXTON(dev_priv))
			ddc_pin = GMBUS_PIN_1_BXT;
		else
			ddc_pin = GMBUS_PIN_DPB;
		break;
	case PORT_C:
		if (IS_BROXTON(dev_priv))
			ddc_pin = GMBUS_PIN_2_BXT;
		else
			ddc_pin = GMBUS_PIN_DPC;
		break;
	case PORT_D:
		if (IS_CHERRYVIEW(dev_priv))
			ddc_pin = GMBUS_PIN_DPD_CHV;
		else
			ddc_pin = GMBUS_PIN_DPD;
		break;
	default:
		MISSING_CASE(port);
		ddc_pin = GMBUS_PIN_DPB;
		break;
	}

	DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
		      ddc_pin, port_name(port));

	return ddc_pin;
}

Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 153 100.00% 1 100.00%
Total 153 100.00% 1 100.00%



void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	enum port port = intel_dig_port->port;

	DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
		      port_name(port));

	if (WARN(intel_dig_port->max_lanes < 4,
		 "Not enough lanes (%d) for HDMI on port %c\n",
		 intel_dig_port->max_lanes, port_name(port)))
		return;

	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;
	connector->stereo_allowed = 1;

	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);

	switch (port) {
	case PORT_B:
		/*
                 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
                 * interrupts to check the external panel connection.
                 */
		if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
			intel_encoder->hpd_pin = HPD_PORT_A;
		else
			intel_encoder->hpd_pin = HPD_PORT_B;
		break;
	case PORT_C:
		intel_encoder->hpd_pin = HPD_PORT_C;
		break;
	case PORT_D:
		intel_encoder->hpd_pin = HPD_PORT_D;
		break;
	case PORT_E:
		intel_encoder->hpd_pin = HPD_PORT_E;
		break;
	default:
		MISSING_CASE(port);
		return;
	}

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		intel_hdmi->write_infoframe = vlv_write_infoframe;
		intel_hdmi->set_infoframes = vlv_set_infoframes;
		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
	} else if (IS_G4X(dev_priv)) {
		intel_hdmi->write_infoframe = g4x_write_infoframe;
		intel_hdmi->set_infoframes = g4x_set_infoframes;
		intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
	} else if (HAS_DDI(dev_priv)) {
		intel_hdmi->write_infoframe = hsw_write_infoframe;
		intel_hdmi->set_infoframes = hsw_set_infoframes;
		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
	} else if (HAS_PCH_IBX(dev_priv)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
		intel_hdmi->set_infoframes = ibx_set_infoframes;
		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
		intel_hdmi->set_infoframes = cpt_set_infoframes;
		intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
	}

	if (HAS_DDI(dev_priv))
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
	intel_hdmi->attached_connector = intel_connector;

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
         * 0xd.  Failure to do so will result in spurious interrupts being
         * generated on the port when a cable is not attached.
         */
	if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}

Contributors
Person Tokens Prop Commits CommitProp
paulo zanoni paulo zanoni 162 36.57% 8 18.18%
jesse barnes jesse barnes 55 12.42% 4 9.09%
ville syrjala ville syrjala 49 11.06% 3 6.82%
eric anholt eric anholt 42 9.48% 2 4.55%
eugeni dodonov eugeni dodonov 19 4.29% 3 6.82%
egbert eich egbert eich 18 4.06% 1 2.27%
sonika jindal sonika jindal 14 3.16% 2 4.55%
daniel vetter daniel vetter 14 3.16% 1 2.27%
shobhit kumar shobhit kumar 13 2.93% 1 2.27%
chris wilson chris wilson 12 2.71% 3 6.82%
xiong zhang xiong zhang 9 2.03% 1 2.27%
tvrtko ursulin tvrtko ursulin 8 1.81% 5 11.36%
shashank sharma shashank sharma 6 1.35% 1 2.27%
jani nikula jani nikula 6 1.35% 2 4.55%
damien lespiau damien lespiau 6 1.35% 1 2.27%
wayne boyer wayne boyer 4 0.90% 1 2.27%
zhenyu wang zhenyu wang 3 0.68% 2 4.55%
peter ross peter ross 1 0.23% 1 2.27%
ling ma ling ma 1 0.23% 1 2.27%
adam jackson adam jackson 1 0.23% 1 2.27%
Total 443 100.00% 44 100.00%



void intel_hdmi_init(struct drm_device *dev,
		     i915_reg_t hdmi_reg, enum port port)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;

	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;

	intel_connector = intel_connector_alloc();
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));

	intel_encoder->compute_config = intel_hdmi_compute_config;
	if (HAS_PCH_SPLIT(dev_priv)) {
		intel_encoder->disable = pch_disable_hdmi;
		intel_encoder->post_disable = pch_post_disable_hdmi;
	} else {
		intel_encoder->disable = g4x_disable_hdmi;
	}
	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
	intel_encoder->get_config = intel_hdmi_get_config;
	if (IS_CHERRYVIEW(dev_priv)) {
		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
		intel_encoder->pre_enable = chv_hdmi_pre_enable;
		intel_encoder->enable = vlv_enable_hdmi;
		intel_encoder->post_disable = chv_hdmi_post_disable;
		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
		intel_encoder->enable = vlv_enable_hdmi;
		intel_encoder->post_disable = vlv_hdmi_post_disable;
	} else {
		intel_encoder->pre_enable = intel_hdmi_pre_enable;
		if (HAS_PCH_CPT(dev_priv))
			intel_encoder->enable = cpt_enable_hdmi;
		else if (HAS_PCH_IBX(dev_priv))
			intel_encoder->enable = ibx_enable_hdmi;
		else
			intel_encoder->enable = g4x_enable_hdmi;
	}

	intel_encoder->type = INTEL_OUTPUT_HDMI;
	intel_encoder->port = port;
	if (IS_CHERRYVIEW(dev_priv)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
	/*
         * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
         * to work on real hardware. And since g4x can send infoframes to
         * only one port anyway, nothing is lost by allowing it.
         */
	if (IS_G4X(dev_priv))
		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;

	intel_dig_port->port = port;
	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
	intel_dig_port->max_lanes = 4;

	intel_hdmi_init_connector(intel_dig_port, intel_connector);
}
Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 144 35.29% 13 37.14%
paulo zanoni paulo zanoni 135 33.09% 3 8.57%
jesse barnes jesse barnes 34 8.33% 3 8.57%
chon ming lee chon ming lee 24 5.88% 2 5.71%
daniel vetter daniel vetter 22 5.39% 4 11.43%
tvrtko ursulin tvrtko ursulin 17 4.17% 4 11.43%
jani nikula jani nikula 15 3.68% 1 2.86%
eric anholt eric anholt 8 1.96% 2 5.71%
dhinakaran pandiyan dhinakaran pandiyan 6 1.47% 1 2.86%
ander conselvan de oliveira ander conselvan de oliveira 2 0.49% 1 2.86%
chris wilson chris wilson 1 0.25% 1 2.86%
Total 408 100.00% 35 100.00%

Overall Contributors
Person Tokens Prop Commits CommitProp
ville syrjala ville syrjala 2757 31.13% 59 24.18%
paulo zanoni paulo zanoni 1773 20.02% 30 12.30%
jesse barnes jesse barnes 911 10.29% 16 6.56%
daniel vetter daniel vetter 706 7.97% 24 9.84%
chris wilson chris wilson 641 7.24% 17 6.97%
damien lespiau damien lespiau 368 4.15% 9 3.69%
eric anholt eric anholt 355 4.01% 3 1.23%
maarten lankhorst maarten lankhorst 223 2.52% 5 2.05%
shobhit kumar shobhit kumar 134 1.51% 1 0.41%
chon ming lee chon ming lee 120 1.35% 4 1.64%
imre deak imre deak 99 1.12% 4 1.64%
jani nikula jani nikula 93 1.05% 7 2.87%
ander conselvan de oliveira ander conselvan de oliveira 89 1.00% 15 6.15%
vandana kannan vandana kannan 69 0.78% 1 0.41%
david hardeman david hardeman 69 0.78% 1 0.41%
clint taylor clint taylor 61 0.69% 2 0.82%
tvrtko ursulin tvrtko ursulin 61 0.69% 8 3.28%
mika kahola mika kahola 37 0.42% 1 0.41%
ling ma ling ma 36 0.41% 2 0.82%
zhenyu wang zhenyu wang 35 0.40% 6 2.46%
eugeni dodonov eugeni dodonov 35 0.40% 3 1.23%
sonika jindal sonika jindal 29 0.33% 5 2.05%
fengguang wu fengguang wu 27 0.30% 2 0.82%
keith packard keith packard 22 0.25% 2 0.82%
adam jackson adam jackson 21 0.24% 2 0.82%
egbert eich egbert eich 18 0.20% 1 0.41%
matt roper matt roper 13 0.15% 2 0.82%
xiong zhang xiong zhang 9 0.10% 1 0.41%
wayne boyer wayne boyer 9 0.10% 1 0.41%
shashank sharma shashank sharma 6 0.07% 1 0.41%
dhinakaran pandiyan dhinakaran pandiyan 6 0.07% 1 0.41%
rodrigo vivi rodrigo vivi 6 0.07% 1 0.41%
daniel kurtz daniel kurtz 4 0.05% 1 0.41%
rob clark rob clark 4 0.05% 1 0.41%
david howells david howells 4 0.05% 1 0.41%
tejun heo tejun heo 3 0.03% 1 0.41%
antti koskipaa antti koskipaa 2 0.02% 1 0.41%
thierry reding thierry reding 1 0.01% 1 0.41%
peter ross peter ross 1 0.01% 1 0.41%
Total 8857 100.00% 244 100.00%
Directory: drivers/gpu/drm/i915

Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.
	Person	Tokens	Prop	Commits	CommitProp
paulo zanoni	paulo zanoni	25	100.00%	2	100.00%
	Total	25	100.00%	2	100.00%
cregit-Linux how code gets into the kernel

Release 4.10 drivers/gpu/drm/i915/intel_hdmi.c

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