Release 4.10 drivers/pci/host/pci-exynos.c

Directory: drivers/pci/host
/*
 * PCIe host controller driver for Samsung EXYNOS SoCs
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * Author: Jingoo Han <jg1.han@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>

#include "pcie-designware.h"


#define to_exynos_pcie(x)	container_of(x, struct exynos_pcie, pp)


struct exynos_pcie {
	
struct pcie_port	pp;
	
void __iomem		*elbi_base;	/* DT 0th resource */
	
void __iomem		*phy_base;	/* DT 1st resource */
	
void __iomem		*block_base;	/* DT 2nd resource */
	
int			reset_gpio;
	
struct clk		*clk;
	
struct clk		*bus_clk;
};

/* PCIe ELBI registers */

#define PCIE_IRQ_PULSE			0x000

#define IRQ_INTA_ASSERT			(0x1 << 0)

#define IRQ_INTB_ASSERT			(0x1 << 2)

#define IRQ_INTC_ASSERT			(0x1 << 4)

#define IRQ_INTD_ASSERT			(0x1 << 6)

#define PCIE_IRQ_LEVEL			0x004

#define PCIE_IRQ_SPECIAL		0x008

#define PCIE_IRQ_EN_PULSE		0x00c

#define PCIE_IRQ_EN_LEVEL		0x010

#define IRQ_MSI_ENABLE			(0x1 << 2)

#define PCIE_IRQ_EN_SPECIAL		0x014

#define PCIE_PWR_RESET			0x018

#define PCIE_CORE_RESET			0x01c

#define PCIE_CORE_RESET_ENABLE		(0x1 << 0)

#define PCIE_STICKY_RESET		0x020

#define PCIE_NONSTICKY_RESET		0x024

#define PCIE_APP_INIT_RESET		0x028

#define PCIE_APP_LTSSM_ENABLE		0x02c

#define PCIE_ELBI_RDLH_LINKUP		0x064

#define PCIE_ELBI_LTSSM_ENABLE		0x1

#define PCIE_ELBI_SLV_AWMISC		0x11c

#define PCIE_ELBI_SLV_ARMISC		0x120

#define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)

/* PCIe Purple registers */

#define PCIE_PHY_GLOBAL_RESET		0x000

#define PCIE_PHY_COMMON_RESET		0x004

#define PCIE_PHY_CMN_REG		0x008

#define PCIE_PHY_MAC_RESET		0x00c

#define PCIE_PHY_PLL_LOCKED		0x010

#define PCIE_PHY_TRSVREG_RESET		0x020

#define PCIE_PHY_TRSV_RESET		0x024

/* PCIe PHY registers */

#define PCIE_PHY_IMPEDANCE		0x004

#define PCIE_PHY_PLL_DIV_0		0x008

#define PCIE_PHY_PLL_BIAS		0x00c

#define PCIE_PHY_DCC_FEEDBACK		0x014

#define PCIE_PHY_PLL_DIV_1		0x05c

#define PCIE_PHY_COMMON_POWER		0x064

#define PCIE_PHY_COMMON_PD_CMN		(0x1 << 3)

#define PCIE_PHY_TRSV0_EMP_LVL		0x084

#define PCIE_PHY_TRSV0_DRV_LVL		0x088

#define PCIE_PHY_TRSV0_RXCDR		0x0ac

#define PCIE_PHY_TRSV0_POWER		0x0c4

#define PCIE_PHY_TRSV0_PD_TSV		(0x1 << 7)

#define PCIE_PHY_TRSV0_LVCC		0x0dc

#define PCIE_PHY_TRSV1_EMP_LVL		0x144

#define PCIE_PHY_TRSV1_RXCDR		0x16c

#define PCIE_PHY_TRSV1_POWER		0x184

#define PCIE_PHY_TRSV1_PD_TSV		(0x1 << 7)

#define PCIE_PHY_TRSV1_LVCC		0x19c

#define PCIE_PHY_TRSV2_EMP_LVL		0x204

#define PCIE_PHY_TRSV2_RXCDR		0x22c

#define PCIE_PHY_TRSV2_POWER		0x244

#define PCIE_PHY_TRSV2_PD_TSV		(0x1 << 7)

#define PCIE_PHY_TRSV2_LVCC		0x25c

#define PCIE_PHY_TRSV3_EMP_LVL		0x2c4

#define PCIE_PHY_TRSV3_RXCDR		0x2ec

#define PCIE_PHY_TRSV3_POWER		0x304

#define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)

#define PCIE_PHY_TRSV3_LVCC		0x31c



static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
{
	writel(val, exynos_pcie->elbi_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 26 92.86% 1 50.00%
bjorn helgaas bjorn helgaas 2 7.14% 1 50.00%
Total 28 100.00% 2 100.00%



static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
{
	return readl(exynos_pcie->elbi_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 22 91.67% 1 50.00%
bjorn helgaas bjorn helgaas 2 8.33% 1 50.00%
Total 24 100.00% 2 100.00%



static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
{
	writel(val, exynos_pcie->phy_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 26 92.86% 1 50.00%
bjorn helgaas bjorn helgaas 2 7.14% 1 50.00%
Total 28 100.00% 2 100.00%



static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
{
	return readl(exynos_pcie->phy_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 22 91.67% 1 50.00%
bjorn helgaas bjorn helgaas 2 8.33% 1 50.00%
Total 24 100.00% 2 100.00%



static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
{
	writel(val, exynos_pcie->block_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 26 92.86% 1 50.00%
bjorn helgaas bjorn helgaas 2 7.14% 1 50.00%
Total 28 100.00% 2 100.00%



static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
{
	return readl(exynos_pcie->block_base + reg);
}

Contributors
Person Tokens Prop Commits CommitProp
seungwon jeon seungwon jeon 22 91.67% 1 50.00%
bjorn helgaas bjorn helgaas 2 8.33% 1 50.00%
Total 24 100.00% 2 100.00%



static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,
					    bool on)
{
	u32 val;

	if (on) {
		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
		val |= PCIE_ELBI_SLV_DBI_ENABLE;
		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
	} else {
		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
	}
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 59 83.10% 1 33.33%
seungwon jeon seungwon jeon 10 14.08% 1 33.33%
bjorn helgaas bjorn helgaas 2 2.82% 1 33.33%
Total 71 100.00% 3 100.00%



static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos_pcie,
					    bool on)
{
	u32 val;

	if (on) {
		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
		val |= PCIE_ELBI_SLV_DBI_ENABLE;
		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
	} else {
		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
	}
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 59 83.10% 1 33.33%
seungwon jeon seungwon jeon 10 14.08% 1 33.33%
bjorn helgaas bjorn helgaas 2 2.82% 1 33.33%
Total 71 100.00% 3 100.00%



static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
	val &= ~PCIE_CORE_RESET_ENABLE;
	exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
	exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
	exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
	exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 47 73.44% 1 33.33%
seungwon jeon seungwon jeon 15 23.44% 1 33.33%
bjorn helgaas bjorn helgaas 2 3.12% 1 33.33%
Total 64 100.00% 3 100.00%



static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
	val |= PCIE_CORE_RESET_ENABLE;

	exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
	exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
	exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
	exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
	exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 58 71.60% 1 33.33%
seungwon jeon seungwon jeon 21 25.93% 1 33.33%
bjorn helgaas bjorn helgaas 2 2.47% 1 33.33%
Total 81 100.00% 3 100.00%



static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos_pcie)
{
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 21 72.41% 1 33.33%
seungwon jeon seungwon jeon 6 20.69% 1 33.33%
bjorn helgaas bjorn helgaas 2 6.90% 1 33.33%
Total 29 100.00% 3 100.00%



static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos_pcie)
{
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
	exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 45 69.23% 1 33.33%
seungwon jeon seungwon jeon 18 27.69% 1 33.33%
bjorn helgaas bjorn helgaas 2 3.08% 1 33.33%
Total 65 100.00% 3 100.00%



static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
	val &= ~PCIE_PHY_COMMON_PD_CMN;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
	val &= ~PCIE_PHY_TRSV0_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
	val &= ~PCIE_PHY_TRSV1_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
	val &= ~PCIE_PHY_TRSV2_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
	val &= ~PCIE_PHY_TRSV3_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 127 98.45% 1 50.00%
bjorn helgaas bjorn helgaas 2 1.55% 1 50.00%
Total 129 100.00% 2 100.00%



static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
	val |= PCIE_PHY_COMMON_PD_CMN;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
	val |= PCIE_PHY_TRSV0_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
	val |= PCIE_PHY_TRSV1_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
	val |= PCIE_PHY_TRSV2_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);

	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
	val |= PCIE_PHY_TRSV3_PD_TSV;
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 122 98.39% 1 50.00%
bjorn helgaas bjorn helgaas 2 1.61% 1 50.00%
Total 124 100.00% 2 100.00%



static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie)
{
	/* DCC feedback control off */
	exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);

	/* set TX/RX impedance */
	exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);

	/* set 50Mhz PHY clock */
	exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
	exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);

	/* set TX Differential output for lane 0 */
	exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);

	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
	exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);

	/* set RX clock and data recovery bandwidth */
	exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);

	/* change TX Pre-emphasis Level Control for lanes */
	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);

	/* set LVCC */
	exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 131 68.95% 1 33.33%
seungwon jeon seungwon jeon 57 30.00% 1 33.33%
bjorn helgaas bjorn helgaas 2 1.05% 1 33.33%
Total 190 100.00% 3 100.00%



static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
{
	struct pcie_port *pp = &exynos_pcie->pp;
	struct device *dev = pp->dev;

	if (exynos_pcie->reset_gpio >= 0)
		devm_gpio_request_one(dev, exynos_pcie->reset_gpio,
				GPIOF_OUT_INIT_HIGH, "RESET");
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 35 68.63% 1 33.33%
bjorn helgaas bjorn helgaas 16 31.37% 2 66.67%
Total 51 100.00% 3 100.00%



static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
{
	struct pcie_port *pp = &exynos_pcie->pp;
	struct device *dev = pp->dev;
	u32 val;

	if (dw_pcie_link_up(pp)) {
		dev_err(dev, "Link already up\n");
		return 0;
	}

	exynos_pcie_assert_core_reset(exynos_pcie);
	exynos_pcie_assert_phy_reset(exynos_pcie);
	exynos_pcie_deassert_phy_reset(exynos_pcie);
	exynos_pcie_power_on_phy(exynos_pcie);
	exynos_pcie_init_phy(exynos_pcie);

	/* pulse for common reset */
	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
	udelay(500);
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);

	exynos_pcie_deassert_core_reset(exynos_pcie);
	dw_pcie_setup_rc(pp);
	exynos_pcie_assert_reset(exynos_pcie);

	/* assert LTSSM enable */
	exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
			  PCIE_APP_LTSSM_ENABLE);

	/* check if the link is up or not */
	if (!dw_pcie_wait_for_link(pp))
		return 0;

	while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
		val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
		dev_info(dev, "PLL Locked: 0x%x\n", val);
	}
	exynos_pcie_power_off_phy(exynos_pcie);
	return -ETIMEDOUT;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 129 72.47% 2 28.57%
bjorn helgaas bjorn helgaas 31 17.42% 3 42.86%
seungwon jeon seungwon jeon 15 8.43% 1 14.29%
joao pinto joao pinto 3 1.69% 1 14.29%
Total 178 100.00% 7 100.00%



static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 24 75.00% 1 33.33%
seungwon jeon seungwon jeon 6 18.75% 1 33.33%
bjorn helgaas bjorn helgaas 2 6.25% 1 33.33%
Total 32 100.00% 3 100.00%



static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos_pcie)
{
	u32 val;

	/* enable INTX interrupt */
	val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
		IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 28 82.35% 1 25.00%
seungwon jeon seungwon jeon 3 8.82% 1 25.00%
bjorn helgaas bjorn helgaas 2 5.88% 1 25.00%
jaehoon chung jaehoon chung 1 2.94% 1 25.00%
Total 34 100.00% 4 100.00%



static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
{
	struct exynos_pcie *exynos_pcie = arg;

	exynos_pcie_clear_irq_pulse(exynos_pcie);
	return IRQ_HANDLED;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 25 89.29% 1 50.00%
bjorn helgaas bjorn helgaas 3 10.71% 1 50.00%
Total 28 100.00% 2 100.00%



static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
{
	struct exynos_pcie *exynos_pcie = arg;
	struct pcie_port *pp = &exynos_pcie->pp;

	return dw_handle_msi_irq(pp);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 24 66.67% 1 33.33%
bjorn helgaas bjorn helgaas 11 30.56% 1 33.33%
lucas stach lucas stach 1 2.78% 1 33.33%
Total 36 100.00% 3 100.00%



static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie)
{
	struct pcie_port *pp = &exynos_pcie->pp;
	u32 val;

	dw_pcie_msi_init(pp);

	/* enable MSI interrupt */
	val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
	val |= IRQ_MSI_ENABLE;
	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 42 80.77% 1 50.00%
bjorn helgaas bjorn helgaas 10 19.23% 1 50.00%
Total 52 100.00% 2 100.00%



static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
{
	exynos_pcie_enable_irq_pulse(exynos_pcie);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		exynos_pcie_msi_init(exynos_pcie);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 24 85.71% 2 66.67%
bjorn helgaas bjorn helgaas 4 14.29% 1 33.33%
Total 28 100.00% 3 100.00%



static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
	u32 val;

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
	val = readl(pp->dbi_base + reg);
	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
	return val;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 30 54.55% 1 25.00%
bjorn helgaas bjorn helgaas 25 45.45% 3 75.00%
Total 55 100.00% 4 100.00%



static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
	writel(val, pp->dbi_base + reg);
	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 33 63.46% 1 25.00%
bjorn helgaas bjorn helgaas 19 36.54% 3 75.00%
Total 52 100.00% 4 100.00%



static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
				u32 *val)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
	int ret;

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
	ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
	return ret;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 53 80.30% 1 33.33%
bjorn helgaas bjorn helgaas 12 18.18% 1 33.33%
pratyush anand pratyush anand 1 1.52% 1 33.33%
Total 66 100.00% 3 100.00%



static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
				u32 val)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
	int ret;

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
	ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
	return ret;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 52 80.00% 1 33.33%
bjorn helgaas bjorn helgaas 12 18.46% 1 33.33%
pratyush anand pratyush anand 1 1.54% 1 33.33%
Total 65 100.00% 3 100.00%



static int exynos_pcie_link_up(struct pcie_port *pp)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
	u32 val;

	val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
	if (val == PCIE_ELBI_LTSSM_ENABLE)
		return 1;

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 39 86.67% 1 33.33%
bjorn helgaas bjorn helgaas 4 8.89% 1 33.33%
seungwon jeon seungwon jeon 2 4.44% 1 33.33%
Total 45 100.00% 3 100.00%



static void exynos_pcie_host_init(struct pcie_port *pp)
{
	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	exynos_pcie_establish_link(exynos_pcie);
	exynos_pcie_enable_interrupts(exynos_pcie);
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 19 61.29% 1 50.00%
bjorn helgaas bjorn helgaas 12 38.71% 1 50.00%
Total 31 100.00% 2 100.00%


static struct pcie_host_ops exynos_pcie_host_ops = {
	.readl_rc = exynos_pcie_readl_rc,
	.writel_rc = exynos_pcie_writel_rc,
	.rd_own_conf = exynos_pcie_rd_own_conf,
	.wr_own_conf = exynos_pcie_wr_own_conf,
	.link_up = exynos_pcie_link_up,
	.host_init = exynos_pcie_host_init,
};



static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
				       struct platform_device *pdev)
{
	struct pcie_port *pp = &exynos_pcie->pp;
	struct device *dev = pp->dev;
	int ret;

	pp->irq = platform_get_irq(pdev, 1);
	if (!pp->irq) {
		dev_err(dev, "failed to get irq\n");
		return -ENODEV;
	}
	ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
				IRQF_SHARED, "exynos-pcie", exynos_pcie);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq(pdev, 0);
		if (!pp->msi_irq) {
			dev_err(dev, "failed to get msi irq\n");
			return -ENODEV;
		}

		ret = devm_request_irq(dev, pp->msi_irq,
					exynos_pcie_msi_irq_handler,
					IRQF_SHARED | IRQF_NO_THREAD,
					"exynos-pcie", exynos_pcie);
		if (ret) {
			dev_err(dev, "failed to request msi irq\n");
			return ret;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &exynos_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 196 88.29% 3 42.86%
bjorn helgaas bjorn helgaas 23 10.36% 2 28.57%
grygorii strashko grygorii strashko 2 0.90% 1 14.29%
sachin kamat sachin kamat 1 0.45% 1 14.29%
Total 222 100.00% 7 100.00%



static int __init exynos_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct exynos_pcie *exynos_pcie;
	struct pcie_port *pp;
	struct device_node *np = dev->of_node;
	struct resource *elbi_base;
	struct resource *phy_base;
	struct resource *block_base;
	int ret;

	exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
	if (!exynos_pcie)
		return -ENOMEM;

	pp = &exynos_pcie->pp;
	pp->dev = dev;

	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);

	exynos_pcie->clk = devm_clk_get(dev, "pcie");
	if (IS_ERR(exynos_pcie->clk)) {
		dev_err(dev, "Failed to get pcie rc clock\n");
		return PTR_ERR(exynos_pcie->clk);
	}
	ret = clk_prepare_enable(exynos_pcie->clk);
	if (ret)
		return ret;

	exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
	if (IS_ERR(exynos_pcie->bus_clk)) {
		dev_err(dev, "Failed to get pcie bus clock\n");
		ret = PTR_ERR(exynos_pcie->bus_clk);
		goto fail_clk;
	}
	ret = clk_prepare_enable(exynos_pcie->bus_clk);
	if (ret)
		goto fail_clk;

	elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base);
	if (IS_ERR(exynos_pcie->elbi_base)) {
		ret = PTR_ERR(exynos_pcie->elbi_base);
		goto fail_bus_clk;
	}

	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
	if (IS_ERR(exynos_pcie->phy_base)) {
		ret = PTR_ERR(exynos_pcie->phy_base);
		goto fail_bus_clk;
	}

	block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	exynos_pcie->block_base = devm_ioremap_resource(dev, block_base);
	if (IS_ERR(exynos_pcie->block_base)) {
		ret = PTR_ERR(exynos_pcie->block_base);
		goto fail_bus_clk;
	}

	ret = exynos_add_pcie_port(exynos_pcie, pdev);
	if (ret < 0)
		goto fail_bus_clk;

	platform_set_drvdata(pdev, exynos_pcie);
	return 0;

fail_bus_clk:
	clk_disable_unprepare(exynos_pcie->bus_clk);
fail_clk:
	clk_disable_unprepare(exynos_pcie->clk);
	return ret;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 367 91.07% 2 40.00%
wei yongjun wei yongjun 24 5.96% 1 20.00%
bjorn helgaas bjorn helgaas 12 2.98% 2 40.00%
Total 403 100.00% 5 100.00%



static int __exit exynos_pcie_remove(struct platform_device *pdev)
{
	struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);

	clk_disable_unprepare(exynos_pcie->bus_clk);
	clk_disable_unprepare(exynos_pcie->clk);

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 39 100.00% 1 100.00%
Total 39 100.00% 1 100.00%


static const struct of_device_id exynos_pcie_of_match[] = {
	{ .compatible = "samsung,exynos5440-pcie", },
	{},
};


static struct platform_driver exynos_pcie_driver = {
	.remove		= __exit_p(exynos_pcie_remove),
	.driver = {
		.name	= "exynos-pcie",
		.of_match_table = exynos_pcie_of_match,
        },
};

/* Exynos PCIe driver does not allow module unload */



static int __init exynos_pcie_init(void)
{
	return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
}
Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 18 100.00% 2 100.00%
Total 18 100.00% 2 100.00%


subsys_initcall(exynos_pcie_init);
Overall Contributors
Person Tokens Prop Commits CommitProp
jingoo han jingoo han 2251 79.60% 4 19.05%
seungwon jeon seungwon jeon 307 10.86% 1 4.76%
bjorn helgaas bjorn helgaas 235 8.31% 8 38.10%
wei yongjun wei yongjun 24 0.85% 1 4.76%
joao pinto joao pinto 3 0.11% 1 4.76%
grygorii strashko grygorii strashko 2 0.07% 1 4.76%
pratyush anand pratyush anand 2 0.07% 1 4.76%
sachin kamat sachin kamat 1 0.04% 1 4.76%
paul gortmaker paul gortmaker 1 0.04% 1 4.76%
jaehoon chung jaehoon chung 1 0.04% 1 4.76%
lucas stach lucas stach 1 0.04% 1 4.76%
Total 2828 100.00% 21 100.00%
Directory: drivers/pci/host

Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.
	Person	Tokens	Prop	Commits	CommitProp
seungwon jeon	seungwon jeon	26	92.86%	1	50.00%
bjorn helgaas	bjorn helgaas	2	7.14%	1	50.00%
	Total	28	100.00%	2	100.00%
cregit-Linux how code gets into the kernel

Release 4.10 drivers/pci/host/pci-exynos.c

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