Release 4.10 drivers/pci/host/pcie-designware.h

/*
 * Synopsys Designware PCIe host controller driver
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * Author: Jingoo Han <jg1.han@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _PCIE_DESIGNWARE_H

#define _PCIE_DESIGNWARE_H

/*
 * Maximum number of MSI IRQs can be 256 per controller. But keep
 * it 32 as of now. Probably we will never need more than 32. If needed,
 * then increment it in multiple of 32.
 */

#define MAX_MSI_IRQS			32

#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)


struct pcie_port {
	
struct device		*dev;
	
u8			root_bus_nr;
	
void __iomem		*dbi_base;
	
u64			cfg0_base;
	
void __iomem		*va_cfg0_base;
	
u32			cfg0_size;
	
u64			cfg1_base;
	
void __iomem		*va_cfg1_base;
	
u32			cfg1_size;
	
resource_size_t		io_base;
	
phys_addr_t		io_bus_addr;
	
u32			io_size;
	
u64			mem_base;
	
phys_addr_t		mem_bus_addr;
	
u32			mem_size;
	
struct resource		*cfg;
	
struct resource		*io;
	
struct resource		*mem;
	
struct resource		*busn;
	
int			irq;
	
u32			lanes;
	
u32			num_viewport;
	
struct pcie_host_ops	*ops;
	
int			msi_irq;
	
struct irq_domain	*irq_domain;
	
unsigned long		msi_data;
	
u8			iatu_unroll_enabled;
	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};


struct pcie_host_ops {
	
u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
	
void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
	
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
	
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
	
int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 *val);
	
int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 val);
	
int (*link_up)(struct pcie_port *pp);
	
void (*host_init)(struct pcie_port *pp);
	
void (*msi_set_irq)(struct pcie_port *pp, int irq);
	
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
	
phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
	
u32 (*get_msi_data)(struct pcie_port *pp, int pos);
	
void (*scan_bus)(struct pcie_port *pp);
	
int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
};

u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);
void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
int dw_pcie_wait_for_link(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);

#endif /* _PCIE_DESIGNWARE_H */
Overall Contributors
Person
Tokens
Prop
Commits
CommitProp
jingoo han
jingoo han
259
52.11%
2
8.70%
murali karicheri
murali karicheri
129
25.96%
3
13.04%
bjorn helgaas
bjorn helgaas
33
6.64%
4
17.39%
pratyush anand
pratyush anand
27
5.43%
4
17.39%
minghuan lian
minghuan lian
16
3.22%
2
8.70%
joao pinto
joao pinto
12
2.41%
2
8.70%
seungwon jeon
seungwon jeon
9
1.81%
1
4.35%
lucas stach
lucas stach
6
1.21%
3
13.04%
zhou wang
zhou wang
5
1.01%
1
4.35%
wang yijing
wang yijing
1
0.20%
1
4.35%
Total
497
100.00%
23
100.00%
Directory: drivers/pci/host

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