/* * Orion CPU Bridge Registers * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #ifndef __ASM_ARCH_BRIDGE_REGS_H #define __ASM_ARCH_BRIDGE_REGS_H #include "orion5x.h" #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define BRIDGE_INT_TIMER1_CLR (~0x0004) #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) #endifOverall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Nico Pitre | 39 | 65.00% | 1 | 14.29% |
| Thomas Petazzoni | 10 | 16.67% | 1 | 14.29% |
| Ezequiel García | 4 | 6.67% | 1 | 14.29% |
| Andrew Lunn | 3 | 5.00% | 1 | 14.29% |
| Arnd Bergmann | 2 | 3.33% | 1 | 14.29% |
| Thomas Reitmayr | 1 | 1.67% | 1 | 14.29% |
| Lennert Buytenhek | 1 | 1.67% | 1 | 14.29% |
| Total | 60 | 100.00% | 7 | 100.00% |