Release 4.11 arch/arm/mach-socfpga/socfpga.c
/*
* Copyright (C) 2012-2015 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/reboot.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/cacheflush.h>
#include "core.h"
void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
void __init socfpga_sysmgr_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
if (of_property_read_u32(np, "cpu1-start-addr",
(u32 *) &socfpga_cpu1start_addr))
pr_err("SMP: Need cpu1-start-addr in device tree.\n");
/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
smp_wmb();
sync_cache_w(&socfpga_cpu1start_addr);
sys_manager_base_addr = of_iomap(np, 0);
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
rst_manager_base_addr = of_iomap(np, 0);
np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
sdr_ctl_base_addr = of_iomap(np, 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Dinh Nguyen | 74 | 71.15% | 3 | 60.00% |
| Alan Tull | 20 | 19.23% | 1 | 20.00% |
| Russell King | 10 | 9.62% | 1 | 20.00% |
| Total | 104 | 100.00% | 5 | 100.00% |
static void __init socfpga_init_irq(void)
{
irqchip_init();
socfpga_sysmgr_init();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
socfpga_init_l2_ecc();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
socfpga_init_ocram_ecc();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thor Thayer | 20 | 57.14% | 2 | 40.00% |
| Dinh Nguyen | 12 | 34.29% | 2 | 40.00% |
| Rob Herring | 3 | 8.57% | 1 | 20.00% |
| Total | 35 | 100.00% | 5 | 100.00% |
static void __init socfpga_arria10_init_irq(void)
{
irqchip_init();
socfpga_sysmgr_init();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
socfpga_init_arria10_l2_ecc();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
socfpga_init_arria10_ocram_ecc();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thor Thayer | 35 | 100.00% | 2 | 100.00% |
| Total | 35 | 100.00% | 2 | 100.00% |
static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
{
u32 temp;
temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
if (mode == REBOOT_HARD)
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
else
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Dinh Nguyen | 48 | 94.12% | 2 | 66.67% |
| Robin Holt | 3 | 5.88% | 1 | 33.33% |
| Total | 51 | 100.00% | 3 | 100.00% |
static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
{
u32 temp;
temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
if (mode == REBOOT_HARD)
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
else
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Dinh Nguyen | 51 | 100.00% | 1 | 100.00% |
| Total | 51 | 100.00% | 1 | 100.00% |
static const char *altera_dt_match[] = {
"altr,socfpga",
NULL
};
DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_irq = socfpga_init_irq,
.restart = socfpga_cyclone5_restart,
.dt_compat = altera_dt_match,
MACHINE_END
static const char *altera_a10_dt_match[] = {
"altr,socfpga-arria10",
NULL
};
DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_irq = socfpga_arria10_init_irq,
.restart = socfpga_arria10_restart,
.dt_compat = altera_a10_dt_match,
MACHINE_END
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Dinh Nguyen | 297 | 71.05% | 6 | 40.00% |
| Thor Thayer | 56 | 13.40% | 4 | 26.67% |
| Alan Tull | 26 | 6.22% | 1 | 6.67% |
| Russell King | 24 | 5.74% | 2 | 13.33% |
| Rob Herring | 9 | 2.15% | 1 | 6.67% |
| Robin Holt | 6 | 1.44% | 1 | 6.67% |
| Total | 418 | 100.00% | 15 | 100.00% |
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