cregit-Linux how code gets into the kernel

Release 4.11 arch/arm/mach-tegra/reset.c

/*
 * arch/arm/mach-tegra/reset.c
 *
 * Copyright (C) 2011,2012 NVIDIA Corporation.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/init.h>
#include <linux/io.h>

#include <soc/tegra/fuse.h>

#include <asm/cacheflush.h>
#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>

#include "iomap.h"
#include "irammap.h"
#include "reset.h"
#include "sleep.h"


#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
                                TEGRA_IRAM_RESET_HANDLER_OFFSET)


static bool is_enabled;


static void __init tegra_cpu_reset_handler_set(const u32 reset_address) { void __iomem *evp_cpu_reset = IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); u32 reg; /* * NOTE: This must be the one and only write to the EVP CPU reset * vector in the entire system. */ writel(reset_address, evp_cpu_reset); wmb(); reg = readl(evp_cpu_reset); /* * Prevent further modifications to the physical reset vector. * NOTE: Has no effect on chips prior to Tegra30. */ reg = readl(sb_ctrl); reg |= 2; writel(reg, sb_ctrl); wmb(); }

Contributors

PersonTokensPropCommitsCommitProp
Peter 'p2' De Schrijver7092.11%133.33%
Alexandre Courbot56.58%133.33%
Stephen Warren11.32%133.33%
Total76100.00%3100.00%


static void __init tegra_cpu_reset_handler_enable(void) { void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); const u32 reset_address = TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset; int err; BUG_ON(is_enabled); BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, tegra_cpu_reset_handler_size); err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); switch (err) { case -ENOSYS: tegra_cpu_reset_handler_set(reset_address); /* pass-through */ case 0: is_enabled = true; break; default: pr_crit("Cannot set CPU reset handler: %d\n", err); BUG(); } }

Contributors

PersonTokensPropCommitsCommitProp
Alexandre Courbot9695.05%266.67%
Peter 'p2' De Schrijver54.95%133.33%
Total101100.00%3100.00%


void __init tegra_cpu_reset_handler_init(void) { #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = *((u32 *)cpu_possible_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = __pa_symbol((void *)secondary_startup); #endif #ifdef CONFIG_PM_SLEEP __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = TEGRA_IRAM_LPx_RESUME_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = __pa_symbol((void *)tegra_resume); #endif tegra_cpu_reset_handler_enable(); }

Contributors

PersonTokensPropCommitsCommitProp
Peter 'p2' De Schrijver4158.57%114.29%
Joseph Lo2535.71%342.86%
Florian Fainelli22.86%114.29%
Stephen Warren11.43%114.29%
Russell King11.43%114.29%
Total70100.00%7100.00%


Overall Contributors

PersonTokensPropCommitsCommitProp
Peter 'p2' De Schrijver14850.68%17.69%
Alexandre Courbot10134.59%215.38%
Joseph Lo268.90%323.08%
Thierry Reding103.42%215.38%
Stephen Warren41.37%323.08%
Florian Fainelli20.68%17.69%
Russell King10.34%17.69%
Total292100.00%13100.00%
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