#ifndef _SPARC_TLBFLUSH_H #define _SPARC_TLBFLUSH_H #include <asm/cachetlb_32.h> #define flush_tlb_all() \ sparc32_cachetlb_ops->tlb_all() #define flush_tlb_mm(mm) \ sparc32_cachetlb_ops->tlb_mm(mm) #define flush_tlb_range(vma, start, end) \ sparc32_cachetlb_ops->tlb_range(vma, start, end) #define flush_tlb_page(vma, addr) \ sparc32_cachetlb_ops->tlb_page(vma, addr) /* * This is a kludge, until I know better. --zaitcev XXX */
static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { flush_tlb_all(); }Contributors
Person | Tokens | Prop | Commits | CommitProp |
Sam Ravnborg | 18 | 100.00% | 1 | 100.00% |
Total | 18 | 100.00% | 1 | 100.00% |
Person | Tokens | Prop | Commits | CommitProp |
Sam Ravnborg | 58 | 86.57% | 1 | 50.00% |
David S. Miller | 9 | 13.43% | 1 | 50.00% |
Total | 67 | 100.00% | 2 | 100.00% |