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Release 4.11 drivers/clocksource/qcom-timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/delay.h>


#define TIMER_MATCH_VAL			0x0000

#define TIMER_COUNT_VAL			0x0004

#define TIMER_ENABLE			0x0008

#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)

#define TIMER_ENABLE_EN			BIT(0)

#define TIMER_CLEAR			0x000C

#define DGT_CLK_CTL			0x10

#define DGT_CLK_CTL_DIV_4		0x3

#define TIMER_STS_GPT0_CLR_PEND		BIT(10)


#define GPT_HZ 32768


static void __iomem *event_base;

static void __iomem *sts_base;


static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; /* Stop the timer tick */ if (clockevent_state_oneshot(evt)) { u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); ctrl &= ~TIMER_ENABLE_EN; writel_relaxed(ctrl, event_base + TIMER_ENABLE); } evt->event_handler(evt); return IRQ_HANDLED; }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd3148.44%250.00%
Arve Hjönnevåg3046.88%125.00%
Viresh Kumar34.69%125.00%
Total64100.00%4100.00%


static int msm_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); ctrl &= ~TIMER_ENABLE_EN; writel_relaxed(ctrl, event_base + TIMER_ENABLE); writel_relaxed(ctrl, event_base + TIMER_CLEAR); writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); if (sts_base) while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) cpu_relax(); writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); return 0; }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd6170.11%480.00%
Arve Hjönnevåg2629.89%120.00%
Total87100.00%5100.00%


static int msm_timer_shutdown(struct clock_event_device *evt) { u32 ctrl; ctrl = readl_relaxed(event_base + TIMER_ENABLE); ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN); writel_relaxed(ctrl, event_base + TIMER_ENABLE); return 0; }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd2454.55%250.00%
Arve Hjönnevåg1534.09%125.00%
Viresh Kumar511.36%125.00%
Total44100.00%4100.00%

static struct clock_event_device __percpu *msm_evt; static void __iomem *source_base;
static notrace u64 msm_read_timer_count(struct clocksource *cs) { return readl_relaxed(source_base + TIMER_COUNT_VAL); }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd1890.00%360.00%
Arve Hjönnevåg15.00%120.00%
Thomas Gleixner15.00%120.00%
Total20100.00%5100.00%

static struct clocksource msm_clocksource = { .name = "dg_timer", .rating = 300, .read = msm_read_timer_count, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; static int msm_timer_irq; static int msm_timer_has_ppi;
static int msm_local_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu); int err; evt->irq = msm_timer_irq; evt->name = "msm_timer"; evt->features = CLOCK_EVT_FEAT_ONESHOT; evt->rating = 200; evt->set_state_shutdown = msm_timer_shutdown; evt->set_state_oneshot = msm_timer_shutdown; evt->tick_resume = msm_timer_shutdown; evt->set_next_event = msm_timer_set_next_event; evt->cpumask = cpumask_of(cpu); clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff); if (msm_timer_has_ppi) { enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); } else { err = request_irq(evt->irq, msm_timer_interrupt, IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING, "gp_timer", evt); if (err) pr_err("request_irq failed\n"); } return 0; }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd5638.89%233.33%
Marc Zyngier5638.89%116.67%
Viresh Kumar149.72%116.67%
Richard Cochran128.33%116.67%
Shawn Guo64.17%116.67%
Total144100.00%6100.00%


static int msm_local_timer_dying_cpu(unsigned int cpu) { struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu); evt->set_state_shutdown(evt); disable_percpu_irq(evt->irq); return 0; }

Contributors

PersonTokensPropCommitsCommitProp
Marc Zyngier1948.72%125.00%
Richard Cochran1641.03%125.00%
Stephen Boyd37.69%125.00%
Viresh Kumar12.56%125.00%
Total39100.00%4100.00%


static u64 notrace msm_sched_clock_read(void) { return msm_clocksource.read(&msm_clocksource); }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd18100.00%2100.00%
Total18100.00%2100.00%


static unsigned long msm_read_current_timer(void) { return msm_clocksource.read(&msm_clocksource); }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd18100.00%1100.00%
Total18100.00%1100.00%

static struct delay_timer msm_delay_timer = { .read_current_timer = msm_read_current_timer, };
static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, bool percpu) { struct clocksource *cs = &msm_clocksource; int res = 0; msm_timer_irq = irq; msm_timer_has_ppi = percpu; msm_evt = alloc_percpu(struct clock_event_device); if (!msm_evt) { pr_err("memory allocation failed for clockevents\n"); goto err; } if (percpu) res = request_percpu_irq(irq, msm_timer_interrupt, "gp_timer", msm_evt); if (res) { pr_err("request_percpu_irq failed\n"); } else { /* Install and invoke hotplug callbacks */ res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING, "clockevents/qcom/timer:starting", msm_local_timer_starting_cpu, msm_local_timer_dying_cpu); if (res) { free_percpu_irq(irq, msm_evt); goto err; } } err: writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); res = clocksource_register_hz(cs, dgt_hz); if (res) pr_err("clocksource_register failed\n"); sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); msm_delay_timer.freq = dgt_hz; register_current_timer_delay(&msm_delay_timer); return res; }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd10157.06%857.14%
Marc Zyngier4123.16%214.29%
Arve Hjönnevåg2212.43%17.14%
Richard Cochran84.52%17.14%
Daniel Lezcano42.26%17.14%
Thomas Gleixner10.56%17.14%
Total177100.00%14100.00%


static int __init msm_dt_timer_init(struct device_node *np) { u32 freq; int irq, ret; struct resource res; u32 percpu_offset; void __iomem *base; void __iomem *cpu0_base; base = of_iomap(np, 0); if (!base) { pr_err("Failed to map event base\n"); return -ENXIO; } /* We use GPT0 for the clockevent */ irq = irq_of_parse_and_map(np, 1); if (irq <= 0) { pr_err("Can't get irq\n"); return -EINVAL; } /* We use CPU0's DGT for the clocksource */ if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) percpu_offset = 0; ret = of_address_to_resource(np, 0, &res); if (ret) { pr_err("Failed to parse DGT resource\n"); return ret; } cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res)); if (!cpu0_base) { pr_err("Failed to map source base\n"); return -EINVAL; } if (of_property_read_u32(np, "clock-frequency", &freq)) { pr_err("Unknown frequency\n"); return -EINVAL; } event_base = base + 0x4; sts_base = base + 0x88; source_base = cpu0_base + 0x24; freq /= 4; writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); return msm_timer_init(freq, 32, irq, !!percpu_offset); }

Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd20387.12%480.00%
Daniel Lezcano3012.88%120.00%
Total233100.00%5100.00%

CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);

Overall Contributors

PersonTokensPropCommitsCommitProp
Stephen Boyd62461.24%1860.00%
Arve Hjönnevåg17016.68%13.33%
Marc Zyngier11611.38%26.67%
Daniel Lezcano363.53%26.67%
Richard Cochran363.53%13.33%
Viresh Kumar232.26%13.33%
Shawn Guo60.59%13.33%
Jeffrey Ohlstein50.49%13.33%
Thomas Gleixner20.20%26.67%
Kumar Gala10.10%13.33%
Total1019100.00%30100.00%
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