Release 4.11 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
/*
* Copyright 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* Authors: Christian König <christian.koenig@amd.com>
*/
#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "vid.h"
#include "vce/vce_3_0_d.h"
#include "vce/vce_3_0_sh_mask.h"
#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"
#include "gca/gfx_8_0_d.h"
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
#include "gca/gfx_8_0_d.h"
#include "gca/gfx_8_0_sh_mask.h"
#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
#define GRBM_GFX_INDEX__VCE_ALL_PIPE 0x07
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
#define mmGRBM_GFX_INDEX_DEFAULT 0xE0000000
#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
#define VCE_V3_0_FW_SIZE (384 * 1024)
#define VCE_V3_0_STACK_SIZE (64 * 1024)
#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
#define GET_VCE_INSTANCE(i) ((i) << GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT \
| GRBM_GFX_INDEX__VCE_ALL_PIPE)
static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
static int vce_v3_0_wait_for_idle(void *handle);
/**
* vce_v3_0_ring_get_rptr - get read pointer
*
* @ring: amdgpu_ring pointer
*
* Returns the current hardware read pointer
*/
static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
return RREG32(mmVCE_RB_RPTR);
else if (ring == &adev->vce.ring[1])
return RREG32(mmVCE_RB_RPTR2);
else
return RREG32(mmVCE_RB_RPTR3);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 68 | 100.00% | 2 | 100.00% |
| Total | 68 | 100.00% | 2 | 100.00% |
/**
* vce_v3_0_ring_get_wptr - get write pointer
*
* @ring: amdgpu_ring pointer
*
* Returns the current hardware write pointer
*/
static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
return RREG32(mmVCE_RB_WPTR);
else if (ring == &adev->vce.ring[1])
return RREG32(mmVCE_RB_WPTR2);
else
return RREG32(mmVCE_RB_WPTR3);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 68 | 100.00% | 2 | 100.00% |
| Total | 68 | 100.00% | 2 | 100.00% |
/**
* vce_v3_0_ring_set_wptr - set write pointer
*
* @ring: amdgpu_ring pointer
*
* Commits the write pointer to the hardware
*/
static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
WREG32(mmVCE_RB_WPTR, ring->wptr);
else if (ring == &adev->vce.ring[1])
WREG32(mmVCE_RB_WPTR2, ring->wptr);
else
WREG32(mmVCE_RB_WPTR3, ring->wptr);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 77 | 100.00% | 2 | 100.00% |
| Total | 77 | 100.00% | 2 | 100.00% |
static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
{
WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 18 | 66.67% | 1 | 50.00% |
| Tom St Denis | 9 | 33.33% | 1 | 50.00% |
| Total | 27 | 100.00% | 2 | 100.00% |
static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
bool gated)
{
u32 data;
/* Set Override to disable Clock Gating */
vce_v3_0_override_vce_clock_gating(adev, true);
/* This function enables MGCG which is controlled by firmware.
With the clocks in the gated state the core is still
accessible but the firmware will throttle the clocks on the
fly as necessary.
*/
if (!gated) {
data = RREG32(mmVCE_CLOCK_GATING_B);
data |= 0x1ff;
data &= ~0xef0000;
WREG32(mmVCE_CLOCK_GATING_B, data);
data = RREG32(mmVCE_UENC_CLOCK_GATING);
data |= 0x3ff000;
data &= ~0xffc00000;
WREG32(mmVCE_UENC_CLOCK_GATING, data);
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
data |= 0x2;
data &= ~0x00010000;
WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
data |= 0x37f;
WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK |
0x8;
WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
} else {
data = RREG32(mmVCE_CLOCK_GATING_B);
data &= ~0x80010;
data |= 0xe70008;
WREG32(mmVCE_CLOCK_GATING_B, data);
data = RREG32(mmVCE_UENC_CLOCK_GATING);
data |= 0xffc00000;
WREG32(mmVCE_UENC_CLOCK_GATING, data);
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
data |= 0x10000;
WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
data &= ~0x3ff;
WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK |
0x8);
WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
}
vce_v3_0_override_vce_clock_gating(adev, false);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 255 | 98.46% | 1 | 25.00% |
| Tom St Denis | 2 | 0.77% | 1 | 25.00% |
| Rex Zhu | 1 | 0.39% | 1 | 25.00% |
| Maruthi Srinivas Bayyavarapu | 1 | 0.39% | 1 | 25.00% |
| Total | 259 | 100.00% | 4 | 100.00% |
static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
{
int i, j;
for (i = 0; i < 10; ++i) {
for (j = 0; j < 100; ++j) {
uint32_t status = RREG32(mmVCE_STATUS);
if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
return 0;
mdelay(10);
}
DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
mdelay(10);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
mdelay(10);
}
return -ETIMEDOUT;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| jimqu | 97 | 92.38% | 2 | 66.67% |
| Tom St Denis | 8 | 7.62% | 1 | 33.33% |
| Total | 105 | 100.00% | 3 | 100.00% |
/**
* vce_v3_0_start - start VCE block
*
* @adev: amdgpu_device pointer
*
* Setup and start the VCE block
*/
static int vce_v3_0_start(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
int idx, r;
ring = &adev->vce.ring[0];
WREG32(mmVCE_RB_RPTR, ring->wptr);
WREG32(mmVCE_RB_WPTR, ring->wptr);
WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
ring = &adev->vce.ring[1];
WREG32(mmVCE_RB_RPTR2, ring->wptr);
WREG32(mmVCE_RB_WPTR2, ring->wptr);
WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
ring = &adev->vce.ring[2];
WREG32(mmVCE_RB_RPTR3, ring->wptr);
WREG32(mmVCE_RB_WPTR3, ring->wptr);
WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
mutex_lock(&adev->grbm_idx_mutex);
for (idx = 0; idx < 2; ++idx) {
if (adev->vce.harvest_config & (1 << idx))
continue;
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
vce_v3_0_mc_resume(adev, idx);
WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
if (adev->asic_type >= CHIP_STONEY)
WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
else
WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
mdelay(100);
r = vce_v3_0_firmware_loaded(adev);
/* clear BUSY flag */
WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
if (r) {
DRM_ERROR("VCE not responding, giving up!!!\n");
mutex_unlock(&adev->grbm_idx_mutex);
return r;
}
}
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
mutex_unlock(&adev->grbm_idx_mutex);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 153 | 41.35% | 3 | 37.50% |
| jimqu | 130 | 35.14% | 1 | 12.50% |
| Leo Liu | 62 | 16.76% | 2 | 25.00% |
| Tom St Denis | 17 | 4.59% | 1 | 12.50% |
| Rex Zhu | 8 | 2.16% | 1 | 12.50% |
| Total | 370 | 100.00% | 8 | 100.00% |
static int vce_v3_0_stop(struct amdgpu_device *adev)
{
int idx;
mutex_lock(&adev->grbm_idx_mutex);
for (idx = 0; idx < 2; ++idx) {
if (adev->vce.harvest_config & (1 << idx))
continue;
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
if (adev->asic_type >= CHIP_STONEY)
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
else
WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);
/* hold on ECPU */
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
/* clear BUSY flag */
WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
/* Set Clock-Gating off */
if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
vce_v3_0_set_vce_sw_clock_gating(adev, false);
}
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
mutex_unlock(&adev->grbm_idx_mutex);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| jimqu | 83 | 57.64% | 1 | 20.00% |
| Leo Liu | 36 | 25.00% | 1 | 20.00% |
| Tom St Denis | 13 | 9.03% | 1 | 20.00% |
| Rex Zhu | 8 | 5.56% | 1 | 20.00% |
| Alex Deucher | 4 | 2.78% | 1 | 20.00% |
| Total | 144 | 100.00% | 5 | 100.00% |
#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
{
u32 tmp;
/* Fiji, Stoney, Polaris10, Polaris11, Polaris12 are single pipe */
if ((adev->asic_type == CHIP_FIJI) ||
(adev->asic_type == CHIP_STONEY) ||
(adev->asic_type == CHIP_POLARIS10) ||
(adev->asic_type == CHIP_POLARIS11) ||
(adev->asic_type == CHIP_POLARIS12))
return AMDGPU_VCE_HARVEST_VCE1;
/* Tonga and CZ are dual or single pipe */
if (adev->flags & AMD_IS_APU)
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
VCE_HARVEST_FUSE_MACRO__MASK) >>
VCE_HARVEST_FUSE_MACRO__SHIFT;
else
tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
switch (tmp) {
case 1:
return AMDGPU_VCE_HARVEST_VCE0;
case 2:
return AMDGPU_VCE_HARVEST_VCE1;
case 3:
return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
default:
return 0;
}
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 81 | 64.29% | 2 | 25.00% |
| Sonny Jiang | 14 | 11.11% | 1 | 12.50% |
| Samuel Li | 10 | 7.94% | 1 | 12.50% |
| Tom St Denis | 9 | 7.14% | 1 | 12.50% |
| Junwei (Martin) Zhang | 9 | 7.14% | 1 | 12.50% |
| Flora Cui | 2 | 1.59% | 1 | 12.50% |
| Jammy Zhou | 1 | 0.79% | 1 | 12.50% |
| Total | 126 | 100.00% | 8 | 100.00% |
static int vce_v3_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
if ((adev->vce.harvest_config &
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
return -ENOENT;
adev->vce.num_rings = 3;
vce_v3_0_set_ring_funcs(adev);
vce_v3_0_set_irq_funcs(adev);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 67 | 83.75% | 4 | 80.00% |
| yanyang1 | 13 | 16.25% | 1 | 20.00% |
| Total | 80 | 100.00% | 5 | 100.00% |
static int vce_v3_0_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring;
int r, i;
/* VCE */
r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
if (r)
return r;
r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE +
(VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
if (r)
return r;
/* 52.8.3 required for 3 ring support */
if (adev->vce.fw_version < FW_52_8_3)
adev->vce.num_rings = 2;
r = amdgpu_vce_resume(adev);
if (r)
return r;
for (i = 0; i < adev->vce.num_rings; i++) {
ring = &adev->vce.ring[i];
sprintf(ring->name, "vce%d", i);
r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
if (r)
return r;
}
return r;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 161 | 87.03% | 3 | 50.00% |
| yanyang1 | 13 | 7.03% | 1 | 16.67% |
| Leo Liu | 10 | 5.41% | 1 | 16.67% |
| Christian König | 1 | 0.54% | 1 | 16.67% |
| Total | 185 | 100.00% | 6 | 100.00% |
static int vce_v3_0_sw_fini(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_suspend(adev);
if (r)
return r;
r = amdgpu_vce_sw_fini(adev);
if (r)
return r;
return r;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 42 | 75.00% | 1 | 50.00% |
| yanyang1 | 14 | 25.00% | 1 | 50.00% |
| Total | 56 | 100.00% | 2 | 100.00% |
static int vce_v3_0_hw_init(void *handle)
{
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
vce_v3_0_override_vce_clock_gating(adev, true);
if (!(adev->flags & AMD_IS_APU))
amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
for (i = 0; i < adev->vce.num_rings; i++)
adev->vce.ring[i].ready = false;
for (i = 0; i < adev->vce.num_rings; i++) {
r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
if (r)
return r;
else
adev->vce.ring[i].ready = true;
}
DRM_INFO("VCE initialized successfully.\n");
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 75 | 51.02% | 2 | 40.00% |
| Tom St Denis | 38 | 25.85% | 1 | 20.00% |
| Rex Zhu | 20 | 13.61% | 1 | 20.00% |
| yanyang1 | 14 | 9.52% | 1 | 20.00% |
| Total | 147 | 100.00% | 5 | 100.00% |
static int vce_v3_0_hw_fini(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v3_0_wait_for_idle(handle);
if (r)
return r;
return vce_v3_0_stop(adev);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| jimqu | 33 | 73.33% | 1 | 33.33% |
| Alex Deucher | 10 | 22.22% | 1 | 33.33% |
| yanyang1 | 2 | 4.44% | 1 | 33.33% |
| Total | 45 | 100.00% | 3 | 100.00% |
static int vce_v3_0_suspend(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v3_0_hw_fini(adev);
if (r)
return r;
r = amdgpu_vce_suspend(adev);
if (r)
return r;
return r;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 42 | 75.00% | 1 | 50.00% |
| yanyang1 | 14 | 25.00% | 1 | 50.00% |
| Total | 56 | 100.00% | 2 | 100.00% |
static int vce_v3_0_resume(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_resume(adev);
if (r)
return r;
r = vce_v3_0_hw_init(adev);
if (r)
return r;
return r;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 42 | 75.00% | 1 | 50.00% |
| yanyang1 | 14 | 25.00% | 1 | 50.00% |
| Total | 56 | 100.00% | 2 | 100.00% |
static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
{
uint32_t offset, size;
WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
WREG32(mmVCE_LMI_CTRL, 0x00398000);
WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
WREG32(mmVCE_LMI_SWAP_CNTL, 0);
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
WREG32(mmVCE_LMI_VM_CTRL, 0);
WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
if (adev->asic_type >= CHIP_STONEY) {
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
} else
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
offset = AMDGPU_VCE_FIRMWARE_OFFSET;
size = VCE_V3_0_FW_SIZE;
WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
if (idx == 0) {
offset += size;
size = VCE_V3_0_STACK_SIZE;
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
offset += size;
size = VCE_V3_0_DATA_SIZE;
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
} else {
offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE;
size = VCE_V3_0_STACK_SIZE;
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
offset += size;
size = VCE_V3_0_DATA_SIZE;
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
}
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 193 | 58.48% | 1 | 14.29% |
| Leo Liu | 125 | 37.88% | 3 | 42.86% |
| Alan Harrison | 7 | 2.12% | 1 | 14.29% |
| Tom St Denis | 5 | 1.52% | 2 | 28.57% |
| Total | 330 | 100.00% | 7 | 100.00% |
static bool vce_v3_0_is_idle(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 mask = 0;
mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
return !(RREG32(mmSRBM_STATUS2) & mask);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 38 | 54.29% | 2 | 40.00% |
| Tom St Denis | 19 | 27.14% | 2 | 40.00% |
| yanyang1 | 13 | 18.57% | 1 | 20.00% |
| Total | 70 | 100.00% | 5 | 100.00% |
static int vce_v3_0_wait_for_idle(void *handle)
{
unsigned i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++)
if (vce_v3_0_is_idle(handle))
return 0;
return -ETIMEDOUT;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 38 | 70.37% | 1 | 33.33% |
| yanyang1 | 14 | 25.93% | 1 | 33.33% |
| Tom St Denis | 2 | 3.70% | 1 | 33.33% |
| Total | 54 | 100.00% | 3 | 100.00% |
#define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK 0x00000008L
/* AUTO_BUSY */
#define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK 0x00000010L
/* RB0_BUSY */
#define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK 0x00000020L
/* RB1_BUSY */
#define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
static bool vce_v3_0_check_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 srbm_soft_reset = 0;
/* According to VCE team , we should use VCE_STATUS instead
* SRBM_STATUS.VCE_BUSY bit for busy status checking.
* GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
* instance's registers are accessed
* (0 for 1st instance, 10 for 2nd instance).
*
*VCE_STATUS
*|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB |
*|----+----+-----------+----+----+----+----------+---------+----|
*|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0|
*
* VCE team suggest use bit 3--bit 6 for busy status check
*/
mutex_lock(&adev->grbm_idx_mutex);
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
}
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
}
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
mutex_unlock(&adev->grbm_idx_mutex);
if (srbm_soft_reset) {
adev->vce.srbm_soft_reset = srbm_soft_reset;
return true;
} else {
adev->vce.srbm_soft_reset = 0;
return false;
}
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Chunming Zhou | 116 | 64.80% | 1 | 12.50% |
| Alex Deucher | 24 | 13.41% | 3 | 37.50% |
| Rex Zhu | 16 | 8.94% | 1 | 12.50% |
| yanyang1 | 13 | 7.26% | 1 | 12.50% |
| Tom St Denis | 10 | 5.59% | 2 | 25.00% |
| Total | 179 | 100.00% | 8 | 100.00% |
static int vce_v3_0_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 srbm_soft_reset;
if (!adev->vce.srbm_soft_reset)
return 0;
srbm_soft_reset = adev->vce.srbm_soft_reset;
if (srbm_soft_reset) {
u32 tmp;
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
WREG32(mmSRBM_SOFT_RESET, tmp);
tmp = RREG32(mmSRBM_SOFT_RESET);
udelay(50);
tmp &= ~srbm_soft_reset;
WREG32(mmSRBM_SOFT_RESET, tmp);
tmp = RREG32(mmSRBM_SOFT_RESET);
/* Wait a little for things to settle down */
udelay(50);
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Chunming Zhou | 113 | 91.87% | 1 | 20.00% |
| Alex Deucher | 8 | 6.50% | 3 | 60.00% |
| Tom St Denis | 2 | 1.63% | 1 | 20.00% |
| Total | 123 | 100.00% | 5 | 100.00% |
static int vce_v3_0_pre_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (!adev->vce.srbm_soft_reset)
return 0;
mdelay(5);
return vce_v3_0_suspend(adev);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Chunming Zhou | 39 | 86.67% | 1 | 25.00% |
| Alex Deucher | 6 | 13.33% | 3 | 75.00% |
| Total | 45 | 100.00% | 4 | 100.00% |
static int vce_v3_0_post_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (!adev->vce.srbm_soft_reset)
return 0;
mdelay(5);
return vce_v3_0_resume(adev);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Chunming Zhou | 32 | 71.11% | 1 | 33.33% |
| Alex Deucher | 13 | 28.89% | 2 | 66.67% |
| Total | 45 | 100.00% | 3 | 100.00% |
static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
enum amdgpu_interrupt_state state)
{
uint32_t val = 0;
if (state == AMDGPU_IRQ_STATE_ENABLE)
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 51 | 100.00% | 1 | 100.00% |
| Total | 51 | 100.00% | 1 | 100.00% |
static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
DRM_DEBUG("IH: VCE\n");
WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
switch (entry->src_data) {
case 0:
case 1:
case 2:
amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
break;
default:
DRM_ERROR("Unhandled interrupt: %d %d\n",
entry->src_id, entry->src_data);
break;
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 74 | 86.05% | 2 | 40.00% |
| Tom St Denis | 7 | 8.14% | 2 | 40.00% |
| Leo Liu | 5 | 5.81% | 1 | 20.00% |
| Total | 86 | 100.00% | 5 | 100.00% |
static int vce_v3_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
return 0;
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < 2; i++) {
/* Program VCE Instance 0 or 1 if not harvested */
if (adev->vce.harvest_config & (1 << i))
continue;
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
if (enable) {
/* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
data &= ~(0xf | 0xff0);
data |= ((0x0 << 0) | (0x04 << 4));
WREG32(mmVCE_CLOCK_GATING_A, data);
/* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */
data = RREG32(mmVCE_UENC_CLOCK_GATING);
data &= ~(0xf | 0xff0);
data |= ((0x0 << 0) | (0x04 << 4));
WREG32(mmVCE_UENC_CLOCK_GATING, data);
}
vce_v3_0_set_vce_sw_clock_gating(adev, enable);
}
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
mutex_unlock(&adev->grbm_idx_mutex);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 190 | 87.56% | 1 | 16.67% |
| Alex Deucher | 15 | 6.91% | 2 | 33.33% |
| Rex Zhu | 8 | 3.69% | 1 | 16.67% |
| yanyang1 | 3 | 1.38% | 1 | 16.67% |
| Tom St Denis | 1 | 0.46% | 1 | 16.67% |
| Total | 217 | 100.00% | 6 | 100.00% |
static int vce_v3_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
* That's done in the dpm code via the SMC. This
* just re-inits the block as necessary. The actual
* gating still happens in the dpm code. We should
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret = 0;
if (state == AMD_PG_STATE_GATE) {
ret = vce_v3_0_stop(adev);
if (ret)
goto out;
} else {
ret = vce_v3_0_start(adev);
if (ret)
goto out;
}
out:
return ret;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Huang Rui | 23 | 30.26% | 1 | 25.00% |
| Alex Deucher | 23 | 30.26% | 1 | 25.00% |
| yanyang1 | 16 | 21.05% | 1 | 25.00% |
| Rex Zhu | 14 | 18.42% | 1 | 25.00% |
| Total | 76 | 100.00% | 4 | 100.00% |
static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;
mutex_lock(&adev->pm.mutex);
if (RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
goto out;
}
WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
/* AMD_CG_SUPPORT_VCE_MGCG */
data = RREG32(mmVCE_CLOCK_GATING_A);
if (data & (0x04 << 4))
*flags |= AMD_CG_SUPPORT_VCE_MGCG;
out:
mutex_unlock(&adev->pm.mutex);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Huang Rui | 96 | 94.12% | 1 | 50.00% |
| Rex Zhu | 6 | 5.88% | 1 | 50.00% |
| Total | 102 | 100.00% | 2 | 100.00% |
static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB_VM);
amdgpu_ring_write(ring, vm_id);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Maruthi Srinivas Bayyavarapu | 70 | 100.00% | 1 | 100.00% |
| Total | 70 | 100.00% | 1 | 100.00% |
static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
unsigned int vm_id, uint64_t pd_addr)
{
amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
amdgpu_ring_write(ring, vm_id);
amdgpu_ring_write(ring, pd_addr >> 12);
amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
amdgpu_ring_write(ring, vm_id);
amdgpu_ring_write(ring, VCE_CMD_END);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Maruthi Srinivas Bayyavarapu | 62 | 100.00% | 1 | 100.00% |
| Total | 62 | 100.00% | 1 | 100.00% |
static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
{
uint32_t seq = ring->fence_drv.sync_seq;
uint64_t addr = ring->fence_drv.gpu_addr;
amdgpu_ring_write(ring, VCE_CMD_WAIT_GE);
amdgpu_ring_write(ring, lower_32_bits(addr));
amdgpu_ring_write(ring, upper_32_bits(addr));
amdgpu_ring_write(ring, seq);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Maruthi Srinivas Bayyavarapu | 63 | 100.00% | 1 | 100.00% |
| Total | 63 | 100.00% | 1 | 100.00% |
static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
.name = "vce_v3_0",
.early_init = vce_v3_0_early_init,
.late_init = NULL,
.sw_init = vce_v3_0_sw_init,
.sw_fini = vce_v3_0_sw_fini,
.hw_init = vce_v3_0_hw_init,
.hw_fini = vce_v3_0_hw_fini,
.suspend = vce_v3_0_suspend,
.resume = vce_v3_0_resume,
.is_idle = vce_v3_0_is_idle,
.wait_for_idle = vce_v3_0_wait_for_idle,
.check_soft_reset = vce_v3_0_check_soft_reset,
.pre_soft_reset = vce_v3_0_pre_soft_reset,
.soft_reset = vce_v3_0_soft_reset,
.post_soft_reset = vce_v3_0_post_soft_reset,
.set_clockgating_state = vce_v3_0_set_clockgating_state,
.set_powergating_state = vce_v3_0_set_powergating_state,
.get_clockgating_state = vce_v3_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
.type = AMDGPU_RING_TYPE_VCE,
.align_mask = 0xf,
.nop = VCE_CMD_NO_OP,
.get_rptr = vce_v3_0_ring_get_rptr,
.get_wptr = vce_v3_0_ring_get_wptr,
.set_wptr = vce_v3_0_ring_set_wptr,
.parse_cs = amdgpu_vce_ring_parse_cs,
.emit_frame_size =
4 + /* vce_v3_0_emit_pipeline_sync */
6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
.emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
.emit_ib = amdgpu_vce_ring_emit_ib,
.emit_fence = amdgpu_vce_ring_emit_fence,
.test_ring = amdgpu_vce_ring_test_ring,
.test_ib = amdgpu_vce_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vce_ring_begin_use,
.end_use = amdgpu_vce_ring_end_use,
};
static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_VCE,
.align_mask = 0xf,
.nop = VCE_CMD_NO_OP,
.get_rptr = vce_v3_0_ring_get_rptr,
.get_wptr = vce_v3_0_ring_get_wptr,
.set_wptr = vce_v3_0_ring_set_wptr,
.parse_cs = amdgpu_vce_ring_parse_cs_vm,
.emit_frame_size =
6 + /* vce_v3_0_emit_vm_flush */
4 + /* vce_v3_0_emit_pipeline_sync */
6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */
.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
.emit_ib = vce_v3_0_ring_emit_ib,
.emit_vm_flush = vce_v3_0_emit_vm_flush,
.emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
.emit_fence = amdgpu_vce_ring_emit_fence,
.test_ring = amdgpu_vce_ring_test_ring,
.test_ib = amdgpu_vce_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vce_ring_begin_use,
.end_use = amdgpu_vce_ring_end_use,
};
static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
if (adev->asic_type >= CHIP_STONEY) {
for (i = 0; i < adev->vce.num_rings; i++)
adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
DRM_INFO("VCE enabled in VM mode\n");
} else {
for (i = 0; i < adev->vce.num_rings; i++)
adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
DRM_INFO("VCE enabled in physical mode\n");
}
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Maruthi Srinivas Bayyavarapu | 55 | 55.56% | 1 | 33.33% |
| Alex Deucher | 44 | 44.44% | 2 | 66.67% |
| Total | 99 | 100.00% | 3 | 100.00% |
static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
.set = vce_v3_0_set_interrupt_state,
.process = vce_v3_0_process_interrupt,
};
static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
{
adev->vce.irq.num_types = 1;
adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
}Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 32 | 100.00% | 1 | 100.00% |
| Total | 32 | 100.00% | 1 | 100.00% |
;
const struct amdgpu_ip_block_version vce_v3_0_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_VCE,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &vce_v3_0_ip_funcs,
};
const struct amdgpu_ip_block_version vce_v3_1_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_VCE,
.major = 3,
.minor = 1,
.rev = 0,
.funcs = &vce_v3_0_ip_funcs,
};
const struct amdgpu_ip_block_version vce_v3_4_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_VCE,
.major = 3,
.minor = 4,
.rev = 0,
.funcs = &vce_v3_0_ip_funcs,
};
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Alex Deucher | 1772 | 42.44% | 10 | 19.61% |
| Eric Huang | 463 | 11.09% | 1 | 1.96% |
| jimqu | 356 | 8.53% | 2 | 3.92% |
| Maruthi Srinivas Bayyavarapu | 325 | 7.78% | 2 | 3.92% |
| Chunming Zhou | 324 | 7.76% | 1 | 1.96% |
| Leo Liu | 276 | 6.61% | 4 | 7.84% |
| Tom St Denis | 147 | 3.52% | 10 | 19.61% |
| yanyang1 | 144 | 3.45% | 1 | 1.96% |
| Huang Rui | 124 | 2.97% | 1 | 1.96% |
| Rex Zhu | 112 | 2.68% | 5 | 9.80% |
| Christian König | 86 | 2.06% | 7 | 13.73% |
| Sonny Jiang | 14 | 0.34% | 1 | 1.96% |
| Samuel Li | 10 | 0.24% | 1 | 1.96% |
| Junwei (Martin) Zhang | 9 | 0.22% | 1 | 1.96% |
| Alan Harrison | 7 | 0.17% | 1 | 1.96% |
| Jammy Zhou | 4 | 0.10% | 2 | 3.92% |
| Flora Cui | 2 | 0.05% | 1 | 1.96% |
| Total | 4175 | 100.00% | 51 | 100.00% |
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