Release 4.11 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h

/*
 *
 * Copyright (C) 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef GMC_6_0_D_H

#define GMC_6_0_D_H


#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE

#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE

#define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE

#define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE

#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE

#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE

#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E

#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E

#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E

#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E

#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x01AE

#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x01BE

#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x012E

#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x013E

#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x016E

#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x017E

#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0x00CD

#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0x00DD

#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0x00AD

#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0x00BD

#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x010D

#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x011D

#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x018D

#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x019D

#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x01AD

#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x01BD

#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x012D

#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x013D

#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x016D

#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x017D

#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0x00CC

#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0x00DC

#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0x00AC

#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0x00BC

#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x010C

#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x011C

#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x018C

#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x019C

#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x01AC

#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x01BC

#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x012C

#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x013C

#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x016C

#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x017C

#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0x00CB

#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0x00DB

#define ixMC_IO_DEBUG_CK_MISC_D0 0x00AB

#define ixMC_IO_DEBUG_CK_MISC_D1 0x00BB

#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x010B

#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x011B

#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x018B

#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x019B

#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x01AB

#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x01BB

#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x012B

#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x013B

#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x016B

#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x017B

#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0x00CF

#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0x00DF

#define ixMC_IO_DEBUG_CMD_MISC_D0 0x00AF

#define ixMC_IO_DEBUG_CMD_MISC_D1 0x00BF

#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0x00EF

#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0x00FF

#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x01CF

#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x01DF

#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x010F

#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x011F

#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x018F

#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x019F

#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x01AF

#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x01BF

#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x012F

#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x013F

#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x016F

#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x017F

#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x014F

#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x015F

#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0x00C8

#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0x00D8

#define ixMC_IO_DEBUG_DBI_MISC_D0 0x00A8

#define ixMC_IO_DEBUG_DBI_MISC_D1 0x00B8

#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0x00E8

#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0x00F8

#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x01C8

#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x01D8

#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x0108

#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x0118

#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x0148

#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x0158

#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x0188

#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x0198

#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x01A8

#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x01B8

#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x0128

#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x0138

#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x0168

#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x0178

#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x01CD

#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x01DD

#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x01CB

#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x01DB

#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x01CE

#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x01DE

#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x01CC

#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x01DC

#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x014B

#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x015B

#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0x00C1

#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0x00D1

#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0x00A1

#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0x00B1

#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0x00E1

#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0x00F1

#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x01C1

#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x01D1

#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x0101

#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x0111

#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x0141

#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x0151

#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x0181

#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x0191

#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x01A1

#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x01B1

#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x0121

#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x0131

#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x0161

#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x0171

#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0x00C0

#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0x00D0

#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0x00A0

#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0x00B0

#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0x00E0

#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0x00F0

#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x01C0

#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x01D0

#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x0100

#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x0110

#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x0140

#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x0150

#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x0180

#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x0190

#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x01A0

#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x01B0

#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x0120

#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x0130

#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x0160

#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x0170

#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x014C

#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x015C

#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0x00C3

#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0x00D3

#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0x00A3

#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0x00B3

#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0x00E3

#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0x00F3

#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x01C3

#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x01D3

#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x0103

#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x0113

#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x0143

#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x0153

#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x0183

#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x0193

#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x01A3

#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x01B3

#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x0123

#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x0133

#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x0163

#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x0173

#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0x00C2

#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0x00D2

#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0x00A2

#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0x00B2

#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0x00E2

#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0x00F2

#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x01C2

#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x01D2

#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x0102

#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x0112

#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x0142

#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x0152

#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x0182

#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x0192

#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x01A2

#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x01B2

#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x0122

#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x0132

#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x0162

#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x0172

#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x014D

#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x015D

#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0x00C5

#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0x00D5

#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0x00A5

#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0x00B5

#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0x00E5

#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0x00F5

#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x01C5

#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x01D5

#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x0105

#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x0115

#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x0145

#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x0155

#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x0185

#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x0195

#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x01A5

#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x01B5

#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x0125

#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x0135

#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x0165

#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x0175

#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0x00C4

#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0x00D4

#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0x00A4

#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0x00B4

#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0x00E4

#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0x00F4

#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x01C4

#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x01D4

#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x0104

#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x0114

#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x0144

#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x0154

#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x0184

#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x0194

#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x01A4

#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x01B4

#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x0124

#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x0134

#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x0164

#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x0174

#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x014E

#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x015E

#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0x00C7

#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0x00D7

#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0x00A7

#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0x00B7

#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0x00E7

#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0x00F7

#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x01C7

#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x01D7

#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x0107

#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x0117

#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x0147

#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x0157

#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x0187

#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x0197

#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x01A7

#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x01B7

#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x0127

#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x0137

#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x0167

#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x0177

#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0x00C6

#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0x00D6

#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0x00A6

#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0x00B6

#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0x00E6

#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0x00F6

#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x01C6

#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x01D6

#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x0106

#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x0116

#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x0146

#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x0156

#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x0186

#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x0196

#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x01A6

#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x01B6

#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x0126

#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x0136

#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x0166

#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x0176

#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0x00ED

#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0x00FD

#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0x00C9

#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0x00D9

#define ixMC_IO_DEBUG_EDC_MISC_D0 0x00A9

#define ixMC_IO_DEBUG_EDC_MISC_D1 0x00B9

#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0x00E9

#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0x00F9

#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0x00EC

#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0x00FC

#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x01C9

#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x01D9

#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0x00EB

#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0x00FB

#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x0109

#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x0119

#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x0149

#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x0159

#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x0189

#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x0199

#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x01A9

#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x01B9

#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x0129

#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x0139

#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x0169

#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x0179

#define ixMC_IO_DEBUG_UP_0 0x0000

#define ixMC_IO_DEBUG_UP_100 0x0064

#define ixMC_IO_DEBUG_UP_10 0x000A

#define ixMC_IO_DEBUG_UP_101 0x0065

#define ixMC_IO_DEBUG_UP_102 0x0066

#define ixMC_IO_DEBUG_UP_103 0x0067

#define ixMC_IO_DEBUG_UP_104 0x0068

#define ixMC_IO_DEBUG_UP_105 0x0069

#define ixMC_IO_DEBUG_UP_106 0x006A

#define ixMC_IO_DEBUG_UP_107 0x006B

#define ixMC_IO_DEBUG_UP_108 0x006C

#define ixMC_IO_DEBUG_UP_109 0x006D

#define ixMC_IO_DEBUG_UP_1 0x0001

#define ixMC_IO_DEBUG_UP_110 0x006E

#define ixMC_IO_DEBUG_UP_11 0x000B

#define ixMC_IO_DEBUG_UP_111 0x006F

#define ixMC_IO_DEBUG_UP_112 0x0070

#define ixMC_IO_DEBUG_UP_113 0x0071

#define ixMC_IO_DEBUG_UP_114 0x0072

#define ixMC_IO_DEBUG_UP_115 0x0073

#define ixMC_IO_DEBUG_UP_116 0x0074

#define ixMC_IO_DEBUG_UP_117 0x0075

#define ixMC_IO_DEBUG_UP_118 0x0076

#define ixMC_IO_DEBUG_UP_119 0x0077

#define ixMC_IO_DEBUG_UP_120 0x0078

#define ixMC_IO_DEBUG_UP_12 0x000C

#define ixMC_IO_DEBUG_UP_121 0x0079

#define ixMC_IO_DEBUG_UP_122 0x007A

#define ixMC_IO_DEBUG_UP_123 0x007B

#define ixMC_IO_DEBUG_UP_124 0x007C

#define ixMC_IO_DEBUG_UP_125 0x007D

#define ixMC_IO_DEBUG_UP_126 0x007E

#define ixMC_IO_DEBUG_UP_127 0x007F

#define ixMC_IO_DEBUG_UP_128 0x0080

#define ixMC_IO_DEBUG_UP_129 0x0081

#define ixMC_IO_DEBUG_UP_130 0x0082

#define ixMC_IO_DEBUG_UP_13 0x000D

#define ixMC_IO_DEBUG_UP_131 0x0083

#define ixMC_IO_DEBUG_UP_132 0x0084

#define ixMC_IO_DEBUG_UP_133 0x0085

#define ixMC_IO_DEBUG_UP_134 0x0086

#define ixMC_IO_DEBUG_UP_135 0x0087

#define ixMC_IO_DEBUG_UP_136 0x0088

#define ixMC_IO_DEBUG_UP_137 0x0089

#define ixMC_IO_DEBUG_UP_138 0x008A

#define ixMC_IO_DEBUG_UP_139 0x008B

#define ixMC_IO_DEBUG_UP_140 0x008C

#define ixMC_IO_DEBUG_UP_14 0x000E

#define ixMC_IO_DEBUG_UP_141 0x008D

#define ixMC_IO_DEBUG_UP_142 0x008E

#define ixMC_IO_DEBUG_UP_143 0x008F

#define ixMC_IO_DEBUG_UP_144 0x0090

#define ixMC_IO_DEBUG_UP_145 0x0091

#define ixMC_IO_DEBUG_UP_146 0x0092

#define ixMC_IO_DEBUG_UP_147 0x0093

#define ixMC_IO_DEBUG_UP_148 0x0094

#define ixMC_IO_DEBUG_UP_149 0x0095

#define ixMC_IO_DEBUG_UP_150 0x0096

#define ixMC_IO_DEBUG_UP_15 0x000F

#define ixMC_IO_DEBUG_UP_151 0x0097

#define ixMC_IO_DEBUG_UP_152 0x0098

#define ixMC_IO_DEBUG_UP_153 0x0099

#define ixMC_IO_DEBUG_UP_154 0x009A

#define ixMC_IO_DEBUG_UP_155 0x009B

#define ixMC_IO_DEBUG_UP_156 0x009C

#define ixMC_IO_DEBUG_UP_157 0x009D

#define ixMC_IO_DEBUG_UP_158 0x009E

#define ixMC_IO_DEBUG_UP_159 0x009F

#define ixMC_IO_DEBUG_UP_16 0x0010

#define ixMC_IO_DEBUG_UP_17 0x0011

#define ixMC_IO_DEBUG_UP_18 0x0012

#define ixMC_IO_DEBUG_UP_19 0x0013

#define ixMC_IO_DEBUG_UP_20 0x0014

#define ixMC_IO_DEBUG_UP_2 0x0002

#define ixMC_IO_DEBUG_UP_21 0x0015

#define ixMC_IO_DEBUG_UP_22 0x0016

#define ixMC_IO_DEBUG_UP_23 0x0017

#define ixMC_IO_DEBUG_UP_24 0x0018

#define ixMC_IO_DEBUG_UP_25 0x0019

#define ixMC_IO_DEBUG_UP_26 0x001A

#define ixMC_IO_DEBUG_UP_27 0x001B

#define ixMC_IO_DEBUG_UP_28 0x001C

#define ixMC_IO_DEBUG_UP_29 0x001D

#define ixMC_IO_DEBUG_UP_30 0x001E

#define ixMC_IO_DEBUG_UP_3 0x0003

#define ixMC_IO_DEBUG_UP_31 0x001F

#define ixMC_IO_DEBUG_UP_32 0x0020

#define ixMC_IO_DEBUG_UP_33 0x0021

#define ixMC_IO_DEBUG_UP_34 0x0022

#define ixMC_IO_DEBUG_UP_35 0x0023

#define ixMC_IO_DEBUG_UP_36 0x0024

#define ixMC_IO_DEBUG_UP_37 0x0025

#define ixMC_IO_DEBUG_UP_38 0x0026

#define ixMC_IO_DEBUG_UP_39 0x0027

#define ixMC_IO_DEBUG_UP_40 0x0028

#define ixMC_IO_DEBUG_UP_4 0x0004

#define ixMC_IO_DEBUG_UP_41 0x0029

#define ixMC_IO_DEBUG_UP_42 0x002A

#define ixMC_IO_DEBUG_UP_43 0x002B

#define ixMC_IO_DEBUG_UP_44 0x002C

#define ixMC_IO_DEBUG_UP_45 0x002D

#define ixMC_IO_DEBUG_UP_46 0x002E

#define ixMC_IO_DEBUG_UP_47 0x002F

#define ixMC_IO_DEBUG_UP_48 0x0030

#define ixMC_IO_DEBUG_UP_49 0x0031

#define ixMC_IO_DEBUG_UP_50 0x0032

#define ixMC_IO_DEBUG_UP_5 0x0005

#define ixMC_IO_DEBUG_UP_51 0x0033

#define ixMC_IO_DEBUG_UP_52 0x0034

#define ixMC_IO_DEBUG_UP_53 0x0035

#define ixMC_IO_DEBUG_UP_54 0x0036

#define ixMC_IO_DEBUG_UP_55 0x0037

#define ixMC_IO_DEBUG_UP_56 0x0038

#define ixMC_IO_DEBUG_UP_57 0x0039

#define ixMC_IO_DEBUG_UP_58 0x003A

#define ixMC_IO_DEBUG_UP_59 0x003B

#define ixMC_IO_DEBUG_UP_60 0x003C

#define ixMC_IO_DEBUG_UP_6 0x0006

#define ixMC_IO_DEBUG_UP_61 0x003D

#define ixMC_IO_DEBUG_UP_62 0x003E

#define ixMC_IO_DEBUG_UP_63 0x003F

#define ixMC_IO_DEBUG_UP_64 0x0040

#define ixMC_IO_DEBUG_UP_65 0x0041

#define ixMC_IO_DEBUG_UP_66 0x0042

#define ixMC_IO_DEBUG_UP_67 0x0043

#define ixMC_IO_DEBUG_UP_68 0x0044

#define ixMC_IO_DEBUG_UP_69 0x0045

#define ixMC_IO_DEBUG_UP_70 0x0046

#define ixMC_IO_DEBUG_UP_7 0x0007

#define ixMC_IO_DEBUG_UP_71 0x0047

#define ixMC_IO_DEBUG_UP_72 0x0048

#define ixMC_IO_DEBUG_UP_73 0x0049

#define ixMC_IO_DEBUG_UP_74 0x004A

#define ixMC_IO_DEBUG_UP_75 0x004B

#define ixMC_IO_DEBUG_UP_76 0x004C

#define ixMC_IO_DEBUG_UP_77 0x004D

#define ixMC_IO_DEBUG_UP_78 0x004E

#define ixMC_IO_DEBUG_UP_79 0x004F

#define ixMC_IO_DEBUG_UP_80 0x0050

#define ixMC_IO_DEBUG_UP_8 0x0008

#define ixMC_IO_DEBUG_UP_81 0x0051

#define ixMC_IO_DEBUG_UP_82 0x0052

#define ixMC_IO_DEBUG_UP_83 0x0053

#define ixMC_IO_DEBUG_UP_84 0x0054

#define ixMC_IO_DEBUG_UP_85 0x0055

#define ixMC_IO_DEBUG_UP_86 0x0056

#define ixMC_IO_DEBUG_UP_87 0x0057

#define ixMC_IO_DEBUG_UP_88 0x0058

#define ixMC_IO_DEBUG_UP_89 0x0059

#define ixMC_IO_DEBUG_UP_90 0x005A

#define ixMC_IO_DEBUG_UP_9 0x0009

#define ixMC_IO_DEBUG_UP_91 0x005B

#define ixMC_IO_DEBUG_UP_92 0x005C

#define ixMC_IO_DEBUG_UP_93 0x005D

#define ixMC_IO_DEBUG_UP_94 0x005E

#define ixMC_IO_DEBUG_UP_95 0x005F

#define ixMC_IO_DEBUG_UP_96 0x0060

#define ixMC_IO_DEBUG_UP_97 0x0061

#define ixMC_IO_DEBUG_UP_98 0x0062

#define ixMC_IO_DEBUG_UP_99 0x0063

#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x01EA

#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x01FA

#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x01E1

#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x01F1

#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x01E0

#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x01F0

#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x01E2

#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x01F2

#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x01EC

#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x01FC

#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x01E9

#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x01F9

#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x01EB

#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x01FB

#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x01E3

#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x01F3

#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x01E5

#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x01F5

#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x01E7

#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x01F7

#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x01E8

#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x01F8

#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x01E4

#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x01F4

#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x01E6

#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x01F6

#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0x00CA

#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0x00DA

#define ixMC_IO_DEBUG_WCK_MISC_D0 0x00AA

#define ixMC_IO_DEBUG_WCK_MISC_D1 0x00BA

#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0x00EA

#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0x00FA

#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x01CA

#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x01DA

#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x010A

#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x011A

#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x014A

#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x015A

#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x018A

#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x019A

#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x01AA

#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x01BA

#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x012A

#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x013A

#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x016A

#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x017A

#define ixMC_TSM_DEBUG_BCNT0 0x0003

#define ixMC_TSM_DEBUG_BCNT10 0x000D

#define ixMC_TSM_DEBUG_BCNT1 0x0004

#define ixMC_TSM_DEBUG_BCNT2 0x0005

#define ixMC_TSM_DEBUG_BCNT3 0x0006

#define ixMC_TSM_DEBUG_BCNT4 0x0007

#define ixMC_TSM_DEBUG_BCNT5 0x0008

#define ixMC_TSM_DEBUG_BCNT6 0x0009

#define ixMC_TSM_DEBUG_BCNT7 0x000A

#define ixMC_TSM_DEBUG_BCNT8 0x000B

#define ixMC_TSM_DEBUG_BCNT9 0x000C

#define ixMC_TSM_DEBUG_BKPT 0x0013

#define ixMC_TSM_DEBUG_FLAG 0x0001

#define ixMC_TSM_DEBUG_GCNT 0x0000

#define ixMC_TSM_DEBUG_MISC 0x0002

#define ixMC_TSM_DEBUG_ST01 0x0010

#define ixMC_TSM_DEBUG_ST23 0x0011

#define ixMC_TSM_DEBUG_ST45 0x0012

#define mmATC_ATS_CNTL 0x0CC9

#define mmATC_ATS_DEBUG 0x0CCA

#define mmATC_ATS_DEFAULT_PAGE_CNTL 0x0CD1

#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0CD0

#define mmATC_ATS_FAULT_CNTL 0x0CCD

#define mmATC_ATS_FAULT_DEBUG 0x0CCB

#define mmATC_ATS_FAULT_STATUS_ADDR 0x0CCF

#define mmATC_ATS_FAULT_STATUS_INFO 0x0CCE

#define mmATC_ATS_STATUS 0x0CCC

#define mmATC_L1_ADDRESS_OFFSET 0x0CDD

#define mmATC_L1_CNTL 0x0CDC

#define mmATC_L1RD_DEBUG_TLB 0x0CDE

#define mmATC_L1RD_STATUS 0x0CE0

#define mmATC_L1WR_DEBUG_TLB 0x0CDF

#define mmATC_L1WR_STATUS 0x0CE1

#define mmATC_L2_CNTL 0x0CD5

#define mmATC_L2_DEBUG 0x0CD7

#define mmATC_MISC_CG 0x0CD4

#define mmATC_VM_APERTURE0_CNTL 0x0CC4

#define mmATC_VM_APERTURE0_CNTL2 0x0CC6

#define mmATC_VM_APERTURE0_HIGH_ADDR 0x0CC2

#define mmATC_VM_APERTURE0_LOW_ADDR 0x0CC0

#define mmATC_VM_APERTURE1_CNTL 0x0CC5

#define mmATC_VM_APERTURE1_CNTL2 0x0CC7

#define mmATC_VM_APERTURE1_HIGH_ADDR 0x0CC3

#define mmATC_VM_APERTURE1_LOW_ADDR 0x0CC1

#define mmATC_VMID0_PASID_MAPPING 0x0CE7

#define mmATC_VMID10_PASID_MAPPING 0x0CF1

#define mmATC_VMID11_PASID_MAPPING 0x0CF2

#define mmATC_VMID12_PASID_MAPPING 0x0CF3

#define mmATC_VMID13_PASID_MAPPING 0x0CF4

#define mmATC_VMID14_PASID_MAPPING 0x0CF5

#define mmATC_VMID15_PASID_MAPPING 0x0CF6

#define mmATC_VMID1_PASID_MAPPING 0x0CE8

#define mmATC_VMID2_PASID_MAPPING 0x0CE9

#define mmATC_VMID3_PASID_MAPPING 0x0CEA

#define mmATC_VMID4_PASID_MAPPING 0x0CEB

#define mmATC_VMID5_PASID_MAPPING 0x0CEC

#define mmATC_VMID6_PASID_MAPPING 0x0CED

#define mmATC_VMID7_PASID_MAPPING 0x0CEE

#define mmATC_VMID8_PASID_MAPPING 0x0CEF

#define mmATC_VMID9_PASID_MAPPING 0x0CF0

#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0CE6

#define mmCC_MC_MAX_CHANNEL 0x096E

#define mmDLL_CNTL 0x0AE9

#define mmGMCON_DEBUG 0x0D5F

#define mmGMCON_MISC 0x0D43

#define mmGMCON_MISC2 0x0D44

#define mmGMCON_MISC3 0x0D51

#define mmGMCON_PERF_MON_CNTL0 0x0D4A

#define mmGMCON_PERF_MON_CNTL1 0x0D4B

#define mmGMCON_PERF_MON_RSLT0 0x0D4C

#define mmGMCON_PERF_MON_RSLT1 0x0D4D

#define mmGMCON_PGFSM_CONFIG 0x0D4E

#define mmGMCON_PGFSM_READ 0x0D50

#define mmGMCON_PGFSM_WRITE 0x0D4F

#define mmGMCON_RENG_EXECUTE 0x0D42

#define mmGMCON_RENG_RAM_DATA 0x0D41

#define mmGMCON_RENG_RAM_INDEX 0x0D40

#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0D48

#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0D49

#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0x0D45

#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0x0D46

#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0x0D47

#define mmMC_ARB_ADDR_HASH 0x09DC

#define mmMC_ARB_AGE_RD 0x09E9

#define mmMC_ARB_AGE_WR 0x09EA

#define mmMC_ARB_BANKMAP 0x09D7

#define mmMC_ARB_BURST_TIME 0x0A02

#define mmMC_ARB_CAC_CNTL 0x09D4

#define mmMC_ARB_CG 0x09FA

#define mmMC_ARB_DRAM_TIMING 0x09DD

#define mmMC_ARB_DRAM_TIMING_1 0x09FC

#define mmMC_ARB_DRAM_TIMING2 0x09DE

#define mmMC_ARB_DRAM_TIMING2_1 0x09FF

#define mmMC_ARB_FED_CNTL 0x09C1

#define mmMC_ARB_GDEC_RD_CNTL 0x09EE

#define mmMC_ARB_GDEC_WR_CNTL 0x09EF

#define mmMC_ARB_GECC2 0x09C9

#define mmMC_ARB_GECC2_CLI 0x09CA

#define mmMC_ARB_GECC2_DEBUG 0x09C4

#define mmMC_ARB_GECC2_DEBUG2 0x09C5

#define mmMC_ARB_GECC2_MISC 0x09C3

#define mmMC_ARB_GECC2_STATUS 0x09C2

#define mmMC_ARB_LAZY0_RD 0x09E5

#define mmMC_ARB_LAZY0_WR 0x09E6

#define mmMC_ARB_LAZY1_RD 0x09E7

#define mmMC_ARB_LAZY1_WR 0x09E8

#define mmMC_ARB_LM_RD 0x09F0

#define mmMC_ARB_LM_WR 0x09F1

#define mmMC_ARB_MINCLKS 0x09DA

#define mmMC_ARB_MISC 0x09D6

#define mmMC_ARB_MISC2 0x09D5

#define mmMC_ARB_PM_CNTL 0x09ED

#define mmMC_ARB_POP 0x09D9

#define mmMC_ARB_RAMCFG 0x09D8

#define mmMC_ARB_REMREQ 0x09F2

#define mmMC_ARB_REPLAY 0x09F3

#define mmMC_ARB_RET_CREDITS_RD 0x09F4

#define mmMC_ARB_RET_CREDITS_WR 0x09F5

#define mmMC_ARB_RFSH_CNTL 0x09EB

#define mmMC_ARB_RFSH_RATE 0x09EC

#define mmMC_ARB_RTT_CNTL0 0x09D0

#define mmMC_ARB_RTT_CNTL1 0x09D1

#define mmMC_ARB_RTT_CNTL2 0x09D2

#define mmMC_ARB_RTT_DATA 0x09CF

#define mmMC_ARB_RTT_DEBUG 0x09D3

#define mmMC_ARB_SQM_CNTL 0x09DB

#define mmMC_ARB_TM_CNTL_RD 0x09E3

#define mmMC_ARB_TM_CNTL_WR 0x09E4

#define mmMC_ARB_WCDR 0x09FB

#define mmMC_ARB_WCDR_2 0x09CE

#define mmMC_ARB_WTM_CNTL_RD 0x09DF

#define mmMC_ARB_WTM_CNTL_WR 0x09E0

#define mmMC_ARB_WTM_GRPWT_RD 0x09E1

#define mmMC_ARB_WTM_GRPWT_WR 0x09E2

#define mmMC_BIST_AUTO_CNTL 0x0A06

#define mmMC_BIST_CMD_CNTL 0x0A8E

#define mmMC_BIST_CMP_CNTL 0x0A8D

#define mmMC_BIST_CMP_CNTL_2 0x0AB6

#define mmMC_BIST_CNTL 0x0A05

#define mmMC_BIST_DATA_MASK 0x0A12

#define mmMC_BIST_DATA_WORD0 0x0A0A

#define mmMC_BIST_DATA_WORD1 0x0A0B

#define mmMC_BIST_DATA_WORD2 0x0A0C

#define mmMC_BIST_DATA_WORD3 0x0A0D

#define mmMC_BIST_DATA_WORD4 0x0A0E

#define mmMC_BIST_DATA_WORD5 0x0A0F

#define mmMC_BIST_DATA_WORD6 0x0A10

#define mmMC_BIST_DATA_WORD7 0x0A11

#define mmMC_BIST_DIR_CNTL 0x0A07

#define mmMC_BIST_EADDR 0x0A09

#define mmMC_BIST_MISMATCH_ADDR 0x0A13

#define mmMC_BIST_RDATA_EDC 0x0A1D

#define mmMC_BIST_RDATA_MASK 0x0A1C

#define mmMC_BIST_RDATA_WORD0 0x0A14

#define mmMC_BIST_RDATA_WORD1 0x0A15

#define mmMC_BIST_RDATA_WORD2 0x0A16

#define mmMC_BIST_RDATA_WORD3 0x0A17

#define mmMC_BIST_RDATA_WORD4 0x0A18

#define mmMC_BIST_RDATA_WORD5 0x0A19

#define mmMC_BIST_RDATA_WORD6 0x0A1A

#define mmMC_BIST_RDATA_WORD7 0x0A1B

#define mmMC_BIST_SADDR 0x0A08

#define mmMC_CG_CONFIG 0x096F

#define mmMC_CG_CONFIG_MCD 0x0829

#define mmMC_CG_DATAPORT 0x0A21

#define mmMC_CITF_CNTL 0x0970

#define mmMC_CITF_CREDITS_ARB_RD 0x0972

#define mmMC_CITF_CREDITS_ARB_WR 0x0973

#define mmMC_CITF_CREDITS_VM 0x0971

#define mmMC_CITF_CREDITS_XBAR 0x0989

#define mmMC_CITF_DAGB_CNTL 0x0974

#define mmMC_CITF_DAGB_DLY 0x0977

#define mmMC_CITF_INT_CREDITS 0x0975

#define mmMC_CITF_INT_CREDITS_WR 0x097D

#define mmMC_CITF_MISC_RD_CG 0x0992

#define mmMC_CITF_MISC_VM_CG 0x0994

#define mmMC_CITF_MISC_WR_CG 0x0993

#define mmMC_CITF_PERF_MON_CNTL2 0x098E

#define mmMC_CITF_PERF_MON_RSLT2 0x0991

#define mmMC_CITF_REMREQ 0x097A

#define mmMC_CITF_RET_MODE 0x0976

#define mmMC_CITF_WTM_RD_CNTL 0x097F

#define mmMC_CITF_WTM_WR_CNTL 0x0980

#define mmMC_CITF_XTRA_ENABLE 0x096D

#define mmMC_CONFIG 0x0800

#define mmMC_CONFIG_MCD 0x0828

#define mmMC_HUB_MISC_DBG 0x0831

#define mmMC_HUB_MISC_FRAMING 0x0834

#define mmMC_HUB_MISC_HUB_CG 0x082E

#define mmMC_HUB_MISC_IDLE_STATUS 0x0847

#define mmMC_HUB_MISC_OVERRIDE 0x0833

#define mmMC_HUB_MISC_POWER 0x082D

#define mmMC_HUB_MISC_SIP_CG 0x0830

#define mmMC_HUB_MISC_STATUS 0x0832

#define mmMC_HUB_MISC_VM_CG 0x082F

#define mmMC_HUB_RDREQ_CNTL 0x083B

#define mmMC_HUB_RDREQ_CREDITS 0x0844

#define mmMC_HUB_RDREQ_CREDITS2 0x0845

#define mmMC_HUB_RDREQ_DMIF 0x0863

#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848

#define mmMC_HUB_RDREQ_GBL0 0x0856

#define mmMC_HUB_RDREQ_GBL1 0x0857

#define mmMC_HUB_RDREQ_HDP 0x085B

#define mmMC_HUB_RDREQ_MCDW 0x0851

#define mmMC_HUB_RDREQ_MCDX 0x0852

#define mmMC_HUB_RDREQ_MCDY 0x0853

#define mmMC_HUB_RDREQ_MCDZ 0x0854

#define mmMC_HUB_RDREQ_MCIF 0x0864

#define mmMC_HUB_RDREQ_RLC 0x085D

#define mmMC_HUB_RDREQ_SEM 0x085E

#define mmMC_HUB_RDREQ_SIP 0x0855

#define mmMC_HUB_RDREQ_SMU 0x0858

#define mmMC_HUB_RDREQ_STATUS 0x0839

#define mmMC_HUB_RDREQ_UMC 0x0860

#define mmMC_HUB_RDREQ_UVD 0x0861

#define mmMC_HUB_RDREQ_VCE 0x085F

#define mmMC_HUB_RDREQ_VCEU 0x0866

#define mmMC_HUB_RDREQ_VMC 0x0865

#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D

#define mmMC_HUB_RDREQ_XDMAM 0x0882

#define mmMC_HUB_SHARED_DAGB_DLY 0x0846

#define mmMC_HUB_WDP_BP 0x0837

#define mmMC_HUB_WDP_CNTL 0x0835

#define mmMC_HUB_WDP_CREDITS 0x083F

#define mmMC_HUB_WDP_ERR 0x0836

#define mmMC_HUB_WDP_GBL0 0x0841

#define mmMC_HUB_WDP_GBL1 0x0842

#define mmMC_HUB_WDP_HDP 0x0879

#define mmMC_HUB_WDP_IH 0x0872

#define mmMC_HUB_WDP_MCDW 0x0867

#define mmMC_HUB_WDP_MCDX 0x0868

#define mmMC_HUB_WDP_MCDY 0x0869

#define mmMC_HUB_WDP_MCDZ 0x086A

#define mmMC_HUB_WDP_MCIF 0x086F

#define mmMC_HUB_WDP_MGPU 0x0843

#define mmMC_HUB_WDP_MGPU2 0x0840

#define mmMC_HUB_WDP_RLC 0x0873

#define mmMC_HUB_WDP_SEM 0x0874

#define mmMC_HUB_WDP_SH0 0x086E

#define mmMC_HUB_WDP_SH1 0x0876

#define mmMC_HUB_WDP_SIP 0x086B

#define mmMC_HUB_WDP_SMU 0x0875

#define mmMC_HUB_WDP_STATUS 0x0838

#define mmMC_HUB_WDP_UMC 0x0877

#define mmMC_HUB_WDP_UVD 0x0878

#define mmMC_HUB_WDP_VCE 0x0870

#define mmMC_HUB_WDP_VCEU 0x087F

#define mmMC_HUB_WDP_WTM_CNTL 0x083E

#define mmMC_HUB_WDP_XDMA 0x0881

#define mmMC_HUB_WDP_XDMAM 0x0880

#define mmMC_HUB_WDP_XDP 0x0871

#define mmMC_HUB_WRRET_CNTL 0x083C

#define mmMC_HUB_WRRET_MCDW 0x087B

#define mmMC_HUB_WRRET_MCDX 0x087C

#define mmMC_HUB_WRRET_MCDY 0x087D

#define mmMC_HUB_WRRET_MCDZ 0x087E

#define mmMC_HUB_WRRET_STATUS 0x083A

#define mmMC_IMP_CNTL 0x0A36

#define mmMC_IMP_DEBUG 0x0A37

#define mmMC_IMP_DQ_STATUS 0x0ABC

#define mmMC_IMP_STATUS 0x0A38

#define mmMC_IO_APHY_STR_CNTL_D0 0x0A97

#define mmMC_IO_APHY_STR_CNTL_D1 0x0A98

#define mmMC_IO_CDRCNTL1_D0 0x0ADD

#define mmMC_IO_CDRCNTL1_D1 0x0ADE

#define mmMC_IO_CDRCNTL2_D0 0x0AE4

#define mmMC_IO_CDRCNTL2_D1 0x0AE5

#define mmMC_IO_CDRCNTL_D0 0x0A55

#define mmMC_IO_CDRCNTL_D1 0x0A56

#define mmMC_IO_DPHY_STR_CNTL_D0 0x0A4E

#define mmMC_IO_DPHY_STR_CNTL_D1 0x0A54

#define mmMC_IO_PAD_CNTL 0x0A73

#define mmMC_IO_PAD_CNTL_D0 0x0A74

#define mmMC_IO_PAD_CNTL_D1 0x0A75

#define mmMC_IO_RXCNTL1_DPHY0_D0 0x0ADF

#define mmMC_IO_RXCNTL1_DPHY0_D1 0x0AE1

#define mmMC_IO_RXCNTL1_DPHY1_D0 0x0AE0

#define mmMC_IO_RXCNTL1_DPHY1_D1 0x0AE2

#define mmMC_IO_RXCNTL_DPHY0_D0 0x0A4C

#define mmMC_IO_RXCNTL_DPHY0_D1 0x0A52

#define mmMC_IO_RXCNTL_DPHY1_D0 0x0A4D

#define mmMC_IO_RXCNTL_DPHY1_D1 0x0A53

#define mmMC_IO_TXCNTL_APHY_D0 0x0A4B

#define mmMC_IO_TXCNTL_APHY_D1 0x0A51

#define mmMC_IO_TXCNTL_DPHY0_D0 0x0A49

#define mmMC_IO_TXCNTL_DPHY0_D1 0x0A4F

#define mmMC_IO_TXCNTL_DPHY1_D0 0x0A4A

#define mmMC_IO_TXCNTL_DPHY1_D1 0x0A50

#define mmMCLK_PWRMGT_CNTL 0x0AE8

#define mmMC_MEM_POWER_LS 0x082A

#define mmMC_NPL_STATUS 0x0A76

#define mmMC_PHY_TIMING_2 0x0ACE

#define mmMC_PHY_TIMING_D0 0x0ACC

#define mmMC_PHY_TIMING_D1 0x0ACD

#define mmMC_PMG_AUTO_CFG 0x0A35

#define mmMC_PMG_AUTO_CMD 0x0A34

#define mmMC_PMG_CFG 0x0A84

#define mmMC_PMG_CMD_EMRS 0x0A83

#define mmMC_PMG_CMD_MRS 0x0AAB

#define mmMC_PMG_CMD_MRS1 0x0AD1

#define mmMC_PMG_CMD_MRS2 0x0AD7

#define mmMC_RD_CB 0x0981

#define mmMC_RD_DB 0x0982

#define mmMC_RD_GRP_EXT 0x0978

#define mmMC_RD_GRP_GFX 0x0803

#define mmMC_RD_GRP_LCL 0x098A

#define mmMC_RD_GRP_OTH 0x0807

#define mmMC_RD_GRP_SYS 0x0805

#define mmMC_RD_HUB 0x0985

#define mmMC_RD_TC0 0x0983

#define mmMC_RD_TC1 0x0984

#define mmMC_RPB_ARB_CNTL 0x0951

#define mmMC_RPB_BIF_CNTL 0x0952

#define mmMC_RPB_CID_QUEUE_EX 0x095A

#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B

#define mmMC_RPB_CID_QUEUE_RD 0x0957

#define mmMC_RPB_CID_QUEUE_WR 0x0956

#define mmMC_RPB_CONF 0x094D

#define mmMC_RPB_DBG1 0x094F

#define mmMC_RPB_EFF_CNTL 0x0950

#define mmMC_RPB_IF_CONF 0x094E

#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958

#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959

#define mmMC_RPB_RD_SWITCH_CNTL 0x0955

#define mmMC_RPB_WR_COMBINE_CNTL 0x0954

#define mmMC_RPB_WR_SWITCH_CNTL 0x0953

#define mmMC_SEQ_BIT_REMAP_B0_D0 0x0AA3

#define mmMC_SEQ_BIT_REMAP_B0_D1 0x0AA7

#define mmMC_SEQ_BIT_REMAP_B1_D0 0x0AA4

#define mmMC_SEQ_BIT_REMAP_B1_D1 0x0AA8

#define mmMC_SEQ_BIT_REMAP_B2_D0 0x0AA5

#define mmMC_SEQ_BIT_REMAP_B2_D1 0x0AA9

#define mmMC_SEQ_BIT_REMAP_B3_D0 0x0AA6

#define mmMC_SEQ_BIT_REMAP_B3_D1 0x0AAA

#define mmMC_SEQ_BYTE_REMAP_D0 0x0A93

#define mmMC_SEQ_BYTE_REMAP_D1 0x0A94

#define mmMC_SEQ_CAS_TIMING 0x0A29

#define mmMC_SEQ_CAS_TIMING_LP 0x0A9C

#define mmMC_SEQ_CG 0x0A9A

#define mmMC_SEQ_CMD 0x0A31

#define mmMC_SEQ_CNTL 0x0A25

#define mmMC_SEQ_CNTL_2 0x0AD4

#define mmMC_SEQ_DRAM 0x0A26

#define mmMC_SEQ_DRAM_2 0x0A27

#define mmMC_SEQ_DRAM_ERROR_INSERTION 0x0ACB

#define mmMC_SEQ_FIFO_CTL 0x0A57

#define mmMC_SEQ_IO_DEBUG_DATA 0x0A92

#define mmMC_SEQ_IO_DEBUG_INDEX 0x0A91

#define mmMC_SEQ_IO_RDBI 0x0AB4

#define mmMC_SEQ_IO_REDC 0x0AB5

#define mmMC_SEQ_IO_RESERVE_D0 0x0AB7

#define mmMC_SEQ_IO_RESERVE_D1 0x0AB8

#define mmMC_SEQ_IO_RWORD0 0x0AAC

#define mmMC_SEQ_IO_RWORD1 0x0AAD

#define mmMC_SEQ_IO_RWORD2 0x0AAE

#define mmMC_SEQ_IO_RWORD3 0x0AAF

#define mmMC_SEQ_IO_RWORD4 0x0AB0

#define mmMC_SEQ_IO_RWORD5 0x0AB1

#define mmMC_SEQ_IO_RWORD6 0x0AB2

#define mmMC_SEQ_IO_RWORD7 0x0AB3

#define mmMC_SEQ_MISC0 0x0A80

#define mmMC_SEQ_MISC1 0x0A81

#define mmMC_SEQ_MISC3 0x0A8B

#define mmMC_SEQ_MISC4 0x0A8C

#define mmMC_SEQ_MISC5 0x0A95

#define mmMC_SEQ_MISC6 0x0A96

#define mmMC_SEQ_MISC7 0x0A99

#define mmMC_SEQ_MISC8 0x0A5F

#define mmMC_SEQ_MISC9 0x0AE7

#define mmMC_SEQ_MISC_TIMING 0x0A2A

#define mmMC_SEQ_MISC_TIMING2 0x0A2B

#define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E

#define mmMC_SEQ_MISC_TIMING_LP 0x0A9D

#define mmMC_SEQ_MPLL_OVERRIDE 0x0A22

#define mmMC_SEQ_PERF_CNTL 0x0A77

#define mmMC_SEQ_PERF_CNTL_1 0x0AFD

#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0x0A79

#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0x0A7A

#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0x0A7B

#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0x0A7C

#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0x0AD9

#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0x0ADA

#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0x0ADB

#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0x0ADC

#define mmMC_SEQ_PERF_SEQ_CTL 0x0A78

#define mmMC_SEQ_PMG_CMD_EMRS_LP 0x0AA1

#define mmMC_SEQ_PMG_CMD_MRS1_LP 0x0AD2

#define mmMC_SEQ_PMG_CMD_MRS2_LP 0x0AD8

#define mmMC_SEQ_PMG_CMD_MRS_LP 0x0AA2

#define mmMC_SEQ_PMG_PG_HWCNTL 0x0AB9

#define mmMC_SEQ_PMG_PG_SWCNTL_0 0x0ABA

#define mmMC_SEQ_PMG_PG_SWCNTL_1 0x0ABB

#define mmMC_SEQ_PMG_TIMING 0x0A2C

#define mmMC_SEQ_PMG_TIMING_LP 0x0AD3

#define mmMC_SEQ_RAS_TIMING 0x0A28

#define mmMC_SEQ_RAS_TIMING_LP 0x0A9B

#define mmMC_SEQ_RD_CTL_D0 0x0A2D

#define mmMC_SEQ_RD_CTL_D0_LP 0x0AC7

#define mmMC_SEQ_RD_CTL_D1 0x0A2E

#define mmMC_SEQ_RD_CTL_D1_LP 0x0AC8

#define mmMC_SEQ_RESERVE_0_S 0x0A1E

#define mmMC_SEQ_RESERVE_1_S 0x0A1F

#define mmMC_SEQ_RESERVE_M 0x0A82

#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0x0A67

#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0x0A6D

#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0x0A68

#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0x0A6E

#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0x0A69

#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0x0A6F

#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0x0A6A

#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0x0A70

#define mmMC_SEQ_RXFRAMING_DBI_D0 0x0A6B

#define mmMC_SEQ_RXFRAMING_DBI_D1 0x0A71

#define mmMC_SEQ_RXFRAMING_EDC_D0 0x0A6C

#define mmMC_SEQ_RXFRAMING_EDC_D1 0x0A72

#define mmMC_SEQ_STATUS_M 0x0A7D

#define mmMC_SEQ_STATUS_S 0x0A20

#define mmMC_SEQ_SUP_CNTL 0x0A32

#define mmMC_SEQ_SUP_DEC_STAT 0x0A88

#define mmMC_SEQ_SUP_GP0_STAT 0x0A8F

#define mmMC_SEQ_SUP_GP1_STAT 0x0A90

#define mmMC_SEQ_SUP_GP2_STAT 0x0A85

#define mmMC_SEQ_SUP_GP3_STAT 0x0A86

#define mmMC_SEQ_SUP_IR_STAT 0x0A87

#define mmMC_SEQ_SUP_PGM 0x0A33

#define mmMC_SEQ_SUP_PGM_STAT 0x0A89

#define mmMC_SEQ_SUP_R_PGM 0x0A8A

#define mmMC_SEQ_TCG_CNTL 0x0ABD

#define mmMC_SEQ_TIMER_RD 0x0ACA

#define mmMC_SEQ_TIMER_WR 0x0AC9

#define mmMC_SEQ_TRAIN_CAPTURE 0x0A3E

#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B

#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0x0AFE

#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0x0AFF

#define mmMC_SEQ_TRAIN_TIMING 0x0A40

#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0x0A3F

#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0x0A3A

#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0x0A3C

#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0x0A3D

#define mmMC_SEQ_TSM_BCNT 0x0AC2

#define mmMC_SEQ_TSM_CTRL 0x0ABE

#define mmMC_SEQ_TSM_DBI 0x0AC6

#define mmMC_SEQ_TSM_DEBUG_DATA 0x0AD0

#define mmMC_SEQ_TSM_DEBUG_INDEX 0x0ACF

#define mmMC_SEQ_TSM_EDC 0x0AC5

#define mmMC_SEQ_TSM_FLAG 0x0AC3

#define mmMC_SEQ_TSM_GCNT 0x0ABF

#define mmMC_SEQ_TSM_MISC 0x0AE6

#define mmMC_SEQ_TSM_NCNT 0x0AC1

#define mmMC_SEQ_TSM_OCNT 0x0AC0

#define mmMC_SEQ_TSM_UPDATE 0x0AC4

#define mmMC_SEQ_TSM_WCDR 0x0AE3

#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0x0A58

#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0x0A60

#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0x0A59

#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0x0A61

#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0x0A5A

#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0x0A62

#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0x0A5B

#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0x0A63

#define mmMC_SEQ_TXFRAMING_DBI_D0 0x0A5C

#define mmMC_SEQ_TXFRAMING_DBI_D1 0x0A64

#define mmMC_SEQ_TXFRAMING_EDC_D0 0x0A5D

#define mmMC_SEQ_TXFRAMING_EDC_D1 0x0A65

#define mmMC_SEQ_TXFRAMING_FCK_D0 0x0A5E

#define mmMC_SEQ_TXFRAMING_FCK_D1 0x0A66

#define mmMC_SEQ_VENDOR_ID_I0 0x0A7E

#define mmMC_SEQ_VENDOR_ID_I1 0x0A7F

#define mmMC_SEQ_WCDR_CTRL 0x0A39

#define mmMC_SEQ_WR_CTL_2 0x0AD5

#define mmMC_SEQ_WR_CTL_2_LP 0x0AD6

#define mmMC_SEQ_WR_CTL_D0 0x0A2F

#define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F

#define mmMC_SEQ_WR_CTL_D1 0x0A30

#define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0

#define mmMC_SHARED_BLACKOUT_CNTL 0x082B

#define mmMC_SHARED_CHMAP 0x0801

#define mmMC_SHARED_CHREMAP 0x0802

#define mmMC_TRAIN_EDCCDR_R_D0 0x0A41

#define mmMC_TRAIN_EDCCDR_R_D1 0x0A42

#define mmMC_TRAIN_EDC_STATUS_D0 0x0A45

#define mmMC_TRAIN_EDC_STATUS_D1 0x0A48

#define mmMC_TRAIN_PRBSERR_0_D0 0x0A43

#define mmMC_TRAIN_PRBSERR_0_D1 0x0A46

#define mmMC_TRAIN_PRBSERR_1_D0 0x0A44

#define mmMC_TRAIN_PRBSERR_1_D1 0x0A47

#define mmMC_TRAIN_PRBSERR_2_D0 0x0AFB

#define mmMC_TRAIN_PRBSERR_2_D1 0x0AFC

#define mmMC_VM_AGP_BASE 0x080C

#define mmMC_VM_AGP_BOT 0x080B

#define mmMC_VM_AGP_TOP 0x080A

#define mmMC_VM_DC_WRITE_CNTL 0x0810

#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815

#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811

#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816

#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812

#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817

#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813

#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818

#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814

#define mmMC_VM_FB_LOCATION 0x0809

#define mmMC_VM_FB_OFFSET 0x081A

#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891

#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895

#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896

#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893

#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897

#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5

#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6

#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1

#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998

#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B

#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999

#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C

#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A

#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D

#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7

#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8

#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4

#define mmMC_VM_MX_L1_TLB_CNTL 0x0819

#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F

#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E

#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D

#define mmMC_WR_CB 0x0986

#define mmMC_WR_DB 0x0987

#define mmMC_WR_GRP_EXT 0x0979

#define mmMC_WR_GRP_GFX 0x0804

#define mmMC_WR_GRP_LCL 0x098B

#define mmMC_WR_GRP_OTH 0x0808

#define mmMC_WR_GRP_SYS 0x0806

#define mmMC_WR_HUB 0x0988

#define mmMC_WR_TC0 0x097B

#define mmMC_WR_TC1 0x097C

#define mmMC_XBAR_ADDR_DEC 0x0C80

#define mmMC_XBAR_ARB 0x0C8D

#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E

#define mmMC_XBAR_CHTRIREMAP 0x0C8B

#define mmMC_XBAR_PERF_MON_CNTL0 0x0C8F

#define mmMC_XBAR_PERF_MON_CNTL1 0x0C90

#define mmMC_XBAR_PERF_MON_CNTL2 0x0C91

#define mmMC_XBAR_PERF_MON_MAX_THSH 0x0C96

#define mmMC_XBAR_PERF_MON_RSLT0 0x0C92

#define mmMC_XBAR_PERF_MON_RSLT1 0x0C93

#define mmMC_XBAR_PERF_MON_RSLT2 0x0C94

#define mmMC_XBAR_PERF_MON_RSLT3 0x0C95

#define mmMC_XBAR_RDREQ_CREDIT 0x0C83

#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84

#define mmMC_XBAR_RDRET_CREDIT1 0x0C87

#define mmMC_XBAR_RDRET_CREDIT2 0x0C88

#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89

#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A

#define mmMC_XBAR_REMOTE 0x0C81

#define mmMC_XBAR_SPARE0 0x0C97

#define mmMC_XBAR_SPARE1 0x0C98

#define mmMC_XBAR_TWOCHAN 0x0C8C

#define mmMC_XBAR_WRREQ_CREDIT 0x0C82

#define mmMC_XBAR_WRRET_CREDIT1 0x0C85

#define mmMC_XBAR_WRRET_CREDIT2 0x0C86

#define mmMC_XPB_CLG_CFG0 0x08E9

#define mmMC_XPB_CLG_CFG10 0x08F3

#define mmMC_XPB_CLG_CFG1 0x08EA

#define mmMC_XPB_CLG_CFG11 0x08F4

#define mmMC_XPB_CLG_CFG12 0x08F5

#define mmMC_XPB_CLG_CFG13 0x08F6

#define mmMC_XPB_CLG_CFG14 0x08F7

#define mmMC_XPB_CLG_CFG15 0x08F8

#define mmMC_XPB_CLG_CFG16 0x08F9

#define mmMC_XPB_CLG_CFG17 0x08FA

#define mmMC_XPB_CLG_CFG18 0x08FB

#define mmMC_XPB_CLG_CFG19 0x08FC

#define mmMC_XPB_CLG_CFG20 0x0928

#define mmMC_XPB_CLG_CFG2 0x08EB

#define mmMC_XPB_CLG_CFG21 0x0929

#define mmMC_XPB_CLG_CFG22 0x092A

#define mmMC_XPB_CLG_CFG23 0x092B

#define mmMC_XPB_CLG_CFG24 0x092C

#define mmMC_XPB_CLG_CFG25 0x092D

#define mmMC_XPB_CLG_CFG26 0x092E

#define mmMC_XPB_CLG_CFG27 0x092F

#define mmMC_XPB_CLG_CFG28 0x0930

#define mmMC_XPB_CLG_CFG29 0x0931

#define mmMC_XPB_CLG_CFG30 0x0932

#define mmMC_XPB_CLG_CFG3 0x08EC

#define mmMC_XPB_CLG_CFG31 0x0933

#define mmMC_XPB_CLG_CFG32 0x0936

#define mmMC_XPB_CLG_CFG33 0x0937

#define mmMC_XPB_CLG_CFG34 0x0938

#define mmMC_XPB_CLG_CFG35 0x0939

#define mmMC_XPB_CLG_CFG36 0x093A

#define mmMC_XPB_CLG_CFG4 0x08ED

#define mmMC_XPB_CLG_CFG5 0x08EE

#define mmMC_XPB_CLG_CFG6 0x08EF

#define mmMC_XPB_CLG_CFG7 0x08F0

#define mmMC_XPB_CLG_CFG8 0x08F1

#define mmMC_XPB_CLG_CFG9 0x08F2

#define mmMC_XPB_CLG_EXTRA 0x08FD

#define mmMC_XPB_CLG_EXTRA_RD 0x0935

#define mmMC_XPB_CLK_GAT 0x091E

#define mmMC_XPB_INTF_CFG 0x091F

#define mmMC_XPB_INTF_CFG2 0x0934

#define mmMC_XPB_INTF_STS 0x0920

#define mmMC_XPB_LB_ADDR 0x08FE

#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923

#define mmMC_XPB_MISC_CFG 0x0927

#define mmMC_XPB_P2P_BAR0 0x0904

#define mmMC_XPB_P2P_BAR1 0x0905

#define mmMC_XPB_P2P_BAR2 0x0906

#define mmMC_XPB_P2P_BAR3 0x0907

#define mmMC_XPB_P2P_BAR4 0x0908

#define mmMC_XPB_P2P_BAR5 0x0909

#define mmMC_XPB_P2P_BAR6 0x090A

#define mmMC_XPB_P2P_BAR7 0x090B

#define mmMC_XPB_P2P_BAR_CFG 0x0903

#define mmMC_XPB_P2P_BAR_DEBUG 0x090D

#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E

#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F

#define mmMC_XPB_P2P_BAR_SETUP 0x090C

#define mmMC_XPB_PEER_SYS_BAR0 0x0910

#define mmMC_XPB_PEER_SYS_BAR1 0x0911

#define mmMC_XPB_PEER_SYS_BAR2 0x0912

#define mmMC_XPB_PEER_SYS_BAR3 0x0913

#define mmMC_XPB_PEER_SYS_BAR4 0x0914

#define mmMC_XPB_PEER_SYS_BAR5 0x0915

#define mmMC_XPB_PEER_SYS_BAR6 0x0916

#define mmMC_XPB_PEER_SYS_BAR7 0x0917

#define mmMC_XPB_PEER_SYS_BAR8 0x0918

#define mmMC_XPB_PEER_SYS_BAR9 0x0919

#define mmMC_XPB_PERF_KNOBS 0x0924

#define mmMC_XPB_PIPE_STS 0x0921

#define mmMC_XPB_RTR_DEST_MAP0 0x08DB

#define mmMC_XPB_RTR_DEST_MAP1 0x08DC

#define mmMC_XPB_RTR_DEST_MAP2 0x08DD

#define mmMC_XPB_RTR_DEST_MAP3 0x08DE

#define mmMC_XPB_RTR_DEST_MAP4 0x08DF

#define mmMC_XPB_RTR_DEST_MAP5 0x08E0

#define mmMC_XPB_RTR_DEST_MAP6 0x08E1

#define mmMC_XPB_RTR_DEST_MAP7 0x08E2

#define mmMC_XPB_RTR_DEST_MAP8 0x08E3

#define mmMC_XPB_RTR_DEST_MAP9 0x08E4

#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD

#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE

#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF

#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0

#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1

#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2

#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3

#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4

#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5

#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6

#define mmMC_XPB_STICKY 0x0925

#define mmMC_XPB_STICKY_W1C 0x0926

#define mmMC_XPB_SUB_CTRL 0x0922

#define mmMC_XPB_UNC_THRESH_HST 0x08FF

#define mmMC_XPB_UNC_THRESH_SID 0x0900

#define mmMC_XPB_WCB_CFG 0x0902

#define mmMC_XPB_WCB_STS 0x0901

#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A

#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B

#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C

#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D

#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5

#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6

#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7

#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8

#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7

#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8

#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9

#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA

#define mmMPLL_AD_FUNC_CNTL 0x0AF0

#define mmMPLL_AD_STATUS 0x0AF6

#define mmMPLL_CNTL_MODE 0x0AEC

#define mmMPLL_CONTROL 0x0AF5

#define mmMPLL_DQ_0_0_STATUS 0x0AF7

#define mmMPLL_DQ_0_1_STATUS 0x0AF8

#define mmMPLL_DQ_1_0_STATUS 0x0AF9

#define mmMPLL_DQ_1_1_STATUS 0x0AFA

#define mmMPLL_DQ_FUNC_CNTL 0x0AF1

#define mmMPLL_FUNC_CNTL 0x0AED

#define mmMPLL_FUNC_CNTL_1 0x0AEE

#define mmMPLL_FUNC_CNTL_2 0x0AEF

#define mmMPLL_SEQ_UCODE_1 0x0AEA

#define mmMPLL_SEQ_UCODE_2 0x0AEB

#define mmMPLL_SS1 0x0AF3

#define mmMPLL_SS2 0x0AF4

#define mmMPLL_TIME 0x0AF2

#define mmVM_CONTEXT0_CNTL 0x0504

#define mmVM_CONTEXT0_CNTL2 0x050C

#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F

#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F

#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557

#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E

#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546

#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536

#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510

#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511

#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512

#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513

#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514

#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515

#define mmVM_CONTEXT1_CNTL 0x0505

#define mmVM_CONTEXT1_CNTL2 0x050D

#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550

#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560

#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558

#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F

#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547

#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537

#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551

#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552

#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553

#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554

#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555

#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556

#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E

#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F

#define mmVM_CONTEXTS_DISABLE 0x0535

#define mmVM_DEBUG 0x056F

#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507

#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506

#define mmVM_FAULT_CLIENT_ID 0x054E

#define mmVM_INVALIDATE_REQUEST 0x051E

#define mmVM_INVALIDATE_RESPONSE 0x051F

#define mmVM_L2_BANK_SELECT_MASKA 0x0572

#define mmVM_L2_BANK_SELECT_MASKB 0x0573

#define mmVM_L2_CG 0x0570

#define mmVM_L2_CNTL 0x0500

#define mmVM_L2_CNTL2 0x0501

#define mmVM_L2_CNTL3 0x0502

#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576

#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575

#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577

#define mmVM_L2_STATUS 0x0503

#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530

#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C

#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531

#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D

#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532

#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E

#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533

#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F

#define mmVM_PRT_CNTL 0x0534

#endif
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Directory: drivers/gpu/drm/amd/include/asic_reg/gmc

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