Release 4.11 drivers/gpu/drm/i915/i915_gem_fence_reg.h

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef __I915_FENCE_REG_H__

#define __I915_FENCE_REG_H__

#include <linux/list.h>

struct drm_i915_private;
struct i915_vma;


#define I965_FENCE_PAGE 4096UL


struct drm_i915_fence_reg {
	
struct list_head link;
	
struct drm_i915_private *i915;
	
struct i915_vma *vma;
	
int pin_count;
	
int id;
	/**
         * Whether the tiling parameters for the currently
         * associated fence register have changed. Note that
         * for the purposes of tracking tiling changes we also
         * treat the unfenced register, the register slot that
         * the object occupies whilst it executes a fenced
         * command (such as BLT on gen2/3), as a "fence".
         */
	
bool dirty;
};

#endif

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Joonas Lahtinen
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Chris Wilson
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Directory: drivers/gpu/drm/i915

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