cregit-Linux how code gets into the kernel

Release 4.11 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c

/*
 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
#include "gf100.h"
#include "ctxgf100.h"

#include <subdev/timer.h>

#include <nvif/class.h>


static void gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; u32 val; /* Bypass MMU check for non-secure boot */ if (!device->secboot) { nvkm_wr32(device, 0x100ce4, 0xffffffff); if (nvkm_rd32(device, 0x100ce4) != 0xffffffff) nvdev_warn(device, "cannot bypass secure boot - expect failure soon!\n"); } val = nvkm_rd32(device, 0x100c80); val &= 0xf000187f; nvkm_wr32(device, 0x418880, val); nvkm_wr32(device, 0x418890, 0); nvkm_wr32(device, 0x418894, 0); nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); }

Contributors

PersonTokensPropCommitsCommitProp
Alexandre Courbot11872.84%240.00%
Ben Skeggs4427.16%360.00%
Total162100.00%5100.00%


static void gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_wr32(device, 0x419e44, 0xdffffe); nvkm_wr32(device, 0x419e4c, 0x5); }

Contributors

PersonTokensPropCommitsCommitProp
Ben Skeggs2250.00%266.67%
Alexandre Courbot2250.00%133.33%
Total44100.00%3100.00%

static const struct gf100_gr_func gm20b_gr = { .init = gk20a_gr_init, .init_gpc_mmu = gm20b_gr_init_gpc_mmu, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, .rops = gm200_gr_rops, .ppc_nr = 1, .grctx = &gm20b_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, { -1, -1, MAXWELL_B, &gf100_fermi }, { -1, -1, MAXWELL_COMPUTE_B }, {} } };
int gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { return gm200_gr_new_(&gm20b_gr, device, index, pgr); }

Contributors

PersonTokensPropCommitsCommitProp
Ben Skeggs2681.25%250.00%
Alexandre Courbot618.75%250.00%
Total32100.00%4100.00%


Overall Contributors

PersonTokensPropCommitsCommitProp
Ben Skeggs18954.78%872.73%
Alexandre Courbot15645.22%327.27%
Total345100.00%11100.00%
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