Release 4.11 drivers/gpu/drm/omapdrm/dss/venc.c

Directory: drivers/gpu/drm/omapdrm/dss
/*
 * linux/drivers/video/omap2/dss/venc.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * VENC settings from TI's DSS driver
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */


#define DSS_SUBSYS_NAME "VENC"

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/component.h>

#include "omapdss.h"
#include "dss.h"
#include "dss_features.h"

/* Venc registers */

#define VENC_REV_ID				0x00

#define VENC_STATUS				0x04

#define VENC_F_CONTROL				0x08

#define VENC_VIDOUT_CTRL			0x10

#define VENC_SYNC_CTRL				0x14

#define VENC_LLEN				0x1C

#define VENC_FLENS				0x20

#define VENC_HFLTR_CTRL				0x24

#define VENC_CC_CARR_WSS_CARR			0x28

#define VENC_C_PHASE				0x2C

#define VENC_GAIN_U				0x30

#define VENC_GAIN_V				0x34

#define VENC_GAIN_Y				0x38

#define VENC_BLACK_LEVEL			0x3C

#define VENC_BLANK_LEVEL			0x40

#define VENC_X_COLOR				0x44

#define VENC_M_CONTROL				0x48

#define VENC_BSTAMP_WSS_DATA			0x4C

#define VENC_S_CARR				0x50

#define VENC_LINE21				0x54

#define VENC_LN_SEL				0x58

#define VENC_L21__WC_CTL			0x5C

#define VENC_HTRIGGER_VTRIGGER			0x60

#define VENC_SAVID__EAVID			0x64

#define VENC_FLEN__FAL				0x68

#define VENC_LAL__PHASE_RESET			0x6C

#define VENC_HS_INT_START_STOP_X		0x70

#define VENC_HS_EXT_START_STOP_X		0x74

#define VENC_VS_INT_START_X			0x78

#define VENC_VS_INT_STOP_X__VS_INT_START_Y	0x7C

#define VENC_VS_INT_STOP_Y__VS_EXT_START_X	0x80

#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y	0x84

#define VENC_VS_EXT_STOP_Y			0x88

#define VENC_AVID_START_STOP_X			0x90

#define VENC_AVID_START_STOP_Y			0x94

#define VENC_FID_INT_START_X__FID_INT_START_Y	0xA0

#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X	0xA4

#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y	0xA8

#define VENC_TVDETGP_INT_START_STOP_X		0xB0

#define VENC_TVDETGP_INT_START_STOP_Y		0xB4

#define VENC_GEN_CTRL				0xB8

#define VENC_OUTPUT_CONTROL			0xC4

#define VENC_OUTPUT_TEST			0xC8

#define VENC_DAC_B__DAC_C			0xC8


struct venc_config {
	
u32 f_control;
	
u32 vidout_ctrl;
	
u32 sync_ctrl;
	
u32 llen;
	
u32 flens;
	
u32 hfltr_ctrl;
	
u32 cc_carr_wss_carr;
	
u32 c_phase;
	
u32 gain_u;
	
u32 gain_v;
	
u32 gain_y;
	
u32 black_level;
	
u32 blank_level;
	
u32 x_color;
	
u32 m_control;
	
u32 bstamp_wss_data;
	
u32 s_carr;
	
u32 line21;
	
u32 ln_sel;
	
u32 l21__wc_ctl;
	
u32 htrigger_vtrigger;
	
u32 savid__eavid;
	
u32 flen__fal;
	
u32 lal__phase_reset;
	
u32 hs_int_start_stop_x;
	
u32 hs_ext_start_stop_x;
	
u32 vs_int_start_x;
	
u32 vs_int_stop_x__vs_int_start_y;
	
u32 vs_int_stop_y__vs_ext_start_x;
	
u32 vs_ext_stop_x__vs_ext_start_y;
	
u32 vs_ext_stop_y;
	
u32 avid_start_stop_x;
	
u32 avid_start_stop_y;
	
u32 fid_int_start_x__fid_int_start_y;
	
u32 fid_int_offset_y__fid_ext_start_x;
	
u32 fid_ext_start_y__fid_ext_offset_y;
	
u32 tvdetgp_int_start_stop_x;
	
u32 tvdetgp_int_start_stop_y;
	
u32 gen_ctrl;
};

/* from TRM */

static const struct venc_config venc_config_pal_trm = {
	.f_control				= 0,
	.vidout_ctrl				= 1,
	.sync_ctrl				= 0x40,
	.llen					= 0x35F, /* 863 */
	.flens					= 0x270, /* 624 */
	.hfltr_ctrl				= 0,
	.cc_carr_wss_carr			= 0x2F7225ED,
	.c_phase				= 0,
	.gain_u					= 0x111,
	.gain_v					= 0x181,
	.gain_y					= 0x140,
	.black_level				= 0x3B,
	.blank_level				= 0x3B,
	.x_color				= 0x7,
	.m_control				= 0x2,
	.bstamp_wss_data			= 0x3F,
	.s_carr					= 0x2A098ACB,
	.line21					= 0,
	.ln_sel					= 0x01290015,
	.l21__wc_ctl				= 0x0000F603,
	.htrigger_vtrigger			= 0,

	.savid__eavid				= 0x06A70108,
	.flen__fal				= 0x00180270,
	.lal__phase_reset			= 0x00040135,
	.hs_int_start_stop_x			= 0x00880358,
	.hs_ext_start_stop_x			= 0x000F035F,
	.vs_int_start_x				= 0x01A70000,
	.vs_int_stop_x__vs_int_start_y		= 0x000001A7,
	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0000,
	.vs_ext_stop_x__vs_ext_start_y		= 0x000101AF,
	.vs_ext_stop_y				= 0x00000025,
	.avid_start_stop_x			= 0x03530083,
	.avid_start_stop_y			= 0x026C002E,
	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
	.fid_ext_start_y__fid_ext_offset_y	= 0x01380001,

	.tvdetgp_int_start_stop_x		= 0x00140001,
	.tvdetgp_int_start_stop_y		= 0x00010001,
	.gen_ctrl				= 0x00FF0000,
};

/* from TRM */

static const struct venc_config venc_config_ntsc_trm = {
	.f_control				= 0,
	.vidout_ctrl				= 1,
	.sync_ctrl				= 0x8040,
	.llen					= 0x359,
	.flens					= 0x20C,
	.hfltr_ctrl				= 0,
	.cc_carr_wss_carr			= 0x043F2631,
	.c_phase				= 0,
	.gain_u					= 0x102,
	.gain_v					= 0x16C,
	.gain_y					= 0x12F,
	.black_level				= 0x43,
	.blank_level				= 0x38,
	.x_color				= 0x7,
	.m_control				= 0x1,
	.bstamp_wss_data			= 0x38,
	.s_carr					= 0x21F07C1F,
	.line21					= 0,
	.ln_sel					= 0x01310011,
	.l21__wc_ctl				= 0x0000F003,
	.htrigger_vtrigger			= 0,

	.savid__eavid				= 0x069300F4,
	.flen__fal				= 0x0016020C,
	.lal__phase_reset			= 0x00060107,
	.hs_int_start_stop_x			= 0x008E0350,
	.hs_ext_start_stop_x			= 0x000F0359,
	.vs_int_start_x				= 0x01A00000,
	.vs_int_stop_x__vs_int_start_y		= 0x020701A0,
	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
	.vs_ext_stop_y				= 0x00000006,
	.avid_start_stop_x			= 0x03480078,
	.avid_start_stop_y			= 0x02060024,
	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,

	.tvdetgp_int_start_stop_x		= 0x00140001,
	.tvdetgp_int_start_stop_y		= 0x00010001,
	.gen_ctrl				= 0x00F90000,
};


static const struct venc_config venc_config_pal_bdghi = {
	.f_control				= 0,
	.vidout_ctrl				= 0,
	.sync_ctrl				= 0,
	.hfltr_ctrl				= 0,
	.x_color				= 0,
	.line21					= 0,
	.ln_sel					= 21,
	.htrigger_vtrigger			= 0,
	.tvdetgp_int_start_stop_x		= 0x00140001,
	.tvdetgp_int_start_stop_y		= 0x00010001,
	.gen_ctrl				= 0x00FB0000,

	.llen					= 864-1,
	.flens					= 625-1,
	.cc_carr_wss_carr			= 0x2F7625ED,
	.c_phase				= 0xDF,
	.gain_u					= 0x111,
	.gain_v					= 0x181,
	.gain_y					= 0x140,
	.black_level				= 0x3e,
	.blank_level				= 0x3e,
	.m_control				= 0<<2 | 1<<1,
	.bstamp_wss_data			= 0x42,
	.s_carr					= 0x2a098acb,
	.l21__wc_ctl				= 0<<13 | 0x16<<8 | 0<<0,
	.savid__eavid				= 0x06A70108,
	.flen__fal				= 23<<16 | 624<<0,
	.lal__phase_reset			= 2<<17 | 310<<0,
	.hs_int_start_stop_x			= 0x00920358,
	.hs_ext_start_stop_x			= 0x000F035F,
	.vs_int_start_x				= 0x1a7<<16,
	.vs_int_stop_x__vs_int_start_y		= 0x000601A7,
	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0036,
	.vs_ext_stop_x__vs_ext_start_y		= 0x27101af,
	.vs_ext_stop_y				= 0x05,
	.avid_start_stop_x			= 0x03530082,
	.avid_start_stop_y			= 0x0270002E,
	.fid_int_start_x__fid_int_start_y	= 0x0005008A,
	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
	.fid_ext_start_y__fid_ext_offset_y	= 0x01380005,
};


const struct videomode omap_dss_pal_vm = {
	.hactive	= 720,
	.vactive	= 574,
	.pixelclock	= 13500000,
	.hsync_len	= 64,
	.hfront_porch	= 12,
	.hback_porch	= 68,
	.vsync_len	= 5,
	.vfront_porch	= 5,
	.vback_porch	= 41,

	.flags		= DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
			  DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
			  DISPLAY_FLAGS_PIXDATA_POSEDGE |
			  DISPLAY_FLAGS_SYNC_NEGEDGE,
};

EXPORT_SYMBOL(omap_dss_pal_vm);


const struct videomode omap_dss_ntsc_vm = {
	.hactive	= 720,
	.vactive	= 482,
	.pixelclock	= 13500000,
	.hsync_len	= 64,
	.hfront_porch	= 16,
	.hback_porch	= 58,
	.vsync_len	= 6,
	.vfront_porch	= 6,
	.vback_porch	= 31,

	.flags		= DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
			  DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
			  DISPLAY_FLAGS_PIXDATA_POSEDGE |
			  DISPLAY_FLAGS_SYNC_NEGEDGE,
};

EXPORT_SYMBOL(omap_dss_ntsc_vm);

static struct {
	
struct platform_device *pdev;
	
void __iomem *base;
	
struct mutex venc_lock;
	
u32 wss_data;
	
struct regulator *vdda_dac_reg;

	
struct clk	*tv_dac_clk;

	
struct videomode vm;
	
enum omap_dss_venc_type type;
	
bool invert_polarity;

	
struct omap_dss_device output;
} 
venc;



static inline void venc_write_reg(int idx, u32 val)
{
	__raw_writel(val, venc.base + idx);
}

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static inline u32 venc_read_reg(int idx)
{
	u32 l = __raw_readl(venc.base + idx);
	return l;
}

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static void venc_write_config(const struct venc_config *config)
{
	DSSDBG("write venc conf\n");

	venc_write_reg(VENC_LLEN, config->llen);
	venc_write_reg(VENC_FLENS, config->flens);
	venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
	venc_write_reg(VENC_C_PHASE, config->c_phase);
	venc_write_reg(VENC_GAIN_U, config->gain_u);
	venc_write_reg(VENC_GAIN_V, config->gain_v);
	venc_write_reg(VENC_GAIN_Y, config->gain_y);
	venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
	venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
	venc_write_reg(VENC_M_CONTROL, config->m_control);
	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
			venc.wss_data);
	venc_write_reg(VENC_S_CARR, config->s_carr);
	venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
	venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
	venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
	venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
	venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
	venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
	venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
	venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
		       config->vs_int_stop_x__vs_int_start_y);
	venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
		       config->vs_int_stop_y__vs_ext_start_x);
	venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
		       config->vs_ext_stop_x__vs_ext_start_y);
	venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
	venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
	venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
	venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
		       config->fid_int_start_x__fid_int_start_y);
	venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
		       config->fid_int_offset_y__fid_ext_start_x);
	venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
		       config->fid_ext_start_y__fid_ext_offset_y);

	venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
	venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
	venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
	venc_write_reg(VENC_X_COLOR, config->x_color);
	venc_write_reg(VENC_LINE21, config->line21);
	venc_write_reg(VENC_LN_SEL, config->ln_sel);
	venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
	venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
		       config->tvdetgp_int_start_stop_x);
	venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
		       config->tvdetgp_int_start_stop_y);
	venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
	venc_write_reg(VENC_F_CONTROL, config->f_control);
	venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
}

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static void venc_reset(void)
{
	int t = 1000;

	venc_write_reg(VENC_F_CONTROL, 1<<8);
	while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
		if (--t == 0) {
			DSSERR("Failed to reset venc\n");
			return;
		}
	}

#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
	/* the magical sleep that makes things work */
	/* XXX more info? What bug this circumvents? */
	msleep(20);
#endif
}

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static int venc_runtime_get(void)
{
	int r;

	DSSDBG("venc_runtime_get\n");

	r = pm_runtime_get_sync(&venc.pdev->dev);
	WARN_ON(r < 0);
	return r < 0 ? r : 0;
}

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static void venc_runtime_put(void)
{
	int r;

	DSSDBG("venc_runtime_put\n");

	r = pm_runtime_put_sync(&venc.pdev->dev);
	WARN_ON(r < 0 && r != -ENOSYS);
}

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static const struct venc_config *venc_timings_to_config(struct videomode *vm)
{
	if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
		return &venc_config_pal_trm;

	if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
		return &venc_config_ntsc_trm;

	BUG();
	return NULL;
}

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static int venc_power_on(struct omap_dss_device *dssdev)
{
	enum omap_channel channel = dssdev->dispc_channel;
	u32 l;
	int r;

	r = venc_runtime_get();
	if (r)
		goto err0;

	venc_reset();
	venc_write_config(venc_timings_to_config(&venc.vm));

	dss_set_venc_output(venc.type);
	dss_set_dac_pwrdn_bgz(1);

	l = 0;

	if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
		l |= 1 << 1;
	else /* S-Video */
		l |= (1 << 0) | (1 << 2);

	if (venc.invert_polarity == false)
		l |= 1 << 3;

	venc_write_reg(VENC_OUTPUT_CONTROL, l);

	dss_mgr_set_timings(channel, &venc.vm);

	r = regulator_enable(venc.vdda_dac_reg);
	if (r)
		goto err1;

	r = dss_mgr_enable(channel);
	if (r)
		goto err2;

	return 0;

err2:
	regulator_disable(venc.vdda_dac_reg);
err1:
	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
	dss_set_dac_pwrdn_bgz(0);

	venc_runtime_put();
err0:
	return r;
}

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Total 192 100.00% 13 100.00%



static void venc_power_off(struct omap_dss_device *dssdev)
{
	enum omap_channel channel = dssdev->dispc_channel;

	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
	dss_set_dac_pwrdn_bgz(0);

	dss_mgr_disable(channel);

	regulator_disable(venc.vdda_dac_reg);

	venc_runtime_put();
}

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static int venc_display_enable(struct omap_dss_device *dssdev)
{
	struct omap_dss_device *out = &venc.output;
	int r;

	DSSDBG("venc_display_enable\n");

	mutex_lock(&venc.venc_lock);

	if (!out->dispc_channel_connected) {
		DSSERR("Failed to enable display: no output/manager\n");
		r = -ENODEV;
		goto err0;
	}

	r = venc_power_on(dssdev);
	if (r)
		goto err0;

	venc.wss_data = 0;

	mutex_unlock(&venc.venc_lock);

	return 0;
err0:
	mutex_unlock(&venc.venc_lock);
	return r;
}

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static void venc_display_disable(struct omap_dss_device *dssdev)
{
	DSSDBG("venc_display_disable\n");

	mutex_lock(&venc.venc_lock);

	venc_power_off(dssdev);

	mutex_unlock(&venc.venc_lock);
}

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static void venc_set_timings(struct omap_dss_device *dssdev,
			     struct videomode *vm)
{
	DSSDBG("venc_set_timings\n");

	mutex_lock(&venc.venc_lock);

	/* Reset WSS data when the TV standard changes. */
	if (memcmp(&venc.vm, vm, sizeof(*vm)))
		venc.wss_data = 0;

	venc.vm = *vm;

	dispc_set_tv_pclk(13500000);

	mutex_unlock(&venc.venc_lock);
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 49 66.22% 3 42.86%
Archit Taneja 18 24.32% 2 28.57%
Peter Ujfalusi 7 9.46% 2 28.57%
Total 74 100.00% 7 100.00%



static int venc_check_timings(struct omap_dss_device *dssdev,
			      struct videomode *vm)
{
	DSSDBG("venc_check_timings\n");

	if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
		return 0;

	if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
		return 0;

	return -EINVAL;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 59 88.06% 2 50.00%
Peter Ujfalusi 8 11.94% 2 50.00%
Total 67 100.00% 4 100.00%



static void venc_get_timings(struct omap_dss_device *dssdev,
			     struct videomode *vm)
{
	mutex_lock(&venc.venc_lock);

	*vm = venc.vm;

	mutex_unlock(&venc.venc_lock);
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 35 89.74% 1 33.33%
Peter Ujfalusi 4 10.26% 2 66.67%
Total 39 100.00% 3 100.00%



static u32 venc_get_wss(struct omap_dss_device *dssdev)
{
	/* Invert due to VENC_L21_WC_CTL:INV=1 */
	return (venc.wss_data >> 8) ^ 0xfffff;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 23 100.00% 2 100.00%
Total 23 100.00% 2 100.00%



static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
{
	const struct venc_config *config;
	int r;

	DSSDBG("venc_set_wss\n");

	mutex_lock(&venc.venc_lock);

	config = venc_timings_to_config(&venc.vm);

	/* Invert due to VENC_L21_WC_CTL:INV=1 */
	venc.wss_data = (wss ^ 0xfffff) << 8;

	r = venc_runtime_get();
	if (r)
		goto err;

	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
			venc.wss_data);

	venc_runtime_put();

err:
	mutex_unlock(&venc.venc_lock);

	return r;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 98 98.00% 3 60.00%
Archit Taneja 1 1.00% 1 20.00%
Peter Ujfalusi 1 1.00% 1 20.00%
Total 100 100.00% 5 100.00%



static void venc_set_type(struct omap_dss_device *dssdev,
		enum omap_dss_venc_type type)
{
	mutex_lock(&venc.venc_lock);

	venc.type = type;

	mutex_unlock(&venc.venc_lock);
}

Contributors
Person Tokens Prop Commits CommitProp
Archit Taneja 35 94.59% 1 50.00%
Tomi Valkeinen 2 5.41% 1 50.00%
Total 37 100.00% 2 100.00%



static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
		bool invert_polarity)
{
	mutex_lock(&venc.venc_lock);

	venc.invert_polarity = invert_polarity;

	mutex_unlock(&venc.venc_lock);
}

Contributors
Person Tokens Prop Commits CommitProp
Archit Taneja 34 94.44% 1 50.00%
Tomi Valkeinen 2 5.56% 1 50.00%
Total 36 100.00% 2 100.00%



static int venc_init_regulator(void)
{
	struct regulator *vdda_dac;

	if (venc.vdda_dac_reg != NULL)
		return 0;

	if (venc.pdev->dev.of_node)
		vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
	else
		vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");

	if (IS_ERR(vdda_dac)) {
		if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
			DSSERR("can't get VDDA_DAC regulator\n");
		return PTR_ERR(vdda_dac);
	}

	venc.vdda_dac_reg = vdda_dac;

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 102 100.00% 6 100.00%
Total 102 100.00% 6 100.00%



static void venc_dump_regs(struct seq_file *s)
{

#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))

	if (venc_runtime_get())
		return;

	DUMPREG(VENC_F_CONTROL);
	DUMPREG(VENC_VIDOUT_CTRL);
	DUMPREG(VENC_SYNC_CTRL);
	DUMPREG(VENC_LLEN);
	DUMPREG(VENC_FLENS);
	DUMPREG(VENC_HFLTR_CTRL);
	DUMPREG(VENC_CC_CARR_WSS_CARR);
	DUMPREG(VENC_C_PHASE);
	DUMPREG(VENC_GAIN_U);
	DUMPREG(VENC_GAIN_V);
	DUMPREG(VENC_GAIN_Y);
	DUMPREG(VENC_BLACK_LEVEL);
	DUMPREG(VENC_BLANK_LEVEL);
	DUMPREG(VENC_X_COLOR);
	DUMPREG(VENC_M_CONTROL);
	DUMPREG(VENC_BSTAMP_WSS_DATA);
	DUMPREG(VENC_S_CARR);
	DUMPREG(VENC_LINE21);
	DUMPREG(VENC_LN_SEL);
	DUMPREG(VENC_L21__WC_CTL);
	DUMPREG(VENC_HTRIGGER_VTRIGGER);
	DUMPREG(VENC_SAVID__EAVID);
	DUMPREG(VENC_FLEN__FAL);
	DUMPREG(VENC_LAL__PHASE_RESET);
	DUMPREG(VENC_HS_INT_START_STOP_X);
	DUMPREG(VENC_HS_EXT_START_STOP_X);
	DUMPREG(VENC_VS_INT_START_X);
	DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
	DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
	DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
	DUMPREG(VENC_VS_EXT_STOP_Y);
	DUMPREG(VENC_AVID_START_STOP_X);
	DUMPREG(VENC_AVID_START_STOP_Y);
	DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
	DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
	DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
	DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
	DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
	DUMPREG(VENC_GEN_CTRL);
	DUMPREG(VENC_OUTPUT_CONTROL);
	DUMPREG(VENC_OUTPUT_TEST);

	venc_runtime_put();


#undef DUMPREG
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 235 100.00% 3 100.00%
Total 235 100.00% 3 100.00%



static int venc_get_clocks(struct platform_device *pdev)
{
	struct clk *clk;

	if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
		clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
		if (IS_ERR(clk)) {
			DSSERR("can't get tv_dac_clk\n");
			return PTR_ERR(clk);
		}
	} else {
		clk = NULL;
	}

	venc.tv_dac_clk = clk;

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 72 98.63% 1 50.00%
Archit Taneja 1 1.37% 1 50.00%
Total 73 100.00% 2 100.00%



static int venc_connect(struct omap_dss_device *dssdev,
		struct omap_dss_device *dst)
{
	enum omap_channel channel = dssdev->dispc_channel;
	int r;

	r = venc_init_regulator();
	if (r)
		return r;

	r = dss_mgr_connect(channel, dssdev);
	if (r)
		return r;

	r = omapdss_output_set_device(dssdev, dst);
	if (r) {
		DSSERR("failed to connect output to new device: %s\n",
				dst->name);
		dss_mgr_disconnect(channel, dssdev);
		return r;
	}

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 92 100.00% 2 100.00%
Total 92 100.00% 2 100.00%



static void venc_disconnect(struct omap_dss_device *dssdev,
		struct omap_dss_device *dst)
{
	enum omap_channel channel = dssdev->dispc_channel;

	WARN_ON(dst != dssdev->dst);

	if (dst != dssdev->dst)
		return;

	omapdss_output_unset_device(dssdev);

	dss_mgr_disconnect(channel, dssdev);
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 54 100.00% 3 100.00%
Total 54 100.00% 3 100.00%


static const struct omapdss_atv_ops venc_ops = {
	.connect = venc_connect,
	.disconnect = venc_disconnect,

	.enable = venc_display_enable,
	.disable = venc_display_disable,

	.check_timings = venc_check_timings,
	.set_timings = venc_set_timings,
	.get_timings = venc_get_timings,

	.set_type = venc_set_type,
	.invert_vid_out_polarity = venc_invert_vid_out_polarity,

	.set_wss = venc_set_wss,
	.get_wss = venc_get_wss,
};



static void venc_init_output(struct platform_device *pdev)
{
	struct omap_dss_device *out = &venc.output;

	out->dev = &pdev->dev;
	out->id = OMAP_DSS_OUTPUT_VENC;
	out->output_type = OMAP_DISPLAY_TYPE_VENC;
	out->name = "venc.0";
	out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
	out->ops.atv = &venc_ops;
	out->owner = THIS_MODULE;

	omapdss_register_output(out);
}

Contributors
Person Tokens Prop Commits CommitProp
Archit Taneja 40 54.05% 1 14.29%
Tomi Valkeinen 34 45.95% 6 85.71%
Total 74 100.00% 7 100.00%



static void venc_uninit_output(struct platform_device *pdev)
{
	struct omap_dss_device *out = &venc.output;

	omapdss_unregister_output(out);
}

Contributors
Person Tokens Prop Commits CommitProp
Archit Taneja 24 92.31% 1 33.33%
Tomi Valkeinen 2 7.69% 2 66.67%
Total 26 100.00% 3 100.00%



static int venc_probe_of(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct device_node *ep;
	u32 channels;
	int r;

	ep = omapdss_of_get_first_endpoint(node);
	if (!ep)
		return 0;

	venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");

	r = of_property_read_u32(ep, "ti,channels", &channels);
	if (r) {
		dev_err(&pdev->dev,
			"failed to read property 'ti,channels': %d\n", r);
		goto err;
	}

	switch (channels) {
	case 1:
		venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
		break;
	case 2:
		venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
		break;
	default:
		dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
		r = -EINVAL;
		goto err;
	}

	of_node_put(ep);

	return 0;
err:
	of_node_put(ep);

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 157 100.00% 1 100.00%
Total 157 100.00% 1 100.00%

/* VENC HW IP initialisation */


static int venc_bind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	u8 rev_id;
	struct resource *venc_mem;
	int r;

	venc.pdev = pdev;

	mutex_init(&venc.venc_lock);

	venc.wss_data = 0;

	venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
	if (!venc_mem) {
		DSSERR("can't get IORESOURCE_MEM VENC\n");
		return -EINVAL;
	}

	venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
				 resource_size(venc_mem));
	if (!venc.base) {
		DSSERR("can't ioremap VENC\n");
		return -ENOMEM;
	}

	r = venc_get_clocks(pdev);
	if (r)
		return r;

	pm_runtime_enable(&pdev->dev);

	r = venc_runtime_get();
	if (r)
		goto err_runtime_get;

	rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
	dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);

	venc_runtime_put();

	if (pdev->dev.of_node) {
		r = venc_probe_of(pdev);
		if (r) {
			DSSERR("Invalid DT data\n");
			goto err_probe_of;
		}
	}

	dss_debugfs_create_file("venc", venc_dump_regs);

	venc_init_output(pdev);

	return 0;

err_probe_of:
err_runtime_get:
	pm_runtime_disable(&pdev->dev);
	return r;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 125 49.41% 7 58.33%
Senthilvadivu Guruswamy 111 43.87% 2 16.67%
Julia Lawall 6 2.37% 1 8.33%
Sumit Semwal 6 2.37% 1 8.33%
Archit Taneja 5 1.98% 1 8.33%
Total 253 100.00% 12 100.00%



static void venc_unbind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);

	venc_uninit_output(pdev);

	pm_runtime_disable(&pdev->dev);
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 32 74.42% 2 50.00%
Senthilvadivu Guruswamy 6 13.95% 1 25.00%
Archit Taneja 5 11.63% 1 25.00%
Total 43 100.00% 4 100.00%


static const struct component_ops venc_component_ops = {
	.bind	= venc_bind,
	.unbind	= venc_unbind,
};



static int venc_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &venc_component_ops);
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 23 100.00% 1 100.00%
Total 23 100.00% 1 100.00%



static int venc_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &venc_component_ops);
	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 21 84.00% 1 50.00%
Senthilvadivu Guruswamy 4 16.00% 1 50.00%
Total 25 100.00% 2 100.00%



static int venc_runtime_suspend(struct device *dev)
{
	if (venc.tv_dac_clk)
		clk_disable_unprepare(venc.tv_dac_clk);

	dispc_runtime_put();

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 29 96.67% 1 50.00%
Rajendra Nayak 1 3.33% 1 50.00%
Total 30 100.00% 2 100.00%



static int venc_runtime_resume(struct device *dev)
{
	int r;

	r = dispc_runtime_get();
	if (r < 0)
		return r;

	if (venc.tv_dac_clk)
		clk_prepare_enable(venc.tv_dac_clk);

	return 0;
}

Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 43 97.73% 2 66.67%
Rajendra Nayak 1 2.27% 1 33.33%
Total 44 100.00% 3 100.00%


static const struct dev_pm_ops venc_pm_ops = {
	.runtime_suspend = venc_runtime_suspend,
	.runtime_resume = venc_runtime_resume,
};


static const struct of_device_id venc_of_match[] = {
	{ .compatible = "ti,omap2-venc", },
	{ .compatible = "ti,omap3-venc", },
	{ .compatible = "ti,omap4-venc", },
	{},
};


static struct platform_driver omap_venchw_driver = {
	.probe		= venc_probe,
	.remove		= venc_remove,
	.driver         = {
		.name   = "omapdss_venc",
		.pm	= &venc_pm_ops,
		.of_match_table = venc_of_match,
		.suppress_bind_attrs = true,
        },
};



int __init venc_init_platform_driver(void)
{
	return platform_driver_register(&omap_venchw_driver);
}

Contributors
Person Tokens Prop Commits CommitProp
Senthilvadivu Guruswamy 13 86.67% 1 33.33%
Tomi Valkeinen 2 13.33% 2 66.67%
Total 15 100.00% 3 100.00%



void venc_uninit_platform_driver(void)
{
	platform_driver_unregister(&omap_venchw_driver);
}
Contributors
Person Tokens Prop Commits CommitProp
Senthilvadivu Guruswamy 12 92.31% 1 50.00%
Tomi Valkeinen 1 7.69% 1 50.00%
Total 13 100.00% 2 100.00%

Overall Contributors
Person Tokens Prop Commits CommitProp
Tomi Valkeinen 3504 86.99% 44 57.14%
Archit Taneja 249 6.18% 11 14.29%
Senthilvadivu Guruswamy 174 4.32% 2 2.60%
Peter Ujfalusi 81 2.01% 16 20.78%
Mark Brown 6 0.15% 1 1.30%
Julia Lawall 6 0.15% 1 1.30%
Sumit Semwal 6 0.15% 1 1.30%
Rajendra Nayak 2 0.05% 1 1.30%
Total 4028 100.00% 77 100.00%
Directory: drivers/gpu/drm/omapdrm/dss

Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.
Created with cregit.
Person	Tokens	Prop	Commits	CommitProp
Tomi Valkeinen	24	100.00%	1	100.00%
Total	24	100.00%	1	100.00%
cregit-Linux how code gets into the kernel

Release 4.11 drivers/gpu/drm/omapdrm/dss/venc.c

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