Release 4.11 drivers/mtd/nand/ndfc.c
/*
* Overview:
* Platform independent driver for NDFC (NanD Flash Controller)
* integrated into EP440 cores
*
* Ported to an OF platform driver by Sean MacLennan
*
* The NDFC supports multiple chips, but this driver only supports a
* single chip since I do not have access to any boards with
* multiple chips.
*
* Author: Thomas Gleixner
*
* Copyright 2006 IBM
* Copyright 2008 PIKA Technologies
* Sean MacLennan <smaclennan@pikatech.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/module.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/ndfc.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/io.h>
#define NDFC_MAX_CS 4
struct ndfc_controller {
struct platform_device *ofdev;
void __iomem *ndfcbase;
struct nand_chip chip;
int chip_select;
struct nand_hw_control ndfc_control;
};
static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
static void ndfc_select_chip(struct mtd_info *mtd, int chip)
{
uint32_t ccr;
struct nand_chip *nchip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(nchip);
ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
if (chip >= 0) {
ccr &= ~NDFC_CCR_BS_MASK;
ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
} else
ccr |= NDFC_CCR_RESET_CE;
out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 68 | 77.27% | 1 | 20.00% |
| Felix Radensky | 8 | 9.09% | 1 | 20.00% |
| Boris Brezillon | 6 | 6.82% | 2 | 40.00% |
| Sean MacLennan | 6 | 6.82% | 1 | 20.00% |
| Total | 88 | 100.00% | 5 | 100.00% |
static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
else
writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 64 | 82.05% | 3 | 50.00% |
| Felix Radensky | 8 | 10.26% | 1 | 16.67% |
| Boris Brezillon | 6 | 7.69% | 2 | 33.33% |
| Total | 78 | 100.00% | 6 | 100.00% |
static int ndfc_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 28 | 65.12% | 1 | 20.00% |
| Felix Radensky | 8 | 18.60% | 1 | 20.00% |
| Boris Brezillon | 6 | 13.95% | 2 | 40.00% |
| Sean MacLennan | 1 | 2.33% | 1 | 20.00% |
| Total | 43 | 100.00% | 5 | 100.00% |
static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
{
uint32_t ccr;
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
ccr |= NDFC_CCR_RESET_ECC;
out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
wmb();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 48 | 72.73% | 1 | 20.00% |
| Felix Radensky | 8 | 12.12% | 1 | 20.00% |
| Boris Brezillon | 6 | 9.09% | 2 | 40.00% |
| Sean MacLennan | 4 | 6.06% | 1 | 20.00% |
| Total | 66 | 100.00% | 5 | 100.00% |
static int ndfc_calculate_ecc(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_code)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
uint32_t ecc;
uint8_t *p = (uint8_t *)&ecc;
wmb();
ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[1];
ecc_code[1] = p[2];
ecc_code[2] = p[3];
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 84 | 82.35% | 1 | 16.67% |
| Felix Radensky | 8 | 7.84% | 1 | 16.67% |
| Boris Brezillon | 6 | 5.88% | 2 | 33.33% |
| Feng Kan | 2 | 1.96% | 1 | 16.67% |
| Sean MacLennan | 2 | 1.96% | 1 | 16.67% |
| Total | 102 | 100.00% | 6 | 100.00% |
/*
* Speedups for buffer read/write/verify
*
* NDFC allows 32bit read/write of data. So we can speed up the buffer
* functions. No further checking, as nand_base will always read/write
* page aligned.
*/
static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
uint32_t *p = (uint32_t *) buf;
for(;len > 0; len -= 4)
*p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 57 | 79.17% | 1 | 20.00% |
| Felix Radensky | 8 | 11.11% | 1 | 20.00% |
| Boris Brezillon | 6 | 8.33% | 2 | 40.00% |
| Sean MacLennan | 1 | 1.39% | 1 | 20.00% |
| Total | 72 | 100.00% | 5 | 100.00% |
static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct ndfc_controller *ndfc = nand_get_controller_data(chip);
uint32_t *p = (uint32_t *) buf;
for(;len > 0; len -= 4)
out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 54 | 73.97% | 1 | 20.00% |
| Felix Radensky | 8 | 10.96% | 1 | 20.00% |
| Boris Brezillon | 6 | 8.22% | 2 | 40.00% |
| Sean MacLennan | 5 | 6.85% | 1 | 20.00% |
| Total | 73 | 100.00% | 5 | 100.00% |
/*
* Initialize chip structure
*/
static int ndfc_chip_init(struct ndfc_controller *ndfc,
struct device_node *node)
{
struct device_node *flash_np;
struct nand_chip *chip = &ndfc->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
chip->cmd_ctrl = ndfc_hwcontrol;
chip->dev_ready = ndfc_ready;
chip->select_chip = ndfc_select_chip;
chip->chip_delay = 50;
chip->controller = &ndfc->ndfc_control;
chip->read_buf = ndfc_read_buf;
chip->write_buf = ndfc_write_buf;
chip->ecc.correct = nand_correct_data;
chip->ecc.hwctl = ndfc_enable_hwecc;
chip->ecc.calculate = ndfc_calculate_ecc;
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.size = 256;
chip->ecc.bytes = 3;
chip->ecc.strength = 1;
nand_set_controller_data(chip, ndfc);
mtd->dev.parent = &ndfc->ofdev->dev;
flash_np = of_get_next_child(node, NULL);
if (!flash_np)
return -ENODEV;
nand_set_flash_node(chip, flash_np);
mtd->name = kasprintf(GFP_KERNEL, "%s.%s", dev_name(&ndfc->ofdev->dev),
flash_np->name);
if (!mtd->name) {
ret = -ENOMEM;
goto err;
}
ret = nand_scan(mtd, 1);
if (ret)
goto err;
ret = mtd_device_register(mtd, NULL, 0);
err:
of_node_put(flash_np);
if (ret)
kfree(mtd->name);
return ret;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 166 | 55.33% | 3 | 21.43% |
| Sean MacLennan | 81 | 27.00% | 1 | 7.14% |
| Boris Brezillon | 19 | 6.33% | 2 | 14.29% |
| Frans Klaver | 9 | 3.00% | 1 | 7.14% |
| Mike Dunn | 7 | 2.33% | 1 | 7.14% |
| Brian Norris | 6 | 2.00% | 1 | 7.14% |
| Dmitry Baryshkov | 4 | 1.33% | 3 | 21.43% |
| Felix Radensky | 4 | 1.33% | 1 | 7.14% |
| Kay Sievers | 4 | 1.33% | 1 | 7.14% |
| Total | 300 | 100.00% | 14 | 100.00% |
static int ndfc_probe(struct platform_device *ofdev)
{
struct ndfc_controller *ndfc;
const __be32 *reg;
u32 ccr;
u32 cs;
int err, len;
/* Read the reg property to get the chip select */
reg = of_get_property(ofdev->dev.of_node, "reg", &len);
if (reg == NULL || len != 12) {
dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
return -ENOENT;
}
cs = be32_to_cpu(reg[0]);
if (cs >= NDFC_MAX_CS) {
dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
return -EINVAL;
}
ndfc = &ndfc_ctrl[cs];
ndfc->chip_select = cs;
nand_hw_control_init(&ndfc->ndfc_control);
ndfc->ofdev = ofdev;
dev_set_drvdata(&ofdev->dev, ndfc);
ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
if (!ndfc->ndfcbase) {
dev_err(&ofdev->dev, "failed to get memory\n");
return -EIO;
}
ccr = NDFC_CCR_BS(ndfc->chip_select);
/* It is ok if ccr does not exist - just default to 0 */
reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
if (reg)
ccr |= be32_to_cpup(reg);
out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
/* Set the bank settings if given */
reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
if (reg) {
int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
}
err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
if (err) {
iounmap(ndfc->ndfcbase);
return err;
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sean MacLennan | 150 | 47.62% | 1 | 11.11% |
| Thomas Gleixner | 69 | 21.90% | 1 | 11.11% |
| Felix Radensky | 62 | 19.68% | 1 | 11.11% |
| Grant C. Likely | 16 | 5.08% | 2 | 22.22% |
| Ian Munsie | 10 | 3.17% | 1 | 11.11% |
| Stefan Roese | 4 | 1.27% | 1 | 11.11% |
| Dan Carpenter | 3 | 0.95% | 1 | 11.11% |
| Marc Gonzalez | 1 | 0.32% | 1 | 11.11% |
| Total | 315 | 100.00% | 9 | 100.00% |
static int ndfc_remove(struct platform_device *ofdev)
{
struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
struct mtd_info *mtd = nand_to_mtd(&ndfc->chip);
nand_release(mtd);
kfree(mtd->name);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 25 | 48.08% | 1 | 20.00% |
| Boris Brezillon | 12 | 23.08% | 1 | 20.00% |
| Sean MacLennan | 8 | 15.38% | 1 | 20.00% |
| Axel Lin | 6 | 11.54% | 1 | 20.00% |
| Grant C. Likely | 1 | 1.92% | 1 | 20.00% |
| Total | 52 | 100.00% | 5 | 100.00% |
static const struct of_device_id ndfc_match[] = {
{ .compatible = "ibm,ndfc", },
{}
};
MODULE_DEVICE_TABLE(of, ndfc_match);
static struct platform_driver ndfc_driver = {
.driver = {
.name = "ndfc",
.of_match_table = ndfc_match,
},
.probe = ndfc_probe,
.remove = ndfc_remove,
};
module_platform_driver(ndfc_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
MODULE_DESCRIPTION("OF Platform driver for NDFC");
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Thomas Gleixner | 748 | 55.95% | 4 | 12.90% |
| Sean MacLennan | 299 | 22.36% | 1 | 3.23% |
| Felix Radensky | 129 | 9.65% | 1 | 3.23% |
| Boris Brezillon | 73 | 5.46% | 3 | 9.68% |
| Grant C. Likely | 21 | 1.57% | 4 | 12.90% |
| Ian Munsie | 10 | 0.75% | 1 | 3.23% |
| Frans Klaver | 9 | 0.67% | 1 | 3.23% |
| Axel Lin | 8 | 0.60% | 2 | 6.45% |
| Mike Dunn | 7 | 0.52% | 1 | 3.23% |
| Brian Norris | 7 | 0.52% | 2 | 6.45% |
| Kay Sievers | 6 | 0.45% | 2 | 6.45% |
| Dmitry Baryshkov | 4 | 0.30% | 3 | 9.68% |
| Stefan Roese | 4 | 0.30% | 1 | 3.23% |
| Rob Herring | 3 | 0.22% | 1 | 3.23% |
| Tejun Heo | 3 | 0.22% | 1 | 3.23% |
| Dan Carpenter | 3 | 0.22% | 1 | 3.23% |
| Feng Kan | 2 | 0.15% | 1 | 3.23% |
| Marc Gonzalez | 1 | 0.07% | 1 | 3.23% |
| Total | 1337 | 100.00% | 31 | 100.00% |
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