Release 4.11 drivers/parisc/gsc.c
/*
* Interrupt management for most GSC and related devices.
*
* (c) Copyright 1999 Alex deVries for The Puffin Group
* (c) Copyright 1999 Grant Grundler for Hewlett-Packard
* (c) Copyright 1999 Matthew Wilcox
* (c) Copyright 2000 Helge Deller
* (c) Copyright 2001 Matthew Wilcox for Hewlett-Packard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/types.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include "gsc.h"
#undef DEBUG
#ifdef DEBUG
#define DEBPRINTK printk
#else
#define DEBPRINTK(x,...)
#endif
int gsc_alloc_irq(struct gsc_irq *i)
{
int irq = txn_alloc_irq(GSC_EIM_WIDTH);
if (irq < 0) {
printk("cannot get irq\n");
return irq;
}
i->txn_addr = txn_alloc_addr(irq);
i->txn_data = txn_alloc_data(irq);
i->irq = irq;
return irq;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 61 | 100.00% | 2 | 100.00% |
Total | 61 | 100.00% | 2 | 100.00% |
int gsc_claim_irq(struct gsc_irq *i, int irq)
{
int c = irq;
irq += CPU_IRQ_BASE; /* virtualize the IRQ first */
irq = txn_claim_irq(irq);
if (irq < 0) {
printk("cannot claim irq %d\n", c);
return irq;
}
i->txn_addr = txn_alloc_addr(irq);
i->txn_data = txn_alloc_data(irq);
i->irq = irq;
return irq;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 75 | 100.00% | 2 | 100.00% |
Total | 75 | 100.00% | 2 | 100.00% |
EXPORT_SYMBOL(gsc_alloc_irq);
EXPORT_SYMBOL(gsc_claim_irq);
/* Common interrupt demultiplexer used by Asp, Lasi & Wax. */
irqreturn_t gsc_asic_intr(int gsc_asic_irq, void *dev)
{
unsigned long irr;
struct gsc_asic *gsc_asic = dev;
irr = gsc_readl(gsc_asic->hpa + OFFSET_IRR);
if (irr == 0)
return IRQ_NONE;
DEBPRINTK("%s intr, mask=0x%x\n", gsc_asic->name, irr);
do {
int local_irq = __ffs(irr);
unsigned int irq = gsc_asic->global_irq[local_irq];
generic_handle_irq(irq);
irr &= ~(1 << local_irq);
} while (irr);
return IRQ_HANDLED;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 97 | 98.98% | 3 | 75.00% |
Kyle McMartin | 1 | 1.02% | 1 | 25.00% |
Total | 98 | 100.00% | 4 | 100.00% |
int gsc_find_local_irq(unsigned int irq, int *global_irqs, int limit)
{
int local_irq;
for (local_irq = 0; local_irq < limit; local_irq++) {
if (global_irqs[local_irq] == irq)
return local_irq;
}
return NO_IRQ;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 49 | 100.00% | 2 | 100.00% |
Total | 49 | 100.00% | 2 | 100.00% |
static void gsc_asic_mask_irq(struct irq_data *d)
{
struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
u32 imr;
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
irq_dev->name, imr);
/* Disable the IRQ line by clearing the bit in the IMR */
imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
imr &= ~(1 << local_irq);
gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 71 | 78.89% | 2 | 28.57% |
Thomas Gleixner | 10 | 11.11% | 1 | 14.29% |
Yinghai Lu | 5 | 5.56% | 1 | 14.29% |
Kyle McMartin | 3 | 3.33% | 2 | 28.57% |
Harvey Harrison | 1 | 1.11% | 1 | 14.29% |
Total | 90 | 100.00% | 7 | 100.00% |
static void gsc_asic_unmask_irq(struct irq_data *d)
{
struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
u32 imr;
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
irq_dev->name, imr);
/* Enable the IRQ line by setting the bit in the IMR */
imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
imr |= 1 << local_irq;
gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
/*
* FIXME: read IPR to make sure the IRQ isn't already pending.
* If so, we need to read IRR and manually call do_irq().
*/
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 69 | 78.41% | 2 | 28.57% |
Thomas Gleixner | 10 | 11.36% | 1 | 14.29% |
Yinghai Lu | 5 | 5.68% | 1 | 14.29% |
Kyle McMartin | 3 | 3.41% | 2 | 28.57% |
Harvey Harrison | 1 | 1.14% | 1 | 14.29% |
Total | 88 | 100.00% | 7 | 100.00% |
static struct irq_chip gsc_asic_interrupt_type = {
.name = "GSC-ASIC",
.irq_unmask = gsc_asic_unmask_irq,
.irq_mask = gsc_asic_mask_irq,
};
int gsc_assign_irq(struct irq_chip *type, void *data)
{
static int irq = GSC_IRQ_BASE;
if (irq > GSC_IRQ_MAX)
return NO_IRQ;
irq_set_chip_and_handler(irq, type, handle_simple_irq);
irq_set_chip_data(irq, data);
return irq++;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 37 | 75.51% | 2 | 28.57% |
Kyle McMartin | 7 | 14.29% | 1 | 14.29% |
Thomas Gleixner | 3 | 6.12% | 2 | 28.57% |
James Bottomley | 1 | 2.04% | 1 | 14.29% |
Yinghai Lu | 1 | 2.04% | 1 | 14.29% |
Total | 49 | 100.00% | 7 | 100.00% |
void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp)
{
int irq = asic->global_irq[local_irq];
if (irq <= 0) {
irq = gsc_assign_irq(&gsc_asic_interrupt_type, asic);
if (irq == NO_IRQ)
return;
asic->global_irq[local_irq] = irq;
}
*irqp = irq;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 66 | 100.00% | 3 | 100.00% |
Total | 66 | 100.00% | 3 | 100.00% |
struct gsc_fixup_struct {
void (*choose_irq)(struct parisc_device *, void *);
void *ctrl;
};
static int gsc_fixup_irqs_callback(struct device *dev, void *data)
{
struct parisc_device *padev = to_parisc_device(dev);
struct gsc_fixup_struct *gf = data;
/* work-around for 715/64 and others which have parent
at path [5] and children at path [5/0/x] */
if (padev->id.hw_type == HPHW_FAULTY)
gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq);
gf->choose_irq(padev, gf->ctrl);
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
James Bottomley | 51 | 72.86% | 1 | 50.00% |
Matthew Wilcox | 19 | 27.14% | 1 | 50.00% |
Total | 70 | 100.00% | 2 | 100.00% |
void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
void (*choose_irq)(struct parisc_device *, void *))
{
struct gsc_fixup_struct data = {
.choose_irq = choose_irq,
.ctrl = ctrl,
};
device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 40 | 70.18% | 3 | 75.00% |
James Bottomley | 17 | 29.82% | 1 | 25.00% |
Total | 57 | 100.00% | 4 | 100.00% |
int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic)
{
struct resource *res;
int i;
gsc_asic->gsc = parent;
/* Initialise local irq -> global irq mapping */
for (i = 0; i < 32; i++) {
gsc_asic->global_irq[i] = NO_IRQ;
}
/* allocate resource region */
res = request_mem_region(gsc_asic->hpa, 0x100000, gsc_asic->name);
if (res) {
res->flags = IORESOURCE_MEM; /* do not mark it busy ! */
}
#if 0
printk(KERN_WARNING "%s IRQ %d EIM 0x%x", gsc_asic->name,
parent->irq, gsc_asic->eim);
if (gsc_readl(gsc_asic->hpa + OFFSET_IMR))
printk(" IMR is non-zero! (0x%x)",
gsc_readl(gsc_asic->hpa + OFFSET_IMR));
printk("\n");
#endif
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 92 | 100.00% | 3 | 100.00% |
Total | 92 | 100.00% | 3 | 100.00% |
extern struct parisc_driver lasi_driver;
extern struct parisc_driver asp_driver;
extern struct parisc_driver wax_driver;
void __init gsc_init(void)
{
#ifdef CONFIG_GSC_LASI
register_parisc_driver(&lasi_driver);
register_parisc_driver(&asp_driver);
#endif
#ifdef CONFIG_GSC_WAX
register_parisc_driver(&wax_driver);
#endif
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 36 | 100.00% | 1 | 100.00% |
Total | 36 | 100.00% | 1 | 100.00% |
Overall Contributors
Person | Tokens | Prop | Commits | CommitProp |
Matthew Wilcox | 807 | 84.50% | 7 | 41.18% |
James Bottomley | 92 | 9.63% | 2 | 11.76% |
Thomas Gleixner | 27 | 2.83% | 4 | 23.53% |
Kyle McMartin | 16 | 1.68% | 2 | 11.76% |
Yinghai Lu | 11 | 1.15% | 1 | 5.88% |
Harvey Harrison | 2 | 0.21% | 1 | 5.88% |
Total | 955 | 100.00% | 17 | 100.00% |
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