Release 4.11 drivers/soc/fsl/qe/gpio.c
/*
* QUICC Engine GPIOs
*
* Copyright (c) MontaVista Software, Inc. 2008.
*
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/driver.h>
/* FIXME: needed for gpio_to_chip() get rid of this */
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <soc/fsl/qe/qe.h>
struct qe_gpio_chip {
struct of_mm_gpio_chip mm_gc;
spinlock_t lock;
unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0
/* shadowed data register to clear/set bits safely */
u32 cpdata;
/* saved_regs used to restore dedicated functions */
struct qe_pio_regs saved_regs;
};
static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
struct qe_gpio_chip *qe_gc =
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
qe_gc->cpdata = in_be32(®s->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
}
Contributors
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| Anton Vorontsov | 122 | 95.31% | 2 | 66.67% |
| Christophe Leroy | 6 | 4.69% | 1 | 33.33% |
| Total | 128 | 100.00% | 3 | 100.00% |
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
return !!(in_be32(®s->cpdata) & pin_mask);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 59 | 93.65% | 1 | 50.00% |
| Linus Walleij | 4 | 6.35% | 1 | 50.00% |
| Total | 63 | 100.00% | 2 | 100.00% |
static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
spin_lock_irqsave(&qe_gc->lock, flags);
if (val)
qe_gc->cpdata |= pin_mask;
else
qe_gc->cpdata &= ~pin_mask;
out_be32(®s->cpdata, qe_gc->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
Contributors
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| Anton Vorontsov | 113 | 98.26% | 1 | 50.00% |
| Linus Walleij | 2 | 1.74% | 1 | 50.00% |
| Total | 115 | 100.00% | 2 | 100.00% |
static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&qe_gc->lock, flags);
__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 77 | 97.47% | 1 | 50.00% |
| Linus Walleij | 2 | 2.53% | 1 | 50.00% |
| Total | 79 | 100.00% | 2 | 100.00% |
static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
unsigned long flags;
qe_gpio_set(gc, gpio, val);
spin_lock_irqsave(&qe_gc->lock, flags);
__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 80 | 87.91% | 1 | 33.33% |
| Michael Barkowski | 9 | 9.89% | 1 | 33.33% |
| Linus Walleij | 2 | 2.20% | 1 | 33.33% |
| Total | 91 | 100.00% | 3 | 100.00% |
struct qe_pin {
/*
* The qe_gpio_chip name is unfortunate, we should change that to
* something like qe_pio_controller. Someday.
*/
struct qe_gpio_chip *controller;
int num;
};
/**
* qe_pin_request - Request a QE pin
* @np: device node to get a pin from
* @index: index of a pin in the device tree
* Context: non-atomic
*
* This function return qe_pin so that you could use it with the rest of
* the QE Pin Multiplexing API.
*/
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
struct qe_pin *qe_pin;
struct gpio_chip *gc;
struct of_mm_gpio_chip *mm_gc;
struct qe_gpio_chip *qe_gc;
int err;
unsigned long flags;
qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
if (!qe_pin) {
pr_debug("%s: can't allocate memory\n", __func__);
return ERR_PTR(-ENOMEM);
}
err = of_get_gpio(np, index);
if (err < 0)
goto err0;
gc = gpio_to_chip(err);
if (WARN_ON(!gc))
goto err0;
if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
pr_debug("%s: tried to get a non-qe pin\n", __func__);
err = -EINVAL;
goto err0;
}
mm_gc = to_of_mm_gpio_chip(gc);
qe_gc = gpiochip_get_data(gc);
spin_lock_irqsave(&qe_gc->lock, flags);
err -= gc->base;
if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
qe_pin->controller = qe_gc;
qe_pin->num = err;
err = 0;
} else {
err = -EBUSY;
}
spin_unlock_irqrestore(&qe_gc->lock, flags);
if (!err)
return qe_pin;
err0:
kfree(qe_pin);
pr_debug("%s failed with status %d\n", __func__, err);
return ERR_PTR(err);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 227 | 89.37% | 2 | 40.00% |
| Grant C. Likely | 25 | 9.84% | 2 | 40.00% |
| Linus Walleij | 2 | 0.79% | 1 | 20.00% |
| Total | 254 | 100.00% | 5 | 100.00% |
EXPORT_SYMBOL(qe_pin_request);
/**
* qe_pin_free - Free a pin
* @qe_pin: pointer to the qe_pin structure
* Context: any
*
* This function frees the qe_pin structure and makes a pin available
* for further qe_pin_request() calls.
*/
void qe_pin_free(struct qe_pin *qe_pin)
{
struct qe_gpio_chip *qe_gc = qe_pin->controller;
unsigned long flags;
const int pin = qe_pin->num;
spin_lock_irqsave(&qe_gc->lock, flags);
test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
spin_unlock_irqrestore(&qe_gc->lock, flags);
kfree(qe_pin);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 69 | 100.00% | 1 | 100.00% |
| Total | 69 | 100.00% | 1 | 100.00% |
EXPORT_SYMBOL(qe_pin_free);
/**
* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
* @qe_pin: pointer to the qe_pin structure
* Context: any
*
* This function resets a pin to a dedicated peripheral function that
* has been set up by the firmware.
*/
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
struct qe_gpio_chip *qe_gc = qe_pin->controller;
struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
struct qe_pio_regs *sregs = &qe_gc->saved_regs;
int pin = qe_pin->num;
u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
unsigned long flags;
spin_lock_irqsave(&qe_gc->lock, flags);
if (second_reg) {
clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
} else {
clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
}
if (sregs->cpdata & mask1)
qe_gc->cpdata |= mask1;
else
qe_gc->cpdata &= ~mask1;
out_be32(®s->cpdata, qe_gc->cpdata);
clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 246 | 100.00% | 1 | 100.00% |
| Total | 246 | 100.00% | 1 | 100.00% |
EXPORT_SYMBOL(qe_pin_set_dedicated);
/**
* qe_pin_set_gpio - Set a pin to the GPIO mode
* @qe_pin: pointer to the qe_pin structure
* Context: any
*
* This function sets a pin to the GPIO mode.
*/
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
struct qe_gpio_chip *qe_gc = qe_pin->controller;
struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
unsigned long flags;
spin_lock_irqsave(&qe_gc->lock, flags);
/* Let's make it input by default, GPIO API is able to change that. */
__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 73 | 100.00% | 1 | 100.00% |
| Total | 73 | 100.00% | 1 | 100.00% |
EXPORT_SYMBOL(qe_pin_set_gpio);
static int __init qe_add_gpiochips(void)
{
struct device_node *np;
for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
int ret;
struct qe_gpio_chip *qe_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
if (!qe_gc) {
ret = -ENOMEM;
goto err;
}
spin_lock_init(&qe_gc->lock);
mm_gc = &qe_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = qe_gpio_save_regs;
gc->ngpio = QE_PIO_PINS;
gc->direction_input = qe_gpio_dir_in;
gc->direction_output = qe_gpio_dir_out;
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
if (ret)
goto err;
continue;
err:
pr_err("%s: registration failed with status %d\n",
np->full_name, ret);
kfree(qe_gc);
/* try others anyway */
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 166 | 98.22% | 3 | 75.00% |
| Linus Walleij | 3 | 1.78% | 1 | 25.00% |
| Total | 169 | 100.00% | 4 | 100.00% |
arch_initcall(qe_add_gpiochips);
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Anton Vorontsov | 1334 | 95.29% | 4 | 30.77% |
| Grant C. Likely | 25 | 1.79% | 2 | 15.38% |
| Linus Walleij | 19 | 1.36% | 2 | 15.38% |
| Michael Barkowski | 9 | 0.64% | 1 | 7.69% |
| Christophe Leroy | 6 | 0.43% | 1 | 7.69% |
| Paul Gortmaker | 3 | 0.21% | 1 | 7.69% |
| Tejun Heo | 3 | 0.21% | 1 | 7.69% |
| Zhao Qiang | 1 | 0.07% | 1 | 7.69% |
| Total | 1400 | 100.00% | 13 | 100.00% |
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