Release 4.11 drivers/staging/sm750fb/ddk750_mode.c
#include "ddk750_reg.h"
#include "ddk750_mode.h"
#include "ddk750_chip.h"
/*
* SM750LE only:
* This function takes care extra registers and bit fields required to set
* up a mode in SM750LE
*
* Explanation about Display Control register:
* HW only supports 7 predefined pixel clocks, and clock select is
* in bit 29:27 of Display Control register.
*/
static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
{
unsigned long x, y;
x = pModeParam->horizontal_display_end;
y = pModeParam->vertical_display_end;
/*
* SM750LE has to set up the top-left and bottom-right
* registers as well.
* Note that normal SM750/SM718 only use those two register for
* auto-centering mode.
*/
poke32(CRT_AUTO_CENTERING_TL, 0);
poke32(CRT_AUTO_CENTERING_BR,
(((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) &
CRT_AUTO_CENTERING_BR_BOTTOM_MASK) |
((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
/*
* Assume common fields in dispControl have been properly set before
* calling this function.
* This function only sets the extra fields in dispControl.
*/
/* Clear bit 29:27 of display control register */
dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK;
/* Set bit 29:27 of display control register for the right clock */
/* Note that SM750LE only need to supported 7 resolutions. */
if (x == 800 && y == 600)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41;
else if (x == 1024 && y == 768)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65;
else if (x == 1152 && y == 864)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
else if (x == 1280 && y == 768)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
else if (x == 1280 && y == 720)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74;
else if (x == 1280 && y == 960)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
else if (x == 1280 && y == 1024)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
else /* default to VGA clock */
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25;
/* Set bit 25:24 of display controller */
dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT);
/* Set bit 14 of display controller */
dispControl |= DISPLAY_CTRL_CLOCK_PHASE;
poke32(CRT_DISPLAY_CTRL, dispControl);
return dispControl;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sudip Mukherjee | 165 | 77.46% | 1 | 11.11% |
| Mike Rapoport | 41 | 19.25% | 4 | 44.44% |
| Matthieu Simon | 3 | 1.41% | 1 | 11.11% |
| Eric S. Stone | 2 | 0.94% | 1 | 11.11% |
| Phil Turnbull | 1 | 0.47% | 1 | 11.11% |
| Matej Vasek | 1 | 0.47% | 1 | 11.11% |
| Total | 213 | 100.00% | 9 | 100.00% |
/* only timing related registers will be programed */
static int programModeRegisters(mode_parameter_t *pModeParam,
struct pll_value *pll)
{
int ret = 0;
int cnt = 0;
unsigned int tmp, reg;
if (pll->clockType == SECONDARY_PLL) {
/* programe secondary pixel clock */
poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
poke32(CRT_HORIZONTAL_TOTAL,
(((pModeParam->horizontal_total - 1) <<
CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
CRT_HORIZONTAL_TOTAL_TOTAL_MASK) |
((pModeParam->horizontal_display_end - 1) &
CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK));
poke32(CRT_HORIZONTAL_SYNC,
((pModeParam->horizontal_sync_width <<
CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) &
CRT_HORIZONTAL_SYNC_WIDTH_MASK) |
((pModeParam->horizontal_sync_start - 1) &
CRT_HORIZONTAL_SYNC_START_MASK));
poke32(CRT_VERTICAL_TOTAL,
(((pModeParam->vertical_total - 1) <<
CRT_VERTICAL_TOTAL_TOTAL_SHIFT) &
CRT_VERTICAL_TOTAL_TOTAL_MASK) |
((pModeParam->vertical_display_end - 1) &
CRT_VERTICAL_TOTAL_DISPLAY_END_MASK));
poke32(CRT_VERTICAL_SYNC,
((pModeParam->vertical_sync_height <<
CRT_VERTICAL_SYNC_HEIGHT_SHIFT) &
CRT_VERTICAL_SYNC_HEIGHT_MASK) |
((pModeParam->vertical_sync_start - 1) &
CRT_VERTICAL_SYNC_START_MASK));
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (sm750_get_chip_type() == SM750LE) {
displayControlAdjust_SM750LE(pModeParam, tmp);
} else {
reg = peek32(CRT_DISPLAY_CTRL) &
~(DISPLAY_CTRL_VSYNC_PHASE |
DISPLAY_CTRL_HSYNC_PHASE |
DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE);
poke32(CRT_DISPLAY_CTRL, tmp | reg);
}
} else if (pll->clockType == PRIMARY_PLL) {
unsigned int reserved;
poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
reg = ((pModeParam->horizontal_total - 1) <<
PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
PANEL_HORIZONTAL_TOTAL_TOTAL_MASK;
reg |= ((pModeParam->horizontal_display_end - 1) &
PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK);
poke32(PANEL_HORIZONTAL_TOTAL, reg);
poke32(PANEL_HORIZONTAL_SYNC,
((pModeParam->horizontal_sync_width <<
PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) &
PANEL_HORIZONTAL_SYNC_WIDTH_MASK) |
((pModeParam->horizontal_sync_start - 1) &
PANEL_HORIZONTAL_SYNC_START_MASK));
poke32(PANEL_VERTICAL_TOTAL,
(((pModeParam->vertical_total - 1) <<
PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) &
PANEL_VERTICAL_TOTAL_TOTAL_MASK) |
((pModeParam->vertical_display_end - 1) &
PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK));
poke32(PANEL_VERTICAL_SYNC,
((pModeParam->vertical_sync_height <<
PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) &
PANEL_VERTICAL_SYNC_HEIGHT_MASK) |
((pModeParam->vertical_sync_start - 1) &
PANEL_VERTICAL_SYNC_START_MASK));
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (pModeParam->clock_phase_polarity)
tmp |= DISPLAY_CTRL_CLOCK_PHASE;
reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
PANEL_DISPLAY_CTRL_VSYNC;
reg = (peek32(PANEL_DISPLAY_CTRL) & ~reserved) &
~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE |
DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
DISPLAY_CTRL_PLANE);
/*
* May a hardware bug or just my test chip (not confirmed).
* PANEL_DISPLAY_CTRL register seems requiring few writes
* before a value can be successfully written in.
* Added some masks to mask out the reserved bits.
* Note: This problem happens by design. The hardware will wait
* for the next vertical sync to turn on/off the plane.
*/
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
while ((peek32(PANEL_DISPLAY_CTRL) & ~reserved) !=
(tmp | reg)) {
cnt++;
if (cnt > 1000)
break;
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
}
} else {
ret = -1;
}
return ret;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sudip Mukherjee | 294 | 55.68% | 1 | 5.88% |
| Mike Rapoport | 212 | 40.15% | 11 | 64.71% |
| Matthieu Simon | 16 | 3.03% | 1 | 5.88% |
| Arnd Bergmann | 2 | 0.38% | 1 | 5.88% |
| Mihaela Muraru | 2 | 0.38% | 1 | 5.88% |
| Eric S. Stone | 1 | 0.19% | 1 | 5.88% |
| Moshe Green | 1 | 0.19% | 1 | 5.88% |
| Total | 528 | 100.00% | 17 | 100.00% |
int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
{
struct pll_value pll;
unsigned int uiActualPixelClk;
pll.inputFreq = DEFAULT_INPUT_CLOCK;
pll.clockType = clock;
uiActualPixelClk = sm750_calc_pll_value(parm->pixel_clock, &pll);
if (sm750_get_chip_type() == SM750LE) {
/* set graphic mode via IO method */
outb_p(0x88, 0x3d4);
outb_p(0x06, 0x3d5);
}
programModeRegisters(parm, &pll);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sudip Mukherjee | 75 | 94.94% | 1 | 25.00% |
| Mihaela Muraru | 2 | 2.53% | 1 | 25.00% |
| Moshe Green | 1 | 1.27% | 1 | 25.00% |
| Arnd Bergmann | 1 | 1.27% | 1 | 25.00% |
| Total | 79 | 100.00% | 4 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sudip Mukherjee | 544 | 65.46% | 1 | 4.55% |
| Mike Rapoport | 253 | 30.45% | 14 | 63.64% |
| Matthieu Simon | 19 | 2.29% | 1 | 4.55% |
| Eric S. Stone | 4 | 0.48% | 1 | 4.55% |
| Mihaela Muraru | 4 | 0.48% | 1 | 4.55% |
| Arnd Bergmann | 3 | 0.36% | 1 | 4.55% |
| Moshe Green | 2 | 0.24% | 1 | 4.55% |
| Matej Vasek | 1 | 0.12% | 1 | 4.55% |
| Phil Turnbull | 1 | 0.12% | 1 | 4.55% |
| Total | 831 | 100.00% | 22 | 100.00% |
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