Release 4.11 drivers/watchdog/booke_wdt.c
/*
* Watchdog timer for PowerPC Book-E systems
*
* Author: Matthew McClintock
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/smp.h>
#include <linux/watchdog.h>
#include <asm/reg_booke.h>
#include <asm/time.h>
#include <asm/div64.h>
/* If the kernel parameter wdt=1, the watchdog will be enabled at boot.
* Also, the wdt_period sets the watchdog timer period timeout.
* For E500 cpus the wdt_period sets which bit changing from 0->1 will
* trigger a watchog timeout. This watchdog timeout will occur 3 times, the
* first time nothing will happen, the second time a watchdog exception will
* occur, and the final time the board will reset.
*/
#ifdef CONFIG_PPC_FSL_BOOK3E
#define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15))
#define WDTP_MASK (WDTP(0x3f))
#else
#define WDTP(x) (TCR_WP(x))
#define WDTP_MASK (TCR_WP_MASK)
#endif
static bool booke_wdt_enabled;
module_param(booke_wdt_enabled, bool, 0);
static int booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT;
module_param(booke_wdt_period, int, 0);
#ifdef CONFIG_PPC_FSL_BOOK3E
/* For the specified period, determine the number of seconds
* corresponding to the reset time. There will be a watchdog
* exception at approximately 3/5 of this time.
*
* The formula to calculate this is given by:
* 2.5 * (2^(63-period+1)) / timebase_freq
*
* In order to simplify things, we assume that period is
* at least 1. This will still result in a very long timeout.
*/
static unsigned long long period_to_sec(unsigned int period)
{
unsigned long long tmp = 1ULL << (64 - period);
unsigned long tmp2 = ppc_tb_freq;
/* tmp may be a very large number and we don't want to overflow,
* so divide the timebase freq instead of multiplying tmp
*/
tmp2 = tmp2 / 5 * 2;
do_div(tmp, tmp2);
return tmp;
}
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/*
* This procedure will find the highest period which will give a timeout
* greater than the one required. e.g. for a bus speed of 66666666 and
* and a parameter of 2 secs, then this procedure will return a value of 38.
*/
static unsigned int sec_to_period(unsigned int secs)
{
unsigned int period;
for (period = 63; period > 0; period--) {
if (period_to_sec(period) >= secs)
return period;
}
return 0;
}
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#define MAX_WDT_TIMEOUT period_to_sec(1)
#else /* CONFIG_PPC_FSL_BOOK3E */
static unsigned long long period_to_sec(unsigned int period)
{
return period;
}
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static unsigned int sec_to_period(unsigned int secs)
{
return secs;
}
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#define MAX_WDT_TIMEOUT 3
/* from Kconfig */
#endif /* !CONFIG_PPC_FSL_BOOK3E */
static void __booke_wdt_set(void *data)
{
u32 val;
struct watchdog_device *wdog = data;
val = mfspr(SPRN_TCR);
val &= ~WDTP_MASK;
val |= WDTP(sec_to_period(wdog->timeout));
mtspr(SPRN_TCR, val);
}
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static void booke_wdt_set(void *data)
{
on_each_cpu(__booke_wdt_set, data, 0);
}
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| Randy Vinson | 16 | 84.21% | 1 | 50.00% |
| Tang Yuantian | 3 | 15.79% | 1 | 50.00% |
| Total | 19 | 100.00% | 2 | 100.00% |
static void __booke_wdt_ping(void *data)
{
mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
}
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| Stefan Roese | 16 | 84.21% | 1 | 50.00% |
| Chen Gong | 3 | 15.79% | 1 | 50.00% |
| Total | 19 | 100.00% | 2 | 100.00% |
static int booke_wdt_ping(struct watchdog_device *wdog)
{
on_each_cpu(__booke_wdt_ping, NULL, 0);
return 0;
}
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| Chen Gong | 15 | 65.22% | 1 | 50.00% |
| Guenter Roeck | 8 | 34.78% | 1 | 50.00% |
| Total | 23 | 100.00% | 2 | 100.00% |
static void __booke_wdt_enable(void *data)
{
u32 val;
struct watchdog_device *wdog = data;
/* clear status before enabling watchdog */
__booke_wdt_ping(NULL);
val = mfspr(SPRN_TCR);
val &= ~WDTP_MASK;
val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(sec_to_period(wdog->timeout)));
mtspr(SPRN_TCR, val);
}
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| Kumar Gala | 39 | 59.09% | 1 | 20.00% |
| Tang Yuantian | 13 | 19.70% | 1 | 20.00% |
| Chen Gong | 7 | 10.61% | 1 | 20.00% |
| Matthias Fuchs | 5 | 7.58% | 1 | 20.00% |
| Stefan Roese | 2 | 3.03% | 1 | 20.00% |
| Total | 66 | 100.00% | 5 | 100.00% |
/**
* booke_wdt_disable - disable the watchdog on the given CPU
*
* This function is called on each CPU. It disables the watchdog on that CPU.
*
* TCR[WRC] cannot be changed once it has been set to non-zero, but we can
* effectively disable the watchdog by setting its period to the maximum value.
*/
static void __booke_wdt_disable(void *data)
{
u32 val;
val = mfspr(SPRN_TCR);
val &= ~(TCR_WIE | WDTP_MASK);
mtspr(SPRN_TCR, val);
/* clear status to make sure nothing is pending */
__booke_wdt_ping(NULL);
}
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static int booke_wdt_start(struct watchdog_device *wdog)
{
on_each_cpu(__booke_wdt_enable, wdog, 0);
pr_debug("watchdog enabled (timeout = %u sec)\n", wdog->timeout);
return 0;
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Kumar Gala | 16 | 50.00% | 1 | 20.00% |
| Guenter Roeck | 10 | 31.25% | 1 | 20.00% |
| Tang Yuantian | 3 | 9.38% | 1 | 20.00% |
| Chris Friesen | 2 | 6.25% | 1 | 20.00% |
| Wim Van Sebroeck | 1 | 3.12% | 1 | 20.00% |
| Total | 32 | 100.00% | 5 | 100.00% |
static int booke_wdt_stop(struct watchdog_device *wdog)
{
on_each_cpu(__booke_wdt_disable, NULL, 0);
pr_debug("watchdog disabled\n");
return 0;
}
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| Timur Tabi | 21 | 75.00% | 3 | 60.00% |
| Guenter Roeck | 6 | 21.43% | 1 | 20.00% |
| Joe Perches | 1 | 3.57% | 1 | 20.00% |
| Total | 28 | 100.00% | 5 | 100.00% |
static int booke_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
wdt_dev->timeout = timeout;
booke_wdt_set(wdt_dev);
return 0;
}
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| Guenter Roeck | 22 | 75.86% | 1 | 33.33% |
| Timur Tabi | 4 | 13.79% | 1 | 33.33% |
| Tang Yuantian | 3 | 10.34% | 1 | 33.33% |
| Total | 29 | 100.00% | 3 | 100.00% |
static struct watchdog_info booke_wdt_info __ro_after_init = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "PowerPC Book-E Watchdog",
};
static const struct watchdog_ops booke_wdt_ops = {
.owner = THIS_MODULE,
.start = booke_wdt_start,
.stop = booke_wdt_stop,
.ping = booke_wdt_ping,
.set_timeout = booke_wdt_set_timeout,
};
static struct watchdog_device booke_wdt_dev = {
.info = &booke_wdt_info,
.ops = &booke_wdt_ops,
.min_timeout = 1,
};
static void __exit booke_wdt_exit(void)
{
watchdog_unregister_device(&booke_wdt_dev);
}
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| Kumar Gala | 13 | 86.67% | 1 | 50.00% |
| Guenter Roeck | 2 | 13.33% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static int __init booke_wdt_init(void)
{
int ret = 0;
bool nowayout = WATCHDOG_NOWAYOUT;
pr_info("powerpc book-e watchdog driver loaded\n");
booke_wdt_info.firmware_version = cur_cpu_spec->pvr_value;
booke_wdt_set_timeout(&booke_wdt_dev,
period_to_sec(booke_wdt_period));
watchdog_set_nowayout(&booke_wdt_dev, nowayout);
booke_wdt_dev.max_timeout = MAX_WDT_TIMEOUT;
if (booke_wdt_enabled)
booke_wdt_start(&booke_wdt_dev);
ret = watchdog_register_device(&booke_wdt_dev);
return ret;
}
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| Kumar Gala | 35 | 44.87% | 2 | 22.22% |
| Guenter Roeck | 27 | 34.62% | 2 | 22.22% |
| Chen Gong | 10 | 12.82% | 1 | 11.11% |
| Al Viro | 2 | 2.56% | 1 | 11.11% |
| Tang Yuantian | 2 | 2.56% | 1 | 11.11% |
| Timur Tabi | 1 | 1.28% | 1 | 11.11% |
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| Total | 78 | 100.00% | 9 | 100.00% |
module_init(booke_wdt_init);
module_exit(booke_wdt_exit);
MODULE_ALIAS("booke_wdt");
MODULE_DESCRIPTION("PowerPC Book-E watchdog driver");
MODULE_LICENSE("GPL");
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| Kumar Gala | 169 | 23.06% | 2 | 8.70% |
| Guenter Roeck | 161 | 21.96% | 2 | 8.70% |
| Chris Friesen | 104 | 14.19% | 1 | 4.35% |
| Timur Tabi | 89 | 12.14% | 3 | 13.04% |
| Randy Vinson | 54 | 7.37% | 1 | 4.35% |
| Tang Yuantian | 50 | 6.82% | 1 | 4.35% |
| Chen Gong | 38 | 5.18% | 1 | 4.35% |
| Pranith Kumar | 20 | 2.73% | 1 | 4.35% |
| Stefan Roese | 18 | 2.46% | 1 | 4.35% |
| Matthias Fuchs | 12 | 1.64% | 1 | 4.35% |
| Joe Perches | 9 | 1.23% | 1 | 4.35% |
| Al Viro | 2 | 0.27% | 1 | 4.35% |
| Bhumika Goyal | 2 | 0.27% | 2 | 8.70% |
| Dave Jiang | 1 | 0.14% | 1 | 4.35% |
| Luuk Paulussen | 1 | 0.14% | 1 | 4.35% |
| Shaohui Xie | 1 | 0.14% | 1 | 4.35% |
| Alan Cox | 1 | 0.14% | 1 | 4.35% |
| Wim Van Sebroeck | 1 | 0.14% | 1 | 4.35% |
| Total | 733 | 100.00% | 23 | 100.00% |
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