Release 4.12 drivers/clocksource/exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>


#define EXYNOS4_MCTREG(x)		(x)

#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)

#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)

#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)

#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)

#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)

#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)

#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)

#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)

#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)

#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)

#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)

#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))

#define EXYNOS4_MCT_L_MASK		(0xffffff00)


#define MCT_L_TCNTB_OFFSET		(0x00)

#define MCT_L_ICNTB_OFFSET		(0x08)

#define MCT_L_TCON_OFFSET		(0x20)

#define MCT_L_INT_CSTAT_OFFSET		(0x30)

#define MCT_L_INT_ENB_OFFSET		(0x34)

#define MCT_L_WSTAT_OFFSET		(0x40)

#define MCT_G_TCON_START		(1 << 8)

#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)

#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)

#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)

#define MCT_L_TCON_INT_START		(1 << 1)

#define MCT_L_TCON_TIMER_START		(1 << 0)


#define TICK_BASE_CNT	1

enum {
	
MCT_INT_SPI,
	
MCT_INT_PPI
};

enum {
	
MCT_G0_IRQ,
	
MCT_G1_IRQ,
	
MCT_G2_IRQ,
	
MCT_G3_IRQ,
	
MCT_L0_IRQ,
	
MCT_L1_IRQ,
	
MCT_L2_IRQ,
	
MCT_L3_IRQ,
	
MCT_L4_IRQ,
	
MCT_L5_IRQ,
	
MCT_L6_IRQ,
	
MCT_L7_IRQ,
	
MCT_NR_IRQS,
};


static void __iomem *reg_base;

static unsigned long clk_rate;

static unsigned int mct_int_type;

static int mct_irqs[MCT_NR_IRQS];


struct mct_clock_event_device {
	
struct clock_event_device evt;
	
unsigned long base;
	
char name[10];
};



static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	writel_relaxed(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & ~EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (readl_relaxed(reg_base + stat_addr) & mask) {
			writel_relaxed(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

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/* Clocksource handling */


static void exynos4_mct_frc_start(void)
{
	u32 reg;

	reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

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/**
 * exynos4_read_count_64 - Read all 64-bits of the global counter
 *
 * This will read all 64-bits of the global counter taking care to make sure
 * that the upper and lower half match.  Note that reading the MCT can be quite
 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
 * only) version when possible.
 *
 * Returns the number of cycles in the global counter.
 */


static u64 exynos4_read_count_64(void)
{
	unsigned int lo, hi;
	u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((u64)hi << 32) | lo;
}

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/**
 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
 *
 * This will read just the lower 32-bits of the global counter.  This is marked
 * as notrace so it can be used by the scheduler clock.
 *
 * Returns the number of cycles in the global counter (lower 32 bits).
 */


static u32 notrace exynos4_read_count_32(void)
{
	return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
}

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static u64 exynos4_frc_read(struct clocksource *cs)
{
	return exynos4_read_count_32();
}

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static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start();
}

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static struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};



static u64 notrace exynos4_read_sched_clock(void)
{
	return exynos4_read_count_32();
}

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#if defined(CONFIG_ARM)

static struct delay_timer exynos4_delay_timer;



static cycles_t exynos4_read_current_timer(void)
{
	BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
			 "cycles_t needs to move to 32-bit for ARM64 usage");
	return exynos4_read_count_32();
}
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#endif



static int __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start();

#if defined(CONFIG_ARM)
	exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
	exynos4_delay_timer.freq = clk_rate;
	register_current_timer_delay(&exynos4_delay_timer);
#endif

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);

	sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);

	return 0;
}

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static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

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static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
{
	unsigned int tcon;
	u64 comp_cycle;

	tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);

	if (periodic) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_read_count_64() + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

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static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(false, cycles);

	return 0;
}

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static int mct_set_state_shutdown(struct clock_event_device *evt)
{
	exynos4_mct_comp0_stop();
	return 0;
}

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static int mct_set_state_periodic(struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;

	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
			    >> evt->shift);
	exynos4_mct_comp0_stop();
	exynos4_mct_comp0_start(true, cycles_per_jiffy);
	return 0;
}

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static struct clock_event_device mct_comp_device = {
	.name			= "mct-comp",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 250,
	.set_next_event		= exynos4_comp_set_next_event,
	.set_state_periodic	= mct_set_state_periodic,
	.set_state_shutdown	= mct_set_state_shutdown,
	.set_state_oneshot	= mct_set_state_shutdown,
	.set_state_oneshot_stopped = mct_set_state_shutdown,
	.tick_resume		= mct_set_state_shutdown,
};



static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

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static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};



static int exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);

	return 0;
}

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static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */


static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = readl_relaxed(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

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static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

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static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;

	mevt = container_of(evt, struct mct_clock_event_device, evt);
	exynos4_mct_tick_start(cycles, mevt);
	return 0;
}

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static int set_state_shutdown(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;

	mevt = container_of(evt, struct mct_clock_event_device, evt);
	exynos4_mct_tick_stop(mevt);
	return 0;
}

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static int set_state_periodic(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned long cycles_per_jiffy;

	mevt = container_of(evt, struct mct_clock_event_device, evt);
	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
			    >> evt->shift);
	exynos4_mct_tick_stop(mevt);
	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
	return 0;
}

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static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	/*
         * This is for supporting oneshot mode.
         * Mct would generate interrupt periodically
         * without explicit stopping.
         */
	if (!clockevent_state_periodic(&mevt->evt))
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
}

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55
100.00%
6
100.00%



static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Changhwan Youn
44
97.78%
2
66.67%
Stephen Boyd
1
2.22%
1
33.33%
Total
45
100.00%
3
100.00%



static int exynos4_mct_starting_cpu(unsigned int cpu)
{
	struct mct_clock_event_device *mevt =
		per_cpu_ptr(&percpu_mct_tick, cpu);
	struct clock_event_device *evt = &mevt->evt;

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_state_periodic = set_state_periodic;
	evt->set_state_shutdown = set_state_shutdown;
	evt->set_state_oneshot = set_state_shutdown;
	evt->set_state_oneshot_stopped = set_state_shutdown;
	evt->tick_resume = set_state_shutdown;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {

		if (evt->irq == -1)
			return -EIO;

		irq_force_affinity(evt->irq, cpumask_of(cpu));
		enable_irq(evt->irq);
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Changhwan Youn
82
38.86%
4
23.53%
Viresh Kumar
26
12.32%
2
11.76%
Krzysztof Kozlowski
17
8.06%
1
5.88%
Marc Zyngier
16
7.58%
2
11.76%
Richard Cochran
15
7.11%
1
5.88%
Damian Eppel
13
6.16%
1
5.88%
Thomas Gleixner
9
4.27%
1
5.88%
Alexey Klimov
8
3.79%
1
5.88%
Dan Carpenter
8
3.79%
1
5.88%
Thomas Abraham
7
3.32%
1
5.88%
Chander Kashyap
7
3.32%
1
5.88%
Kukjin Kim
3
1.42%
1
5.88%
Total
211
100.00%
17
100.00%



static int exynos4_mct_dying_cpu(unsigned int cpu)
{
	struct mct_clock_event_device *mevt =
		per_cpu_ptr(&percpu_mct_tick, cpu);
	struct clock_event_device *evt = &mevt->evt;

	evt->set_state_shutdown(evt);
	if (mct_int_type == MCT_INT_SPI) {
		if (evt->irq != -1)
			disable_irq_nosync(evt->irq);
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	} else {
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
	}
	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Marc Zyngier
22
24.72%
3
23.08%
Richard Cochran
17
19.10%
1
7.69%
Damian Eppel
13
14.61%
1
7.69%
Alexey Klimov
12
13.48%
1
7.69%
Joonyoung Shim
11
12.36%
1
7.69%
Changhwan Youn
5
5.62%
2
15.38%
Thomas Abraham
4
4.49%
1
7.69%
Stephen Boyd
3
3.37%
1
7.69%
Viresh Kumar
1
1.12%
1
7.69%
Amit Daniel Kachhap
1
1.12%
1
7.69%
Total
89
100.00%
13
100.00%



static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err, cpu;
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	} else {
		for_each_possible_cpu(cpu) {
			int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
			struct mct_clock_event_device *pcpu_mevt =
				per_cpu_ptr(&percpu_mct_tick, cpu);

			pcpu_mevt->evt.irq = -1;

			irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
			if (request_irq(mct_irq,
					exynos4_mct_tick_isr,
					IRQF_TIMER | IRQF_NOBALANCING,
					pcpu_mevt->name, pcpu_mevt)) {
				pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
									cpu);

				continue;
			}
			pcpu_mevt->evt.irq = mct_irq;
		}
	}

	/* Install hotplug callbacks which configure the timer on this CPU */
	err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
				"clockevents/exynos4/mct_timer:starting",
				exynos4_mct_starting_cpu,
				exynos4_mct_dying_cpu);
	if (err)
		goto out_irq;

	return 0;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
	return err;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Thomas Abraham
91
31.82%
5
31.25%
Damian Eppel
74
25.87%
1
6.25%
Marc Zyngier
36
12.59%
2
12.50%
Changhwan Youn
28
9.79%
1
6.25%
Stephen Boyd
24
8.39%
1
6.25%
Tomasz Figa
13
4.55%
1
6.25%
Richard Cochran
8
2.80%
1
6.25%
Daniel Lezcano
7
2.45%
1
6.25%
Arnd Bergmann
4
1.40%
2
12.50%
Thomas Gleixner
1
0.35%
1
6.25%
Total
286
100.00%
16
100.00%



static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;
	int ret;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
         * Find out the number of local irqs specified. The local
         * timer irqs are specified after the four global timer
         * irqs are specified.
         */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	ret = exynos4_timer_resources(np, of_iomap(np, 0));
	if (ret)
		return ret;

	ret = exynos4_clocksource_init();
	if (ret)
		return ret;

	return exynos4_clockevent_init();
}


Contributors
Person
Tokens
Prop
Commits
CommitProp
Thomas Abraham
58
47.54%
2
25.00%
Arnd Bergmann
27
22.13%
3
37.50%
Daniel Lezcano
24
19.67%
1
12.50%
Changhwan Youn
13
10.66%
2
25.00%
Total
122
100.00%
8
100.00%



static int __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Arnd Bergmann
19
95.00%
1
50.00%
Daniel Lezcano
1
5.00%
1
50.00%
Total
20
100.00%
2
100.00%



static int __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Arnd Bergmann
19
95.00%
1
50.00%
Daniel Lezcano
1
5.00%
1
50.00%
Total
20
100.00%
2
100.00%

CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Overall Contributors
Person
Tokens
Prop
Commits
CommitProp
Changhwan Youn
1210
50.97%
5
9.62%
Thomas Abraham
370
15.59%
6
11.54%
Viresh Kumar
114
4.80%
2
3.85%
Damian Eppel
100
4.21%
1
1.92%
Marc Zyngier
78
3.29%
3
5.77%
Arnd Bergmann
71
2.99%
3
5.77%
Douglas Anderson
70
2.95%
3
5.77%
Alexey Klimov
61
2.57%
2
3.85%
Daniel Lezcano
43
1.81%
2
3.85%
Richard Cochran
40
1.68%
1
1.92%
Amit Daniel Kachhap
36
1.52%
2
3.85%
Stephen Boyd
31
1.31%
1
1.92%
Vincent Guittot
22
0.93%
1
1.92%
Krzysztof Kozlowski
19
0.80%
3
5.77%
Kukjin Kim
17
0.72%
3
5.77%
Chanwoo Choi
16
0.67%
1
1.92%
Chander Kashyap
15
0.63%
2
3.85%
Thomas Gleixner
13
0.55%
3
5.77%
Tomasz Figa
13
0.55%
1
1.92%
Joonyoung Shim
11
0.46%
1
1.92%
Dan Carpenter
8
0.34%
1
1.92%
Shawn Guo
7
0.29%
1
1.92%
Doug Anderson
4
0.17%
1
1.92%
Chirantan Ekbote
3
0.13%
1
1.92%
Lucas De Marchi
1
0.04%
1
1.92%
Tobias Jakobi
1
0.04%
1
1.92%
Total
2374
100.00%
52
100.00%
Directory: drivers/clocksource

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