Release 4.12 drivers/clocksource/qcom-timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/delay.h>


#define TIMER_MATCH_VAL			0x0000

#define TIMER_COUNT_VAL			0x0004

#define TIMER_ENABLE			0x0008

#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)

#define TIMER_ENABLE_EN			BIT(0)

#define TIMER_CLEAR			0x000C

#define DGT_CLK_CTL			0x10

#define DGT_CLK_CTL_DIV_4		0x3

#define TIMER_STS_GPT0_CLR_PEND		BIT(10)


#define GPT_HZ 32768


static void __iomem *event_base;

static void __iomem *sts_base;



static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	/* Stop the timer tick */
	if (clockevent_state_oneshot(evt)) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
31
48.44%
2
50.00%
Arve Hjönnevåg
30
46.88%
1
25.00%
Viresh Kumar
3
4.69%
1
25.00%
Total
64
100.00%
4
100.00%



static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
61
70.11%
4
80.00%
Arve Hjönnevåg
26
29.89%
1
20.00%
Total
87
100.00%
5
100.00%



static int msm_timer_shutdown(struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
24
54.55%
2
50.00%
Arve Hjönnevåg
15
34.09%
1
25.00%
Viresh Kumar
5
11.36%
1
25.00%
Total
44
100.00%
4
100.00%


static struct clock_event_device __percpu *msm_evt;


static void __iomem *source_base;



static notrace u64 msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
18
90.00%
3
60.00%
Thomas Gleixner
1
5.00%
1
20.00%
Arve Hjönnevåg
1
5.00%
1
20.00%
Total
20
100.00%
5
100.00%


static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};


static int msm_timer_irq;

static int msm_timer_has_ppi;



static int msm_local_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
	int err;

	evt->irq = msm_timer_irq;
	evt->name = "msm_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 200;
	evt->set_state_shutdown = msm_timer_shutdown;
	evt->set_state_oneshot = msm_timer_shutdown;
	evt->tick_resume = msm_timer_shutdown;
	evt->set_next_event = msm_timer_set_next_event;
	evt->cpumask = cpumask_of(cpu);

	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);

	if (msm_timer_has_ppi) {
		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	} else {
		err = request_irq(evt->irq, msm_timer_interrupt,
				IRQF_TIMER | IRQF_NOBALANCING |
				IRQF_TRIGGER_RISING, "gp_timer", evt);
		if (err)
			pr_err("request_irq failed\n");
	}

	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
56
38.89%
2
33.33%
Marc Zyngier
56
38.89%
1
16.67%
Viresh Kumar
14
9.72%
1
16.67%
Richard Cochran
12
8.33%
1
16.67%
Shawn Guo
6
4.17%
1
16.67%
Total
144
100.00%
6
100.00%



static int msm_local_timer_dying_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);

	evt->set_state_shutdown(evt);
	disable_percpu_irq(evt->irq);
	return 0;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Marc Zyngier
19
48.72%
1
25.00%
Richard Cochran
16
41.03%
1
25.00%
Stephen Boyd
3
7.69%
1
25.00%
Viresh Kumar
1
2.56%
1
25.00%
Total
39
100.00%
4
100.00%



static u64 notrace msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
18
100.00%
2
100.00%
Total
18
100.00%
2
100.00%



static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
18
100.00%
1
100.00%
Total
18
100.00%
1
100.00%


static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};



static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clocksource *cs = &msm_clocksource;
	int res = 0;

	msm_timer_irq = irq;
	msm_timer_has_ppi = percpu;

	msm_evt = alloc_percpu(struct clock_event_device);
	if (!msm_evt) {
		pr_err("memory allocation failed for clockevents\n");
		goto err;
	}

	if (percpu)
		res = request_percpu_irq(irq, msm_timer_interrupt,
					 "gp_timer", msm_evt);

	if (res) {
		pr_err("request_percpu_irq failed\n");
	} else {
		/* Install and invoke hotplug callbacks */
		res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
					"clockevents/qcom/timer:starting",
					msm_local_timer_starting_cpu,
					msm_local_timer_dying_cpu);
		if (res) {
			free_percpu_irq(irq, msm_evt);
			goto err;
		}
	}

err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);

	return res;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
99
55.93%
8
57.14%
Marc Zyngier
41
23.16%
2
14.29%
Arve Hjönnevåg
24
13.56%
1
7.14%
Richard Cochran
8
4.52%
1
7.14%
Daniel Lezcano
4
2.26%
1
7.14%
Thomas Gleixner
1
0.56%
1
7.14%
Total
177
100.00%
14
100.00%



static int __init msm_dt_timer_init(struct device_node *np)
{
	u32 freq;
	int irq, ret;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return -ENXIO;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return -EINVAL;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
		pr_err("Failed to parse DGT resource\n");
		return ret;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return -EINVAL;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return -EINVAL;
	}

	event_base = base + 0x4;
	sts_base = base + 0x88;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	return msm_timer_init(freq, 32, irq, !!percpu_offset);
}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
203
87.12%
4
80.00%
Daniel Lezcano
30
12.88%
1
20.00%
Total
233
100.00%
5
100.00%

CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
Overall Contributors
Person
Tokens
Prop
Commits
CommitProp
Stephen Boyd
622
61.04%
18
60.00%
Arve Hjönnevåg
172
16.88%
1
3.33%
Marc Zyngier
116
11.38%
2
6.67%
Daniel Lezcano
36
3.53%
2
6.67%
Richard Cochran
36
3.53%
1
3.33%
Viresh Kumar
23
2.26%
1
3.33%
Shawn Guo
6
0.59%
1
3.33%
Jeffrey Ohlstein
5
0.49%
1
3.33%
Thomas Gleixner
2
0.20%
2
6.67%
Kumar Gala
1
0.10%
1
3.33%
Total
1019
100.00%
30
100.00%
Directory: drivers/clocksource

Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.