/* * Copyright (c) 2013, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H #define _DT_BINDINGS_RESET_MSM_GCC_8660_H #define AFAB_CORE_RESET 0 #define SCSS_SYS_RESET 1 #define SCSS_SYS_POR_RESET 2 #define AFAB_SMPSS_S_RESET 3 #define AFAB_SMPSS_M1_RESET 4 #define AFAB_SMPSS_M0_RESET 5 #define AFAB_EBI1_S_RESET 6 #define SFAB_CORE_RESET 7 #define SFAB_ADM0_M0_RESET 8 #define SFAB_ADM0_M1_RESET 9 #define SFAB_ADM0_M2_RESET 10 #define ADM0_C2_RESET 11 #define ADM0_C1_RESET 12 #define ADM0_C0_RESET 13 #define ADM0_PBUS_RESET 14 #define ADM0_RESET 15 #define SFAB_ADM1_M0_RESET 16 #define SFAB_ADM1_M1_RESET 17 #define SFAB_ADM1_M2_RESET 18 #define MMFAB_ADM1_M3_RESET 19 #define ADM1_C3_RESET 20 #define ADM1_C2_RESET 21 #define ADM1_C1_RESET 22 #define ADM1_C0_RESET 23 #define ADM1_PBUS_RESET 24 #define ADM1_RESET 25 #define IMEM0_RESET 26 #define SFAB_LPASS_Q6_RESET 27 #define SFAB_AFAB_M_RESET 28 #define AFAB_SFAB_M0_RESET 29 #define AFAB_SFAB_M1_RESET 30 #define DFAB_CORE_RESET 31 #define SFAB_DFAB_M_RESET 32 #define DFAB_SFAB_M_RESET 33 #define DFAB_SWAY0_RESET 34 #define DFAB_SWAY1_RESET 35 #define DFAB_ARB0_RESET 36 #define DFAB_ARB1_RESET 37 #define PPSS_PROC_RESET 38 #define PPSS_RESET 39 #define PMEM_RESET 40 #define DMA_BAM_RESET 41 #define SIC_RESET 42 #define SPS_TIC_RESET 43 #define CFBP0_RESET 44 #define CFBP1_RESET 45 #define CFBP2_RESET 46 #define EBI2_RESET 47 #define SFAB_CFPB_M_RESET 48 #define CFPB_MASTER_RESET 49 #define SFAB_CFPB_S_RESET 50 #define CFPB_SPLITTER_RESET 51 #define TSIF_RESET 52 #define CE1_RESET 53 #define CE2_RESET 54 #define SFAB_SFPB_M_RESET 55 #define SFAB_SFPB_S_RESET 56 #define RPM_PROC_RESET 57 #define RPM_BUS_RESET 58 #define RPM_MSG_RAM_RESET 59 #define PMIC_ARB0_RESET 60 #define PMIC_ARB1_RESET 61 #define PMIC_SSBI2_RESET 62 #define SDC1_RESET 63 #define SDC2_RESET 64 #define SDC3_RESET 65 #define SDC4_RESET 66 #define SDC5_RESET 67 #define USB_HS1_RESET 68 #define USB_HS2_XCVR_RESET 69 #define USB_HS2_RESET 70 #define USB_FS1_XCVR_RESET 71 #define USB_FS1_RESET 72 #define USB_FS2_XCVR_RESET 73 #define USB_FS2_RESET 74 #define GSBI1_RESET 75 #define GSBI2_RESET 76 #define GSBI3_RESET 77 #define GSBI4_RESET 78 #define GSBI5_RESET 79 #define GSBI6_RESET 80 #define GSBI7_RESET 81 #define GSBI8_RESET 82 #define GSBI9_RESET 83 #define GSBI10_RESET 84 #define GSBI11_RESET 85 #define GSBI12_RESET 86 #define SPDM_RESET 87 #define SEC_CTRL_RESET 88 #define TLMM_H_RESET 89 #define TLMM_RESET 90 #define MARRM_PWRON_RESET 91 #define MARM_RESET 92 #define MAHB1_RESET 93 #define SFAB_MSS_S_RESET 94 #define MAHB2_RESET 95 #define MODEM_SW_AHB_RESET 96 #define MODEM_RESET 97 #define SFAB_MSS_MDM1_RESET 98 #define SFAB_MSS_MDM0_RESET 99 #define MSS_SLP_RESET 100 #define MSS_MARM_SAW_RESET 101 #define MSS_WDOG_RESET 102 #define TSSC_RESET 103 #define PDM_RESET 104 #define SCSS_CORE0_RESET 105 #define SCSS_CORE0_POR_RESET 106 #define SCSS_CORE1_RESET 107 #define SCSS_CORE1_POR_RESET 108 #define MPM_RESET 109 #define EBI1_1X_DIV_RESET 110 #define EBI1_RESET 111 #define SFAB_SMPSS_S_RESET 112 #define USB_PHY0_RESET 113 #define USB_PHY1_RESET 114 #define PRNG_RESET 115 #endifOverall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Stephen Boyd | 473 | 100.00% | 1 | 100.00% |
| Total | 473 | 100.00% | 1 | 100.00% |