Release 4.12 include/uapi/linux/pci_regs.h
/*
* pci_regs.h
*
* PCI standard defines
* Copyright 1994, Drew Eckhardt
* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
*
* For more information, please consult the following manuals (look at
* http://www.pcisig.com/ for how to get them):
*
* PCI BIOS Specification
* PCI Local Bus Specification
* PCI to PCI Bridge Specification
* PCI System Design Guide
*
* For HyperTransport information, please consult the following manuals
* from http://www.hypertransport.org
*
* The HyperTransport I/O Link Specification
*/
#ifndef LINUX_PCI_REGS_H
#define LINUX_PCI_REGS_H
/*
* Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
* configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
* configuration space.
*/
#define PCI_CFG_SPACE_SIZE 256
#define PCI_CFG_SPACE_EXP_SIZE 4096
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_STD_HEADER_SIZEOF 64
#define PCI_VENDOR_ID 0x00
/* 16 bits */
#define PCI_DEVICE_ID 0x02
/* 16 bits */
#define PCI_COMMAND 0x04
/* 16 bits */
#define PCI_COMMAND_IO 0x1
/* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2
/* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4
/* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8
/* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10
/* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20
/* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40
/* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80
/* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100
/* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200
/* Enable back-to-back writes */
#define PCI_COMMAND_INTX_DISABLE 0x400
/* INTx Emulation Disable */
#define PCI_STATUS 0x06
/* 16 bits */
#define PCI_STATUS_INTERRUPT 0x08
/* Interrupt status */
#define PCI_STATUS_CAP_LIST 0x10
/* Support Capability List */
#define PCI_STATUS_66MHZ 0x20
/* Support 66 MHz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40
/* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80
/* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100
/* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600
/* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800
/* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000
/* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000
/* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
/* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000
/* Set on parity error */
#define PCI_CLASS_REVISION 0x08
/* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID 0x08
/* Revision ID */
#define PCI_CLASS_PROG 0x09
/* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a
/* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c
/* 8 bits */
#define PCI_LATENCY_TIMER 0x0d
/* 8 bits */
#define PCI_HEADER_TYPE 0x0e
/* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f
/* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f
/* Return result */
#define PCI_BIST_START 0x40
/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80
/* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10
/* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14
/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18
/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c
/* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20
/* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24
/* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01
/* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
/* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
/* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
/* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
/* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30
/* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffU)
#define PCI_CAPABILITY_LIST 0x34
/* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c
/* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d
/* 8 bits */
#define PCI_MIN_GNT 0x3e
/* 8 bits */
#define PCI_MAX_LAT 0x3f
/* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18
/* Primary bus number */
#define PCI_SECONDARY_BUS 0x19
/* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a
/* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b
/* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c
/* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL
/* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK (~0x0fUL)
/* Standard 4K I/O windows */
#define PCI_IO_1K_RANGE_MASK (~0x03UL)
/* Intel 1K I/O windows */
#define PCI_SEC_STATUS 0x1e
/* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20
/* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
#define PCI_PREF_MEMORY_BASE 0x24
/* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK (~0x0fUL)
#define PCI_PREF_BASE_UPPER32 0x28
/* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30
/* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38
/* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01
/* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02
/* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_ISA 0x04
/* Enable ISA mode */
#define PCI_BRIDGE_CTL_VGA 0x08
/* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
/* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40
/* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80
/* Fast Back2Back enabled on secondary interface */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16
/* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18
/* PCI bus number */
#define PCI_CB_CARD_BUS 0x19
/* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a
/* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b
/* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK (~0x03UL)
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01
/* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
/* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
/* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
/* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44
/* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0
/* Capability ID */
#define PCI_CAP_ID_PM 0x01
/* Power Management */
#define PCI_CAP_ID_AGP 0x02
/* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03
/* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04
/* Slot Identification */
#define PCI_CAP_ID_MSI 0x05
/* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06
/* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07
/* PCI-X */
#define PCI_CAP_ID_HT 0x08
/* HyperTransport */
#define PCI_CAP_ID_VNDR 0x09
/* Vendor-Specific */
#define PCI_CAP_ID_DBG 0x0A
/* Debug port */
#define PCI_CAP_ID_CCRC 0x0B
/* CompactPCI Central Resource Control */
#define PCI_CAP_ID_SHPC 0x0C
/* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_SSVID 0x0D
/* Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_AGP3 0x0E
/* AGP Target PCI-PCI bridge */
#define PCI_CAP_ID_SECDEV 0x0F
/* Secure Device */
#define PCI_CAP_ID_EXP 0x10
/* PCI Express */
#define PCI_CAP_ID_MSIX 0x11
/* MSI-X */
#define PCI_CAP_ID_SATA 0x12
/* SATA Data/Index Conf. */
#define PCI_CAP_ID_AF 0x13
/* PCI Advanced Features */
#define PCI_CAP_ID_EA 0x14
/* PCI Enhanced Allocation */
#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
#define PCI_CAP_LIST_NEXT 1
/* Next capability in the list */
#define PCI_CAP_FLAGS 2
/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_PMC 2
/* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007
/* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008
/* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010
/* Reserved field */
#define PCI_PM_CAP_DSI 0x0020
/* Device specific initialization */
#define PCI_PM_CAP_AUX_POWER 0x01C0
/* Auxiliary power support mask */
#define PCI_PM_CAP_D1 0x0200
/* D1 power state support */
#define PCI_PM_CAP_D2 0x0400
/* D2 power state support */
#define PCI_PM_CAP_PME 0x0800
/* PME pin supported */
#define PCI_PM_CAP_PME_MASK 0xF800
/* PME Mask of all supported states */
#define PCI_PM_CAP_PME_D0 0x0800
/* PME# from D0 */
#define PCI_PM_CAP_PME_D1 0x1000
/* PME# from D1 */
#define PCI_PM_CAP_PME_D2 0x2000
/* PME# from D2 */
#define PCI_PM_CAP_PME_D3 0x4000
/* PME# from D3 (hot) */
#define PCI_PM_CAP_PME_D3cold 0x8000
/* PME# from D3 (cold) */
#define PCI_PM_CAP_PME_SHIFT 11
/* Start of the PME Mask in PMC */
#define PCI_PM_CTRL 4
/* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003
/* Current power state (D0 to D3) */
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008
/* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100
/* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
/* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
/* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000
/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6
/* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40
/* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80
/* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7
/* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2
/* BCD version number */
#define PCI_AGP_RFU 3
/* Rest of capability flags */
#define PCI_AGP_STATUS 4
/* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000
/* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200
/* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020
/* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010
/* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004
/* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002
/* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001
/* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8
/* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
/* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200
/* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100
/* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020
/* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010
/* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004
/* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002
/* Use 2x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001
/* Use 1x rate */
#define PCI_AGP_SIZEOF 12
/* Vital Product Data */
#define PCI_VPD_ADDR 2
/* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK 0x7fff
/* Address mask */
#define PCI_VPD_ADDR_F 0x8000
/* Write 0, 1 indicates completion */
#define PCI_VPD_DATA 4
/* 32-bits of data returned here */
#define PCI_CAP_VPD_SIZEOF 8
/* Slot Identification */
#define PCI_SID_ESR 2
/* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f
/* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20
/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3
/* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2
/* Message Control */
#define PCI_MSI_FLAGS_ENABLE 0x0001
/* MSI feature enabled */
#define PCI_MSI_FLAGS_QMASK 0x000e
/* Maximum queue size available */
#define PCI_MSI_FLAGS_QSIZE 0x0070
/* Message queue size configured */
#define PCI_MSI_FLAGS_64BIT 0x0080
/* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_MASKBIT 0x0100
/* Per-vector masking capable */
#define PCI_MSI_RFU 3
/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4
/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8
/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8
/* 16 bits of data for 32-bit devices */
#define PCI_MSI_MASK_32 12
/* Mask bits register for 32-bit devices */
#define PCI_MSI_PENDING_32 16
/* Pending intrs for 32-bit devices */
#define PCI_MSI_DATA_64 12
/* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_64 16
/* Mask bits register for 64-bit devices */
#define PCI_MSI_PENDING_64 20
/* Pending intrs for 64-bit devices */
/* MSI-X registers */
#define PCI_MSIX_FLAGS 2
/* Message Control */
#define PCI_MSIX_FLAGS_QSIZE 0x07FF
/* Table size */
#define PCI_MSIX_FLAGS_MASKALL 0x4000
/* Mask all vectors for this function */
#define PCI_MSIX_FLAGS_ENABLE 0x8000
/* MSI-X enable */
#define PCI_MSIX_TABLE 4
/* Table offset */
#define PCI_MSIX_TABLE_BIR 0x00000007
/* BAR index */
#define PCI_MSIX_TABLE_OFFSET 0xfffffff8
/* Offset into specified BAR */
#define PCI_MSIX_PBA 8
/* Pending Bit Array offset */
#define PCI_MSIX_PBA_BIR 0x00000007
/* BAR index */
#define PCI_MSIX_PBA_OFFSET 0xfffffff8
/* Offset into specified BAR */
#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR
/* deprecated */
#define PCI_CAP_MSIX_SIZEOF 12
/* size of MSIX registers */
/* MSI-X Table entry format */
#define PCI_MSIX_ENTRY_SIZE 16
#define PCI_MSIX_ENTRY_LOWER_ADDR 0
#define PCI_MSIX_ENTRY_UPPER_ADDR 4
#define PCI_MSIX_ENTRY_DATA 8
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2
/* Control and Status Register */
#define PCI_CHSWP_DHA 0x01
/* Device Hiding Arm */
#define PCI_CHSWP_EIM 0x02
/* ENUM# Signal Mask */
#define PCI_CHSWP_PIE 0x04
/* Pending Insert or Extract */
#define PCI_CHSWP_LOO 0x08
/* LED On / Off */
#define PCI_CHSWP_PI 0x30
/* Programming Interface */
#define PCI_CHSWP_EXT 0x40
/* ENUM# status - extraction */
#define PCI_CHSWP_INS 0x80
/* ENUM# status - insertion */
/* PCI Advanced Feature registers */
#define PCI_AF_LENGTH 2
#define PCI_AF_CAP 3
#define PCI_AF_CAP_TP 0x01
#define PCI_AF_CAP_FLR 0x02
#define PCI_AF_CTRL 4
#define PCI_AF_CTRL_FLR 0x01
#define PCI_AF_STATUS 5
#define PCI_AF_STATUS_TP 0x01
#define PCI_CAP_AF_SIZEOF 6
/* size of AF registers */
/* PCI Enhanced Allocation registers */
#define PCI_EA_NUM_ENT 2
/* Number of Capability Entries */
#define PCI_EA_NUM_ENT_MASK 0x3f
/* Num Entries Mask */
#define PCI_EA_FIRST_ENT 4
/* First EA Entry in List */
#define PCI_EA_FIRST_ENT_BRIDGE 8
/* First EA Entry for Bridges */
#define PCI_EA_ES 0x00000007
/* Entry Size */
#define PCI_EA_BEI 0x000000f0
/* BAR Equivalent Indicator */
/* 0-5 map to BARs 0-5 respectively */
#define PCI_EA_BEI_BAR0 0
#define PCI_EA_BEI_BAR5 5
#define PCI_EA_BEI_BRIDGE 6
/* Resource behind bridge */
#define PCI_EA_BEI_ENI 7
/* Equivalent Not Indicated */
#define PCI_EA_BEI_ROM 8
/* Expansion ROM */
/* 9-14 map to VF BARs 0-5 respectively */
#define PCI_EA_BEI_VF_BAR0 9
#define PCI_EA_BEI_VF_BAR5 14
#define PCI_EA_BEI_RESERVED 15
/* Reserved - Treat like ENI */
#define PCI_EA_PP 0x0000ff00
/* Primary Properties */
#define PCI_EA_SP 0x00ff0000
/* Secondary Properties */
#define PCI_EA_P_MEM 0x00
/* Non-Prefetch Memory */
#define PCI_EA_P_MEM_PREFETCH 0x01
/* Prefetchable Memory */
#define PCI_EA_P_IO 0x02
/* I/O Space */
#define PCI_EA_P_VF_MEM_PREFETCH 0x03
/* VF Prefetchable Memory */
#define PCI_EA_P_VF_MEM 0x04
/* VF Non-Prefetch Memory */
#define PCI_EA_P_BRIDGE_MEM 0x05
/* Bridge Non-Prefetch Memory */
#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06
/* Bridge Prefetchable Memory */
#define PCI_EA_P_BRIDGE_IO 0x07
/* Bridge I/O Space */
/* 0x08-0xfc reserved */
#define PCI_EA_P_MEM_RESERVED 0xfd
/* Reserved Memory */
#define PCI_EA_P_IO_RESERVED 0xfe
/* Reserved I/O Space */
#define PCI_EA_P_UNAVAILABLE 0xff
/* Entry Unavailable */
#define PCI_EA_WRITABLE 0x40000000
/* Writable: 1 = RW, 0 = HwInit */
#define PCI_EA_ENABLE 0x80000000
/* Enable for this entry */
#define PCI_EA_BASE 4
/* Base Address Offset */
#define PCI_EA_MAX_OFFSET 8
/* MaxOffset (resource length) */
/* bit 0 is reserved */
#define PCI_EA_IS_64 0x00000002
/* 64-bit field flag */
#define PCI_EA_FIELD_MASK 0xfffffffc
/* For Base & Max Offset */
/* PCI-X registers (Type 0 (non-bridge) devices) */
#define PCI_X_CMD 2
/* Modes & Features */
#define PCI_X_CMD_DPERR_E 0x0001
/* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002
/* Enable Relaxed Ordering */
#define PCI_X_CMD_READ_512 0x0000
/* 512 byte maximum read byte count */
#define PCI_X_CMD_READ_1K 0x0004
/* 1Kbyte maximum read byte count */
#define PCI_X_CMD_READ_2K 0x0008
/* 2Kbyte maximum read byte count */
#define PCI_X_CMD_READ_4K 0x000c
/* 4Kbyte maximum read byte count */
#define PCI_X_CMD_MAX_READ 0x000c
/* Max Memory Read Byte Count */
/* Max # of outstanding split transactions */
#define PCI_X_CMD_SPLIT_1 0x0000
/* Max 1 */
#define PCI_X_CMD_SPLIT_2 0x0010
/* Max 2 */
#define PCI_X_CMD_SPLIT_3 0x0020
/* Max 3 */
#define PCI_X_CMD_SPLIT_4 0x0030
/* Max 4 */
#define PCI_X_CMD_SPLIT_8 0x0040
/* Max 8 */
#define PCI_X_CMD_SPLIT_12 0x0050
/* Max 12 */
#define PCI_X_CMD_SPLIT_16 0x0060
/* Max 16 */
#define PCI_X_CMD_SPLIT_32 0x0070
/* Max 32 */
#define PCI_X_CMD_MAX_SPLIT 0x0070
/* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
/* Version */
#define PCI_X_STATUS 4
/* PCI-X capabilities */
#define PCI_X_STATUS_DEVFN 0x000000ff
/* A copy of devfn */
#define PCI_X_STATUS_BUS 0x0000ff00
/* A copy of bus nr */
#define PCI_X_STATUS_64BIT 0x00010000
/* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x00020000
/* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x00040000
/* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x00080000
/* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x00100000
/* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x00600000
/* Designed Max Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x03800000
/* Designed Max Outstanding Split Transactions */
#define PCI_X_STATUS_MAX_CUM 0x1c000000
/* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x20000000
/* Rcvd Split Completion Error Msg */
#define PCI_X_STATUS_266MHZ 0x40000000
/* 266 MHz capable */
#define PCI_X_STATUS_533MHZ 0x80000000
/* 533 MHz capable */
#define PCI_X_ECC_CSR 8
/* ECC control and status */
#define PCI_CAP_PCIX_SIZEOF_V0 8
/* size of registers for Version 0 */
#define PCI_CAP_PCIX_SIZEOF_V1 24
/* size for Version 1 */
#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1
/* Same for v2 */
/* PCI-X registers (Type 1 (bridge) devices) */
#define PCI_X_BRIDGE_SSTATUS 2
/* Secondary Status */
#define PCI_X_SSTATUS_64BIT 0x0001
/* Secondary AD interface is 64 bits */
#define PCI_X_SSTATUS_133MHZ 0x0002
/* 133 MHz capable */
#define PCI_X_SSTATUS_FREQ 0x03c0
/* Secondary Bus Mode and Frequency */
#define PCI_X_SSTATUS_VERS 0x3000
/* PCI-X Capability Version */
#define PCI_X_SSTATUS_V1 0x1000
/* Mode 2, not Mode 1 */
#define PCI_X_SSTATUS_V2 0x2000
/* Mode 1 or Modes 1 and 2 */
#define PCI_X_SSTATUS_266MHZ 0x4000
/* 266 MHz capable */
#define PCI_X_SSTATUS_533MHZ 0x8000
/* 533 MHz capable */
#define PCI_X_BRIDGE_STATUS 4
/* Bridge Status */
/* PCI Bridge Subsystem ID registers */
#define PCI_SSVID_VENDOR_ID 4
/* PCI Bridge subsystem vendor ID */
#define PCI_SSVID_DEVICE_ID 6
/* PCI Bridge subsystem device ID */
/* PCI Express capability registers */
#define PCI_EXP_FLAGS 2
/* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f
/* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0
/* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0
/* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1
/* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4
/* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5
/* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6
/* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7
/* PCIe to PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
/* PCI/PCI-X to PCIe Bridge */
#define PCI_EXP_TYPE_RC_END 0x9
/* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_RC_EC 0xa
/* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100
/* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00
/* Interrupt message number */
#define PCI_EXP_DEVCAP 4
/* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007
/* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x00000018
/* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020
/* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x000001c0
/* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0x00000e00
/* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000
/* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x00002000
/* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x00004000
/* Power Indicator Present */
#define PCI_EXP_DEVCAP_RBER 0x00008000
/* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000
/* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000
/* Slot Power Limit Scale */
#define PCI_EXP_DEVCAP_FLR 0x10000000
/* Function Level Reset */
#define PCI_EXP_DEVCTL 8
/* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001
/* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002
/* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE 0x0004
/* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE 0x0008
/* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010
/* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
/* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100
/* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200
/* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400
/* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
/* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000
/* Max_Read_Request_Size */
#define PCI_EXP_DEVCTL_READRQ_128B 0x0000
/* 128 Bytes */
#define PCI_EXP_DEVCTL_READRQ_256B 0x1000
/* 256 Bytes */
#define PCI_EXP_DEVCTL_READRQ_512B 0x2000
/* 512 Bytes */
#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000
/* 1024 Bytes */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
/* Bridge Configuration Retry / FLR */
#define PCI_EXP_DEVSTA 10
/* Device Status */
#define PCI_EXP_DEVSTA_CED 0x0001
/* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x0002
/* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED 0x0004
/* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD 0x0008
/* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x0010
/* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x0020
/* Transactions Pending */
#define PCI_EXP_LNKCAP 12
/* Link Capabilities */
#define PCI_EXP_LNKCAP_SLS 0x0000000f
/* Supported Link Speeds */
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
/* LNKCAP2 SLS Vector bit 0 */