Release 4.13 arch/arm/mach-omap2/io.c
/*
* linux/arch/arm/mach-omap2/io.c
*
* OMAP2 I/O mapping code
*
* Copyright (C) 2005 Nokia Corporation
* Copyright (C) 2007-2009 Texas Instruments
*
* Author:
* Juha Yrjola <juha.yrjola@nokia.com>
* Syed Khasim <x0khasim@ti.com>
*
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/tlb.h>
#include <asm/mach/map.h>
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "soc.h"
#include "iomap.h"
#include "voltage.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "common.h"
#include "clock.h"
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "omap-pm.h"
#include "sdrc.h"
#include "control.h"
#include "serial.h"
#include "sram.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
#include "prm.h"
#include "cm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
#include "opp2xxx.h"
/*
* omap_clk_soc_init: points to a function that does the SoC-specific
* clock initializations
*/
static int (*omap_clk_soc_init)(void);
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
.pfn = __phys_to_pfn(L3_24XX_PHYS),
.length = L3_24XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_24XX_VIRT,
.pfn = __phys_to_pfn(L4_24XX_PHYS),
.length = L4_24XX_SIZE,
.type = MT_DEVICE
},
};
#ifdef CONFIG_SOC_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
{
.virtual = DSP_MEM_2420_VIRT,
.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
.length = DSP_MEM_2420_SIZE,
.type = MT_DEVICE
},
{
.virtual = DSP_IPI_2420_VIRT,
.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
.length = DSP_IPI_2420_SIZE,
.type = MT_DEVICE
},
{
.virtual = DSP_MMU_2420_VIRT,
.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
.length = DSP_MMU_2420_SIZE,
.type = MT_DEVICE
},
};
#endif
#ifdef CONFIG_SOC_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
{
.virtual = L4_WK_243X_VIRT,
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
.length = L4_WK_243X_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
.length = OMAP243X_GPMC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_SDRC_VIRT,
.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
.length = OMAP243X_SDRC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_SMS_VIRT,
.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
.length = OMAP243X_SMS_SIZE,
.type = MT_DEVICE
},
};
#endif
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
{
.virtual = L3_34XX_VIRT,
.pfn = __phys_to_pfn(L3_34XX_PHYS),
.length = L3_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP34XX_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
.length = OMAP34XX_GPMC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP343X_SMS_VIRT,
.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
.length = OMAP343X_SMS_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP343X_SDRC_VIRT,
.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
.length = OMAP343X_SDRC_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_PER_34XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
.length = L4_PER_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_EMU_34XX_VIRT,
.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
.length = L4_EMU_34XX_SIZE,
.type = MT_DEVICE
},
};
#endif
#ifdef CONFIG_SOC_TI81XX
static struct map_desc omapti81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
}
};
#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static struct map_desc omapam33xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_WK_AM33XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
.length = L4_WK_AM33XX_SIZE,
.type = MT_DEVICE
}
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
.virtual = L3_44XX_VIRT,
.pfn = __phys_to_pfn(L3_44XX_PHYS),
.length = L3_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_44XX_VIRT,
.pfn = __phys_to_pfn(L4_44XX_PHYS),
.length = L4_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_44XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
.length = L4_PER_44XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
#ifdef CONFIG_SOC_OMAP5
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
.pfn = __phys_to_pfn(L3_54XX_PHYS),
.length = L3_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_54XX_VIRT,
.pfn = __phys_to_pfn(L4_54XX_PHYS),
.length = L4_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WK_54XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
.length = L4_WK_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_54XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
.length = L4_PER_54XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
#ifdef CONFIG_SOC_DRA7XX
static struct map_desc dra7xx_io_desc[] __initdata = {
{
.virtual = L4_CFG_MPU_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
.length = L4_CFG_MPU_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L3_MAIN_SN_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
.length = L3_MAIN_SN_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER1_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
.length = L4_PER1_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER2_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
.length = L4_PER2_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER3_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
.length = L4_PER3_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_CFG_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
.length = L4_CFG_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WKUP_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
.length = L4_WKUP_DRA7XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
}
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Total | 28 | 100.00% | 4 | 100.00% |
#endif
#ifdef CONFIG_SOC_OMAP2430
void __init omap243x_map_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
}
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Paul Walmsley | 1 | 3.57% | 1 | 20.00% |
Total | 28 | 100.00% | 5 | 100.00% |
#endif
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_map_io(void)
{
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
}
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Paul Walmsley | 1 | 5.56% | 1 | 20.00% |
Total | 18 | 100.00% | 5 | 100.00% |
#endif
#ifdef CONFIG_SOC_TI81XX
void __init ti81xx_map_io(void)
{
iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
}
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#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
void __init am33xx_map_io(void)
{
iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
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Total | 18 | 100.00% | 3 | 100.00% |
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4_map_io(void)
{
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
omap_barriers_init();
}
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Santosh Shilimkar | 10 | 47.62% | 1 | 16.67% |
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Russell King | 3 | 14.29% | 1 | 16.67% |
Paul Walmsley | 1 | 4.76% | 1 | 16.67% |
Total | 21 | 100.00% | 6 | 100.00% |
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
omap_barriers_init();
}
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#endif
#ifdef CONFIG_SOC_DRA7XX
void __init dra7xx_map_io(void)
{
iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
omap_barriers_init();
}
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#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
* Sets the CORE DPLL3 M2 divider to the same value that it's at
* currently. This has the effect of setting the SDRC SDRAM AC timing
* registers to the values currently defined by the kernel. Currently
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
* or passes along the return value of clk_set_rate().
*/
static int __init _omap2_init_reprogram_sdrc(void)
{
struct clk *dpll3_m2_ck;
int v = -EINVAL;
long rate;
if (!cpu_is_omap34xx())
return 0;
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
rate = clk_get_rate(dpll3_m2_ck);
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
v = clk_set_rate(dpll3_m2_ck, rate);
if (v)
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
clk_put(dpll3_m2_ck);
return v;
}
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static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
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static void __init __maybe_unused omap_hwmod_init_postsetup(void)
{
u8 postsetup_state;
/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM
postsetup_state = _HWMOD_STATE_IDLE;
#else
postsetup_state = _HWMOD_STATE_ENABLED;
#endif
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
omap_pm_if_early_init();
}
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static void __init __maybe_unused omap_common_late_init(void)
{
omap2_common_pm_late_init();
omap_soc_device_init();
}
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#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
omap2_control_base_init();
omap2xxx_check_revision();
omap2_prcm_base_init();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table;
}
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void __init omap2420_init_late(void)
{
omap_common_late_init();
omap2_pm_init();
omap2_clk_enable_autoidle_all();
}
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#endif
#ifdef CONFIG_SOC_OMAP2430
void __init omap2430_init_early(void)
{
omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
omap2_control_base_init();
omap2xxx_check_revision();
omap2_prcm_base_init();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table;
}
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Rajendra Nayak | 1 | 1.59% | 1 | 9.09% |
Total | 63 | 100.00% | 11 | 100.00% |
void __init omap2430_init_late(void)
{
omap_common_late_init();
omap2_pm_init();
omap2_clk_enable_autoidle_all();
}
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#endif
/*
* Currently only board-omap3beagle.c should call this because of the
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
omap3xxx_check_features();
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
}
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void __init omap3430_init_early(void)
{
omap3_init_early();
omap_clk_soc_init = omap3430_dt_clk_init;
}
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void __init omap35xx_init_early(void)
{
omap3_init_early();
omap_clk_soc_init = omap3430_dt_clk_init;
}
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void __init omap3630_init_early(void)
{
omap3_init_early();
omap_clk_soc_init = omap3630_dt_clk_init;
}
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void __init am35xx_init_early(void)
{
omap3_init_early();
omap_clk_soc_init = am35xx_dt_clk_init;
}
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void __init omap3_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
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void __init omap3430_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Aida Mynzhasova | 17 | 100.00% | 1 | 100.00% |
Total | 17 | 100.00% | 1 | 100.00% |
void __init omap35xx_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Aida Mynzhasova | 17 | 100.00% | 1 | 100.00% |
Total | 17 | 100.00% | 1 | 100.00% |
void __init omap3630_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Aida Mynzhasova | 17 | 100.00% | 1 | 100.00% |
Total | 17 | 100.00% | 1 | 100.00% |
void __init am35xx_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Aida Mynzhasova | 17 | 100.00% | 1 | 100.00% |
Total | 17 | 100.00% | 1 | 100.00% |
void __init ti81xx_init_late(void)
{
omap_common_late_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Aida Mynzhasova | 14 | 100.00% | 1 | 100.00% |
Total | 14 | 100.00% | 1 | 100.00% |
#endif
#ifdef CONFIG_SOC_TI81XX
void __init ti814x_init_early(void)
{
omap2_set_globals_tap(TI814X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti814x_clockdomains_init();
dm814x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm814x_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Tony Lindgren | 28 | 57.14% | 7 | 58.33% |
Paul Walmsley | 9 | 18.37% | 1 | 8.33% |
Vaibhav Hiremath | 6 | 12.24% | 1 | 8.33% |
Tero Kristo | 6 | 12.24% | 3 | 25.00% |
Total | 49 | 100.00% | 12 | 100.00% |
void __init ti816x_init_early(void)
{
omap2_set_globals_tap(TI816X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti816x_clockdomains_init();
dm816x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm816x_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Tony Lindgren | 44 | 89.80% | 6 | 60.00% |
Tero Kristo | 4 | 8.16% | 3 | 30.00% |
Rajendra Nayak | 1 | 2.04% | 1 | 10.00% |
Total | 49 | 100.00% | 10 | 100.00% |
#endif
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
omap2_set_globals_tap(AM335X_CLASS,
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
omap2_prcm_base_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Afzal Mohammed | 14 | 30.43% | 1 | 7.69% |
Vaibhav Hiremath | 14 | 30.43% | 5 | 38.46% |
Paul Walmsley | 10 | 21.74% | 1 | 7.69% |
Tero Kristo | 7 | 15.22% | 5 | 38.46% |
Rajendra Nayak | 1 | 2.17% | 1 | 7.69% |
Total | 46 | 100.00% | 13 | 100.00% |
void __init am33xx_init_late(void)
{
omap_common_late_init();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nishanth Menon | 11 | 100.00% | 1 | 100.00% |
Total | 11 | 100.00% | 1 | 100.00% |
#endif
#ifdef CONFIG_SOC_AM43XX
void __init am43xx_init_early(void)
{
omap2_set_globals_tap(AM335X_CLASS,
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
omap2_prcm_base_init();
am43xx_powerdomains_init();
am43xx_clockdomains_init();
am43xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = am43xx_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Afzal Mohammed | 24 | 48.98% | 2 | 25.00% |
Ambresh K | 14 | 28.57% | 1 | 12.50% |
Tero Kristo | 8 | 16.33% | 4 | 50.00% |
Sekhar Nori | 3 | 6.12% | 1 | 12.50% |
Total | 49 | 100.00% | 8 | 100.00% |
void __init am43xx_init_late(void)
{
omap_common_late_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nishanth Menon | 11 | 78.57% | 1 | 50.00% |
Dave Gerlach | 3 | 21.43% | 1 | 50.00% |
Total | 14 | 100.00% | 2 | 100.00% |
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
omap2_set_globals_tap(OMAP443X_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
omap2_control_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
omap2_prcm_base_init();
omap4_sar_ram_init();
omap4_mpuss_early_init();
omap4_pm_init_early();
omap44xx_voltagedomains_init();
omap44xx_powerdomains_init();
omap44xx_clockdomains_init();
omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = omap4xxx_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Tony Lindgren | 33 | 47.83% | 5 | 31.25% |
Paul Walmsley | 17 | 24.64% | 2 | 12.50% |
Vaibhav Hiremath | 6 | 8.70% | 1 | 6.25% |
Tero Kristo | 6 | 8.70% | 5 | 31.25% |
Sekhar Nori | 3 | 4.35% | 1 | 6.25% |
Nishanth Menon | 3 | 4.35% | 1 | 6.25% |
Rajendra Nayak | 1 | 1.45% | 1 | 6.25% |
Total | 69 | 100.00% | 16 | 100.00% |
void __init omap4430_init_late(void)
{
omap_common_late_init();
omap4_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Shawn Guo | 13 | 76.47% | 1 | 33.33% |
Rajendra Nayak | 3 | 17.65% | 1 | 33.33% |
Ruslan Bilovol | 1 | 5.88% | 1 | 33.33% |
Total | 17 | 100.00% | 3 | 100.00% |
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_init_early(void)
{
omap2_set_globals_tap(OMAP54XX_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap2_control_base_init();
omap2_prcm_base_init();
omap5xxx_check_revision();
omap4_sar_ram_init();
omap4_mpuss_early_init();
omap4_pm_init_early();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap5xxx_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Walmsley | 19 | 30.16% | 2 | 20.00% |
Santosh Shilimkar | 17 | 26.98% | 1 | 10.00% |
R Sricharan | 12 | 19.05% | 1 | 10.00% |
Tony Lindgren | 9 | 14.29% | 2 | 20.00% |
Tero Kristo | 6 | 9.52% | 4 | 40.00% |
Total | 63 | 100.00% | 10 | 100.00% |
void __init omap5_init_late(void)
{
omap_common_late_init();
omap4_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nishanth Menon | 11 | 64.71% | 1 | 50.00% |
Santosh Shilimkar | 6 | 35.29% | 1 | 50.00% |
Total | 17 | 100.00% | 2 | 100.00% |
#endif
#ifdef CONFIG_SOC_DRA7XX
void __init dra7xx_init_early(void)
{
omap2_set_globals_tap(DRA7XX_CLASS,
OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap2_control_base_init();
omap4_pm_init_early();
omap2_prcm_base_init();
dra7xxx_check_revision();
dra7xx_powerdomains_init();
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dra7xx_dt_clk_init;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
R Sricharan | 29 | 53.70% | 1 | 12.50% |
Ambresh K | 14 | 25.93% | 1 | 12.50% |
Tero Kristo | 6 | 11.11% | 3 | 37.50% |
Nishanth Menon | 4 | 7.41% | 2 | 25.00% |
Rajendra Nayak | 1 | 1.85% | 1 | 12.50% |
Total | 54 | 100.00% | 8 | 100.00% |
void __init dra7xx_init_late(void)
{
omap_common_late_init();
omap4_pm_init();
omap2_clk_enable_autoidle_all();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nishanth Menon | 11 | 64.71% | 1 | 50.00% |
Rajendra Nayak | 6 | 35.29% | 1 | 50.00% |
Total | 17 | 100.00% | 2 | 100.00% |
#endif
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_sram_init();
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Walmsley | 20 | 51.28% | 4 | 36.36% |
Kevin Hilman | 9 | 23.08% | 1 | 9.09% |
Tony Lindgren | 5 | 12.82% | 3 | 27.27% |
Jean Pihet | 3 | 7.69% | 1 | 9.09% |
Hemant Pedanekar | 1 | 2.56% | 1 | 9.09% |
Juha Yrjölä | 1 | 2.56% | 1 | 9.09% |
Total | 39 | 100.00% | 11 | 100.00% |
int __init omap_clk_init(void)
{
int ret = 0;
if (!omap_clk_soc_init)
return 0;
ti_clk_init_features();
omap2_clk_setup_ll_ops();
ret = omap_control_init();
if (ret)
return ret;
ret = omap_prcm_init();
if (ret)
return ret;
of_clk_init(NULL);
ti_dt_clk_init_retry_clks();
ti_dt_clockdomains_setup();
ret = omap_clk_soc_init();
return ret;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Tero Kristo | 70 | 100.00% | 6 | 100.00% |
Total | 70 | 100.00% | 6 | 100.00% |
Overall Contributors
Person | Tokens | Prop | Commits | CommitProp |
Tony Lindgren | 427 | 17.25% | 32 | 25.40% |
Syed Mohammed Khasim | 371 | 14.99% | 2 | 1.59% |
Paul Walmsley | 366 | 14.79% | 17 | 13.49% |
Nishanth Menon | 270 | 10.91% | 6 | 4.76% |
R Sricharan | 184 | 7.43% | 2 | 1.59% |
Tero Kristo | 166 | 6.71% | 19 | 15.08% |
Afzal Mohammed | 132 | 5.33% | 5 | 3.97% |
Santosh Shilimkar | 123 | 4.97% | 3 | 2.38% |
Aida Mynzhasova | 104 | 4.20% | 1 | 0.79% |
Hemant Pedanekar | 76 | 3.07% | 2 | 1.59% |
Vaibhav Hiremath | 41 | 1.66% | 6 | 4.76% |
Shawn Guo | 39 | 1.58% | 1 | 0.79% |
Rajendra Nayak | 31 | 1.25% | 4 | 3.17% |
Ambresh K | 28 | 1.13% | 2 | 1.59% |
Kyungmin Park | 26 | 1.05% | 1 | 0.79% |
Ruslan Bilovol | 18 | 0.73% | 2 | 1.59% |
Kevin Hilman | 16 | 0.65% | 5 | 3.97% |
Aaro Koskinen | 15 | 0.61% | 2 | 1.59% |
Sanjeev Premi | 14 | 0.57% | 1 | 0.79% |
Russell King | 7 | 0.28% | 2 | 1.59% |
Sekhar Nori | 6 | 0.24% | 2 | 1.59% |
Jean Pihet | 3 | 0.12% | 1 | 0.79% |
Dave Gerlach | 3 | 0.12% | 1 | 0.79% |
Tomi Valkeinen | 2 | 0.08% | 1 | 0.79% |
Manjunath Kondaiah G | 2 | 0.08% | 1 | 0.79% |
Arnd Bergmann | 2 | 0.08% | 2 | 1.59% |
Juha Yrjölä | 1 | 0.04% | 1 | 0.79% |
Rafael J. Wysocki | 1 | 0.04% | 1 | 0.79% |
Paul Bolle | 1 | 0.04% | 1 | 0.79% |
Total | 2475 | 100.00% | 126 | 100.00% |
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