Release 4.13 arch/arm/plat-iop/time.c
/*
* arch/arm/plat-iop/time.c
*
* Timer code for IOP32x and IOP33x based systems
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright 2002-2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/sched_clock.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>
/*
* Minimum clocksource/clockevent timer range in seconds
*/
#define IOP_MIN_RANGE 4
/*
* IOP clocksource (free-running timer 1).
*/
static u64 notrace iop_clocksource_read(struct clocksource *unused)
{
return 0xffffffffu - read_tcr1();
}
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| Thomas Gleixner | 1 | 5.56% | 1 | 33.33% |
| Total | 18 | 100.00% | 3 | 100.00% |
static struct clocksource iop_clocksource = {
.name = "iop_timer1",
.rating = 300,
.read = iop_clocksource_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/*
* IOP sched_clock() implementation via its clocksource.
*/
static u64 notrace iop_read_sched_clock(void)
{
return 0xffffffffu - read_tcr1();
}
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| Stephen Boyd | 1 | 6.67% | 1 | 25.00% |
| Mikael Pettersson | 1 | 6.67% | 1 | 25.00% |
| Total | 15 | 100.00% | 4 | 100.00% |
/*
* IOP clockevents (interrupting timer 0).
*/
static int iop_set_next_event(unsigned long delta,
struct clock_event_device *unused)
{
u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
BUG_ON(delta == 0);
write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
write_tcr0(delta);
write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
return 0;
}
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static unsigned long ticks_per_jiffy;
static int iop_set_periodic(struct clock_event_device *evt)
{
u32 tmr = read_tmr0();
write_tmr0(tmr & ~IOP_TMR_EN);
write_tcr0(ticks_per_jiffy - 1);
write_trr0(ticks_per_jiffy - 1);
tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
write_tmr0(tmr);
return 0;
}
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| Russell King | 7 | 12.73% | 1 | 33.33% |
| Total | 55 | 100.00% | 3 | 100.00% |
static int iop_set_oneshot(struct clock_event_device *evt)
{
u32 tmr = read_tmr0();
/* ->set_next_event sets period and enables timer */
tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
write_tmr0(tmr);
return 0;
}
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| Mikael Pettersson | 12 | 34.29% | 1 | 50.00% |
| Total | 35 | 100.00% | 2 | 100.00% |
static int iop_shutdown(struct clock_event_device *evt)
{
u32 tmr = read_tmr0();
tmr &= ~IOP_TMR_EN;
write_tmr0(tmr);
return 0;
}
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static int iop_resume(struct clock_event_device *evt)
{
u32 tmr = read_tmr0();
tmr |= IOP_TMR_EN;
write_tmr0(tmr);
return 0;
}
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static struct clock_event_device iop_clockevent = {
.name = "iop_timer0",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = iop_set_next_event,
.set_state_shutdown = iop_shutdown,
.set_state_periodic = iop_set_periodic,
.tick_resume = iop_resume,
.set_state_oneshot = iop_set_oneshot,
};
static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
write_tisr(1);
evt->event_handler(evt);
return IRQ_HANDLED;
}
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| Lennert Buytenhek | 18 | 51.43% | 1 | 33.33% |
| Mikael Pettersson | 11 | 31.43% | 1 | 33.33% |
| Dan J Williams | 6 | 17.14% | 1 | 33.33% |
| Total | 35 | 100.00% | 3 | 100.00% |
static struct irqaction iop_timer_irq = {
.name = "IOP Timer Tick",
.handler = iop_timer_interrupt,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.dev_id = &iop_clockevent,
};
static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
return iop_tick_rate;
}
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| Dan J Williams | 11 | 100.00% | 1 | 100.00% |
| Total | 11 | 100.00% | 1 | 100.00% |
EXPORT_SYMBOL(get_iop_tick_rate);
void __init iop_init_time(unsigned long tick_rate)
{
u32 timer_ctl;
sched_clock_register(iop_read_sched_clock, 32, tick_rate);
ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
iop_tick_rate = tick_rate;
timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
/*
* Set up interrupting clockevent timer 0.
*/
write_tmr0(timer_ctl & ~IOP_TMR_EN);
write_tisr(1);
setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
iop_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&iop_clockevent, tick_rate,
0xf, 0xfffffffe);
/*
* Set up free-running clocksource timer 1.
*/
write_trr1(0xffffffff);
write_tcr1(0xffffffff);
write_tmr1(timer_ctl);
clocksource_register_hz(&iop_clocksource, tick_rate);
}
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| Mikael Pettersson | 44 | 39.29% | 2 | 16.67% |
| Lennert Buytenhek | 23 | 20.54% | 1 | 8.33% |
| Dan J Williams | 19 | 16.96% | 2 | 16.67% |
| Russell King | 13 | 11.61% | 3 | 25.00% |
| Shawn Guo | 7 | 6.25% | 1 | 8.33% |
| Julia Lawall | 4 | 3.57% | 1 | 8.33% |
| Marc Zyngier | 1 | 0.89% | 1 | 8.33% |
| Stephen Boyd | 1 | 0.89% | 1 | 8.33% |
| Total | 112 | 100.00% | 12 | 100.00% |
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| Dan J Williams | 51 | 8.69% | 2 | 8.70% |
| Russell King | 34 | 5.79% | 5 | 21.74% |
| Shawn Guo | 7 | 1.19% | 1 | 4.35% |
| Linus Walleij | 5 | 0.85% | 1 | 4.35% |
| Stephen Boyd | 5 | 0.85% | 2 | 8.70% |
| Julia Lawall | 4 | 0.68% | 1 | 4.35% |
| Marc Zyngier | 4 | 0.68% | 1 | 4.35% |
| Paul Gortmaker | 3 | 0.51% | 1 | 4.35% |
| Bernhard Walle | 2 | 0.34% | 1 | 4.35% |
| Rabin Vincent | 1 | 0.17% | 1 | 4.35% |
| Linus Torvalds | 1 | 0.17% | 1 | 4.35% |
| Thomas Gleixner | 1 | 0.17% | 1 | 4.35% |
| Total | 587 | 100.00% | 23 | 100.00% |
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