Release 4.14 arch/arm64/include/asm/arch_timer.h
/*
* arch/arm64/include/asm/arch_timer.h
*
* Copyright (C) 2012 ARM Ltd.
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_ARCH_TIMER_H
#define __ASM_ARCH_TIMER_H
#include <asm/barrier.h>
#include <asm/sysreg.h>
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/jump_label.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <clocksource/arm_arch_timer.h>
#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
extern struct static_key_false arch_timer_read_ool_enabled;
#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
#define needs_unstable_timer_counter_workaround() false
#endif
enum arch_timer_erratum_match_type {
ate_match_dt,
ate_match_local_cap_id,
ate_match_acpi_oem_info,
};
struct clock_event_device;
struct arch_timer_erratum_workaround {
enum arch_timer_erratum_match_type match_type;
const void *id;
const char *desc;
u32 (*read_cntp_tval_el0)(void);
u32 (*read_cntv_tval_el0)(void);
u64 (*read_cntvct_el0)(void);
int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
};
DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
timer_unstable_counter_workaround);
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
if (needs_unstable_timer_counter_workaround()) { \
const struct arch_timer_erratum_workaround *wa; \
preempt_disable_notrace(); \
wa = __this_cpu_read(timer_unstable_counter_workaround); \
if (wa && wa->read_##reg) \
_val = wa->read_##reg(); \
else \
_val = read_sysreg(reg); \
preempt_enable_notrace(); \
} else { \
_val = read_sysreg(reg); \
} \
_val; \
})
/*
* These register accessors are marked inline so the compiler can
* nicely work out which register we want, and chuck away the rest of
* the code.
*/
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntp_ctl_el0);
break;
case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntp_tval_el0);
break;
}
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntv_ctl_el0);
break;
case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntv_tval_el0);
break;
}
}
isb();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mark Rutland | 61 | 65.59% | 2 | 40.00% |
| Marc Zyngier | 28 | 30.11% | 1 | 20.00% |
| Stephen Boyd | 4 | 4.30% | 2 | 40.00% |
| Total | 93 | 100.00% | 5 | 100.00% |
static __always_inline
u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntp_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntp_tval_el0);
}
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntv_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntv_tval_el0);
}
}
BUG();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mark Rutland | 56 | 68.29% | 2 | 33.33% |
| Marc Zyngier | 20 | 24.39% | 1 | 16.67% |
| Stephen Boyd | 4 | 4.88% | 2 | 33.33% |
| Scott Wood | 2 | 2.44% | 1 | 16.67% |
| Total | 82 | 100.00% | 6 | 100.00% |
static inline u32 arch_timer_get_cntfrq(void)
{
return read_sysreg(cntfrq_el0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mark Rutland | 12 | 80.00% | 2 | 66.67% |
| Marc Zyngier | 3 | 20.00% | 1 | 33.33% |
| Total | 15 | 100.00% | 3 | 100.00% |
static inline u32 arch_timer_get_cntkctl(void)
{
return read_sysreg(cntkctl_el1);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 6 | 40.00% | 1 | 33.33% |
| Sudeep KarkadaNagesha | 5 | 33.33% | 1 | 33.33% |
| Mark Rutland | 4 | 26.67% | 1 | 33.33% |
| Total | 15 | 100.00% | 3 | 100.00% |
static inline void arch_timer_set_cntkctl(u32 cntkctl)
{
write_sysreg(cntkctl, cntkctl_el1);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sudeep KarkadaNagesha | 10 | 58.82% | 1 | 50.00% |
| Mark Rutland | 7 | 41.18% | 1 | 50.00% |
| Total | 17 | 100.00% | 2 | 100.00% |
static inline u64 arch_counter_get_cntpct(void)
{
/*
* AArch64 kernel and user space mandate the use of CNTVCT.
*/
BUG();
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sonny Rao | 16 | 100.00% | 1 | 100.00% |
| Total | 16 | 100.00% | 1 | 100.00% |
static inline u64 arch_counter_get_cntvct(void)
{
isb();
return arch_timer_reg_read_stable(cntvct_el0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 10 | 55.56% | 1 | 20.00% |
| Mark Rutland | 7 | 38.89% | 3 | 60.00% |
| Scott Wood | 1 | 5.56% | 1 | 20.00% |
| Total | 18 | 100.00% | 5 | 100.00% |
static inline int arch_timer_arch_init(void)
{
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Rob Herring | 12 | 100.00% | 1 | 100.00% |
| Total | 12 | 100.00% | 1 | 100.00% |
#endif
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mark Rutland | 163 | 37.64% | 3 | 16.67% |
| Marc Zyngier | 136 | 31.41% | 6 | 33.33% |
| Scott Wood | 51 | 11.78% | 1 | 5.56% |
| Ding Tianhong | 28 | 6.47% | 2 | 11.11% |
| Sonny Rao | 16 | 3.70% | 1 | 5.56% |
| Sudeep KarkadaNagesha | 15 | 3.46% | 1 | 5.56% |
| Rob Herring | 12 | 2.77% | 1 | 5.56% |
| Stephen Boyd | 9 | 2.08% | 2 | 11.11% |
| Paul Walmsley | 3 | 0.69% | 1 | 5.56% |
| Total | 433 | 100.00% | 18 | 100.00% |
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