Release 4.14 arch/arm64/kvm/reset.c
/*
* Copyright (C) 2012,2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* Derived from arch/arm/kvm/reset.c
* Copyright (C) 2012 - Virtual Open Systems and Columbia University
* Author: Christoffer Dall <c.dall@virtualopensystems.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/errno.h>
#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/hw_breakpoint.h>
#include <kvm/arm_arch_timer.h>
#include <asm/cputype.h>
#include <asm/ptrace.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_coproc.h>
#include <asm/kvm_mmu.h>
/*
* ARMv8 Reset Values
*/
static const struct kvm_regs default_regs_reset = {
.regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
PSR_F_BIT | PSR_D_BIT),
};
static const struct kvm_regs default_regs_reset32 = {
.regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
};
static bool cpu_has_32bit_el1(void)
{
u64 pfr0;
pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
return !!(pfr0 & 0x20);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 25 | 92.59% | 1 | 33.33% |
| Suzuki K. Poulose | 1 | 3.70% | 1 | 33.33% |
| Dave P Martin | 1 | 3.70% | 1 | 33.33% |
| Total | 27 | 100.00% | 3 | 100.00% |
/**
* kvm_arch_dev_ioctl_check_extension
*
* We currently assume that the number of HW registers is uniform
* across all CPUs (see cpuinfo_sanity_check).
*/
int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext)
{
int r;
switch (ext) {
case KVM_CAP_ARM_EL1_32BIT:
r = cpu_has_32bit_el1();
break;
case KVM_CAP_GUEST_DEBUG_HW_BPS:
r = get_num_brps();
break;
case KVM_CAP_GUEST_DEBUG_HW_WPS:
r = get_num_wrps();
break;
case KVM_CAP_ARM_PMU_V3:
r = kvm_arm_support_pmu_v3();
break;
case KVM_CAP_SET_GUEST_DEBUG:
case KVM_CAP_VCPU_ATTRIBUTES:
r = 1;
break;
default:
r = 0;
}
return r;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 34 | 44.16% | 2 | 33.33% |
| Alex Bennée | 26 | 33.77% | 1 | 16.67% |
| Shannon Zhao | 12 | 15.58% | 2 | 33.33% |
| Andre Przywara | 5 | 6.49% | 1 | 16.67% |
| Total | 77 | 100.00% | 6 | 100.00% |
/**
* kvm_reset_vcpu - sets core registers and sys_regs to reset value
* @vcpu: The VCPU pointer
*
* This function finds the right table above and sets the registers on
* the virtual CPU struct to their architecturally defined reset
* values.
*/
int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
{
const struct kvm_regs *cpu_reset;
switch (vcpu->arch.target) {
default:
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
if (!cpu_has_32bit_el1())
return -EINVAL;
cpu_reset = &default_regs_reset32;
} else {
cpu_reset = &default_regs_reset;
}
break;
}
/* Reset core registers */
memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset));
/* Reset system registers */
kvm_reset_sys_regs(vcpu);
/* Reset PMU */
kvm_pmu_vcpu_reset(vcpu);
/* Reset timer */
return kvm_timer_vcpu_reset(vcpu);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 96 | 94.12% | 4 | 80.00% |
| Shannon Zhao | 6 | 5.88% | 1 | 20.00% |
| Total | 102 | 100.00% | 5 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Marc Zyngier | 229 | 78.69% | 4 | 30.77% |
| Alex Bennée | 30 | 10.31% | 1 | 7.69% |
| Shannon Zhao | 18 | 6.19% | 3 | 23.08% |
| AKASHI Takahiro | 6 | 2.06% | 1 | 7.69% |
| Andre Przywara | 5 | 1.72% | 1 | 7.69% |
| Andrea Gelmini | 1 | 0.34% | 1 | 7.69% |
| Dave P Martin | 1 | 0.34% | 1 | 7.69% |
| Suzuki K. Poulose | 1 | 0.34% | 1 | 7.69% |
| Total | 291 | 100.00% | 13 | 100.00% |
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