Release 4.14 arch/blackfin/mach-common/cache-c.c
/*
* Blackfin cache control code (simpler control-style functions)
*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
/* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
*/
void blackfin_invalidate_entire_dcache(void)
{
u32 dmem = bfin_read_DMEM_CONTROL();
bfin_write_DMEM_CONTROL(dmem & ~0xc);
SSYNC();
bfin_write_DMEM_CONTROL(dmem);
SSYNC();
}
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/* Invalidate the Entire Instruction cache by
* clearing IMC bit
*/
void blackfin_invalidate_entire_icache(void)
{
u32 imem = bfin_read_IMEM_CONTROL();
bfin_write_IMEM_CONTROL(imem & ~0x4);
SSYNC();
bfin_write_IMEM_CONTROL(imem);
SSYNC();
}
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| Person | Tokens | Prop | Commits | CommitProp |
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| Total | 32 | 100.00% | 1 | 100.00% |
#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
static void
bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
unsigned long cplb_data, unsigned long mem_control,
unsigned long mem_mask)
{
int i;
#ifdef CONFIG_L1_PARITY_CHECK
u32 ctrl;
if (cplb_addr == DCPLB_ADDR0) {
ctrl = bfin_read32(mem_control) | (1 << RDCHK);
CSYNC();
bfin_write32(mem_control, ctrl);
SSYNC();
}
#endif
for (i = 0; i < MAX_CPLBS; i++) {
bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
}
_enable_cplb(mem_control, mem_mask);
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Mike Frysinger | 84 | 66.67% | 1 | 50.00% |
| Sonic Zhang | 42 | 33.33% | 1 | 50.00% |
| Total | 126 | 100.00% | 2 | 100.00% |
#ifdef CONFIG_BFIN_ICACHE
void bfin_icache_init(struct cplb_entry *icplb_tbl)
{
bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
(IMC | ENICPLB));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mike Frysinger | 27 | 100.00% | 1 | 100.00% |
| Total | 27 | 100.00% | 1 | 100.00% |
#endif
#ifdef CONFIG_BFIN_DCACHE
void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
{
/*
* Anomaly notes:
* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
* register, so that the port preferences for DAG0 and DAG1 are set
* to port B
*/
bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Mike Frysinger | 36 | 100.00% | 1 | 100.00% |
| Total | 36 | 100.00% | 1 | 100.00% |
#endif
#endif
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Mike Frysinger | 209 | 73.33% | 2 | 40.00% |
| Sonic Zhang | 75 | 26.32% | 2 | 40.00% |
| Robin Getz | 1 | 0.35% | 1 | 20.00% |
| Total | 285 | 100.00% | 5 | 100.00% |
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