Release 4.14 arch/m68k/mm/memory.c
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/memory.c
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/gfp.h>
#include <asm/setup.h>
#include <asm/segment.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/traps.h>
#include <asm/machdep.h>
/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
struct page instead of separately kmalloced struct. Stolen from
arch/sparc/mm/srmmu.c ... */
typedef struct list_head ptable_desc;
static LIST_HEAD(ptable_list);
#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
void __init init_pointer_table(unsigned long ptable)
{
ptable_desc *dp;
unsigned long page = ptable & PAGE_MASK;
unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
dp = PD_PTABLE(page);
if (!(PD_MARKBITS(dp) & mask)) {
PD_MARKBITS(dp) = 0xff;
list_add(dp, &ptable_list);
}
PD_MARKBITS(dp) &= ~mask;
pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
/* unreserve the page so it's possible to free that page */
PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
init_page_count(PD_PAGE(dp));
return;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 116 | 98.31% | 3 | 60.00% |
| Nicholas Piggin | 1 | 0.85% | 1 | 20.00% |
| Geert Uytterhoeven | 1 | 0.85% | 1 | 20.00% |
| Total | 118 | 100.00% | 5 | 100.00% |
pmd_t *get_pointer_table (void)
{
ptable_desc *dp = ptable_list.next;
unsigned char mask = PD_MARKBITS (dp);
unsigned char tmp;
unsigned int off;
/*
* For a pointer table for a user process address space, a
* table is taken from a page allocated for the purpose. Each
* page can hold 8 pointer tables. The page is remapped in
* virtual address space to be noncacheable.
*/
if (mask == 0) {
void *page;
ptable_desc *new;
if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
return NULL;
flush_tlb_kernel_page(page);
nocache_page(page);
new = PD_PTABLE(page);
PD_MARKBITS(new) = 0xfe;
list_add_tail(new, dp);
return (pmd_t *)page;
}
for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
;
PD_MARKBITS(dp) = mask & ~tmp;
if (!PD_MARKBITS(dp)) {
/* move to end of list */
list_move_tail(dp, &ptable_list);
}
return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 171 | 95.00% | 5 | 55.56% |
| Geert Uytterhoeven | 7 | 3.89% | 2 | 22.22% |
| Akinobu Mita | 1 | 0.56% | 1 | 11.11% |
| Andrew Morton | 1 | 0.56% | 1 | 11.11% |
| Total | 180 | 100.00% | 9 | 100.00% |
int free_pointer_table (pmd_t *ptable)
{
ptable_desc *dp;
unsigned long page = (unsigned long)ptable & PAGE_MASK;
unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
dp = PD_PTABLE(page);
if (PD_MARKBITS (dp) & mask)
panic ("table already free!");
PD_MARKBITS (dp) |= mask;
if (PD_MARKBITS(dp) == 0xff) {
/* all tables in page are free, free page */
list_del(dp);
cache_page((void *)page);
free_page (page);
return 1;
} else if (ptable_list.next != dp) {
/*
* move this descriptor to the front of the list, since
* it has one or more free tables.
*/
list_move(dp, &ptable_list);
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 125 | 96.15% | 5 | 71.43% |
| Geert Uytterhoeven | 4 | 3.08% | 1 | 14.29% |
| Akinobu Mita | 1 | 0.77% | 1 | 14.29% |
| Total | 130 | 100.00% | 7 | 100.00% |
/* invalidate page in both caches */
static inline void clear040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cinvp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Geert Uytterhoeven | 10 | 71.43% | 1 | 50.00% |
| Linus Torvalds (pre-git) | 4 | 28.57% | 1 | 50.00% |
| Total | 14 | 100.00% | 2 | 100.00% |
/* invalidate page in i-cache */
static inline void cleari040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cinvp %%ic,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Geert Uytterhoeven | 10 | 71.43% | 1 | 50.00% |
| Linus Torvalds (pre-git) | 4 | 28.57% | 1 | 50.00% |
| Total | 14 | 100.00% | 2 | 100.00% |
/* push page in both caches */
/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
static inline void push040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Geert Uytterhoeven | 10 | 71.43% | 1 | 50.00% |
| Linus Torvalds (pre-git) | 4 | 28.57% | 1 | 50.00% |
| Total | 14 | 100.00% | 2 | 100.00% |
/* push and invalidate page in both caches, must disable ints
* to avoid invalidating valid data */
static inline void pushcl040(unsigned long paddr)
{
unsigned long flags;
local_irq_save(flags);
push040(paddr);
if (CPU_IS_060)
clear040(paddr);
local_irq_restore(flags);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Geert Uytterhoeven | 34 | 87.18% | 1 | 33.33% |
| Linus Torvalds (pre-git) | 5 | 12.82% | 2 | 66.67% |
| Total | 39 | 100.00% | 3 | 100.00% |
/*
* 040: Hit every page containing an address in the range paddr..paddr+len-1.
* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
* Hit every page until there is a page or less to go. Hit the next page,
* and the one after that if the range hits it.
*/
/* ++roman: A little bit more care is required here: The CINVP instruction
* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
* and the end of the region must be treated differently if they are not
* exactly at the beginning or end of a page boundary. Else, maybe too much
* data becomes invalidated and thus lost forever. CPUSHP does what we need:
* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
* for discovering the problem!)
*/
/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
* the DPI bit in the CACR; would it cause problems with temporarily changing
* this?). So we have to push first and then additionally to invalidate.
*/
/*
* cache_clear() semantics: Clear any cache entries for the area in question,
* without writing back dirty entries first. This is useful if the data will
* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
* _physical_ address.
*/
void cache_clear (unsigned long paddr, int len)
{
if (CPU_IS_COLDFIRE) {
clear_cf_bcache(0, DCACHE_MAX_ADDR);
} else if (CPU_IS_040_OR_060) {
int tmp;
/*
* We need special treatment for the first page, in case it
* is not page-aligned. Page align the addresses to work
* around bug I17 in the 68060.
*/
if ((tmp = -paddr & (PAGE_SIZE - 1))) {
pushcl040(paddr & PAGE_MASK);
if ((len -= tmp) <= 0)
return;
paddr += tmp;
}
tmp = PAGE_SIZE;
paddr &= PAGE_MASK;
while ((len -= tmp) >= 0) {
clear040(paddr);
paddr += tmp;
}
if ((len += tmp))
/* a page boundary gets crossed at the end */
pushcl040(paddr);
}
else /* 68030 or 68020 */
asm volatile ("movec %/cacr,%/d0\n\t"
"oriw %0,%/d0\n\t"
"movec %/d0,%/cacr"
: : "i" (FLUSH_I_AND_D)
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
mach_l2_flush(0);
#endif
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 123 | 89.78% | 5 | 71.43% |
| Greg Ungerer | 14 | 10.22% | 2 | 28.57% |
| Total | 137 | 100.00% | 7 | 100.00% |
EXPORT_SYMBOL(cache_clear);
/*
* cache_push() semantics: Write back any dirty cache data in the given area,
* and invalidate the range in the instruction cache. It needs not (but may)
* invalidate those entries also in the data cache. The range is defined by a
* _physical_ address.
*/
void cache_push (unsigned long paddr, int len)
{
if (CPU_IS_COLDFIRE) {
flush_cf_bcache(0, DCACHE_MAX_ADDR);
} else if (CPU_IS_040_OR_060) {
int tmp = PAGE_SIZE;
/*
* on 68040 or 68060, push cache lines for pages in the range;
* on the '040 this also invalidates the pushed lines, but not on
* the '060!
*/
len += paddr & (PAGE_SIZE - 1);
/*
* Work around bug I17 in the 68060 affecting some instruction
* lines not being invalidated properly.
*/
paddr &= PAGE_MASK;
do {
push040(paddr);
paddr += tmp;
} while ((len -= tmp) > 0);
}
/*
* 68030/68020 have no writeback cache. On the other hand,
* cache_push is actually a superset of cache_clear (the lines
* get written back and invalidated), so we should make sure
* to perform the corresponding actions. After all, this is getting
* called in places where we've just loaded code, or whatever, so
* flushing the icache is appropriate; flushing the dcache shouldn't
* be required.
*/
else /* 68030 or 68020 */
asm volatile ("movec %/cacr,%/d0\n\t"
"oriw %0,%/d0\n\t"
"movec %/d0,%/cacr"
: : "i" (FLUSH_I)
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
mach_l2_flush(1);
#endif
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 81 | 84.38% | 5 | 71.43% |
| Greg Ungerer | 14 | 14.58% | 1 | 14.29% |
| Geert Uytterhoeven | 1 | 1.04% | 1 | 14.29% |
| Total | 96 | 100.00% | 7 | 100.00% |
EXPORT_SYMBOL(cache_push);
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Linus Torvalds (pre-git) | 713 | 84.58% | 15 | 51.72% |
| Geert Uytterhoeven | 78 | 9.25% | 4 | 13.79% |
| Greg Ungerer | 28 | 3.32% | 2 | 6.90% |
| Al Viro | 13 | 1.54% | 1 | 3.45% |
| Tejun Heo | 3 | 0.36% | 1 | 3.45% |
| Andrew Morton | 3 | 0.36% | 2 | 6.90% |
| Akinobu Mita | 2 | 0.24% | 1 | 3.45% |
| Linus Torvalds | 1 | 0.12% | 1 | 3.45% |
| Nicholas Piggin | 1 | 0.12% | 1 | 3.45% |
| Greg Kroah-Hartman | 1 | 0.12% | 1 | 3.45% |
| Total | 843 | 100.00% | 29 | 100.00% |
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