Release 4.14 arch/mips/dec/kn02-irq.c

/*
 *      DECstation 5000/200 (KN02) Control and Status Register
 *      interrupts.
 *
 *      Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>

#include <asm/dec/kn02.h>


/*
 * Bits 7:0 of the Control Register are write-only -- the
 * corresponding bits of the Status Register have a different
 * meaning.  Hence we use a cache.  It speeds up things a bit
 * as well.
 *
 * There is no default value -- it has to be initialized.
 */

u32 cached_kn02_csr;


static int kn02_irq_base;



static void unmask_kn02_irq(struct irq_data *d)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);

	cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
	*csr = cached_kn02_csr;
}

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37
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Thomas Gleixner
6
12.24%
1
33.33%
Maciej W. Rozycki
6
12.24%
1
33.33%
Total
49
100.00%
3
100.00%



static void mask_kn02_irq(struct irq_data *d)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);

	cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
	*csr = cached_kn02_csr;
}

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Ralf Bächle
38
76.00%
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Maciej W. Rozycki
6
12.00%
1
33.33%
Thomas Gleixner
6
12.00%
1
33.33%
Total
50
100.00%
3
100.00%



static void ack_kn02_irq(struct irq_data *d)
{
	mask_kn02_irq(d);
	iob();
}

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19
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2
100.00%


static struct irq_chip kn02_irq_type = {
	.name = "KN02-CSR",
	.irq_ack = ack_kn02_irq,
	.irq_mask = mask_kn02_irq,
	.irq_mask_ack = ack_kn02_irq,
	.irq_unmask = unmask_kn02_irq,
};



void __init init_kn02_irqs(int base)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);
	int i;

	/* Mask interrupts. */
	cached_kn02_csr &= ~KN02_CSR_IOINTEN;
	*csr = cached_kn02_csr;
	iob();

	for (i = base; i < base + KN02_IRQ_LINES; i++)
		irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);

	kn02_irq_base = base;
}
Contributors
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CommitProp
Ralf Bächle
59
81.94%
1
16.67%
Maciej W. Rozycki
7
9.72%
2
33.33%
Atsushi Nemoto
5
6.94%
2
33.33%
Thomas Gleixner
1
1.39%
1
16.67%
Total
72
100.00%
6
100.00%

Overall Contributors
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CommitProp
Ralf Bächle
192
79.01%
3
30.00%
Thomas Gleixner
22
9.05%
2
20.00%
Maciej W. Rozycki
19
7.82%
2
20.00%
Atsushi Nemoto
10
4.12%
3
30.00%
Total
243
100.00%
10
100.00%
Directory: arch/mips/dec

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