Release 4.14 arch/mips/lib/mips-atomic.c
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#include <asm/irqflags.h>
#include <asm/hazards.h>
#include <linux/compiler.h>
#include <linux/preempt.h>
#include <linux/export.h>
#include <linux/stringify.h>
#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6)
/*
* For cli() we have to insert nops to make sure that the new value
* has actually arrived in the status register before the end of this
* macro.
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
/*
* For TX49, operating only IE bit is not enough.
*
* If mfc0 $12 follows store and the mfc0 is last instruction of a
* page and fetching the next instruction causes TLB miss, the result
* of the mfc0 might wrongly contain EXL bit.
*
* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
*
* Workaround: mask EXL bit of the result or place a nop before mfc0.
*/
notrace void arch_local_irq_disable(void)
{
preempt_disable();
__asm__ __volatile__(
" .set push \n"
" .set noat \n"
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
" xori $1,0x1f \n"
" .set noreorder \n"
" mtc0 $1,$12 \n"
" " __stringify(__irq_disable_hazard) " \n"
" .set pop \n"
: /* no outputs */
: /* no inputs */
: "memory");
preempt_enable();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Ralf Bächle | 12 | 57.14% | 1 | 33.33% |
| Jim Quinlan | 8 | 38.10% | 1 | 33.33% |
| Markos Chandras | 1 | 4.76% | 1 | 33.33% |
| Total | 21 | 100.00% | 3 | 100.00% |
EXPORT_SYMBOL(arch_local_irq_disable);
notrace unsigned long arch_local_irq_save(void)
{
unsigned long flags;
preempt_disable();
__asm__ __volatile__(
" .set push \n"
" .set reorder \n"
" .set noat \n"
" mfc0 %[flags], $12 \n"
" ori $1, %[flags], 0x1f \n"
" xori $1, 0x1f \n"
" .set noreorder \n"
" mtc0 $1, $12 \n"
" " __stringify(__irq_disable_hazard) " \n"
" .set pop \n"
: [flags] "=r" (flags)
: /* no inputs */
: "memory");
preempt_enable();
return flags;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Jim Quinlan | 23 | 85.19% | 1 | 25.00% |
| Ralf Bächle | 2 | 7.41% | 1 | 25.00% |
| Al Cooper | 1 | 3.70% | 1 | 25.00% |
| Markos Chandras | 1 | 3.70% | 1 | 25.00% |
| Total | 27 | 100.00% | 4 | 100.00% |
EXPORT_SYMBOL(arch_local_irq_save);
notrace void arch_local_irq_restore(unsigned long flags)
{
unsigned long __tmp1;
preempt_disable();
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" mfc0 $1, $12 \n"
" andi %[flags], 1 \n"
" ori $1, 0x1f \n"
" xori $1, 0x1f \n"
" or %[flags], $1 \n"
" mtc0 %[flags], $12 \n"
" " __stringify(__irq_disable_hazard) " \n"
" .set pop \n"
: [flags] "=r" (__tmp1)
: "0" (flags)
: "memory");
preempt_enable();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Jim Quinlan | 21 | 91.30% | 1 | 33.33% |
| Al Cooper | 1 | 4.35% | 1 | 33.33% |
| Markos Chandras | 1 | 4.35% | 1 | 33.33% |
| Total | 23 | 100.00% | 3 | 100.00% |
EXPORT_SYMBOL(arch_local_irq_restore);
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Jim Quinlan | 88 | 71.54% | 1 | 16.67% |
| Ralf Bächle | 17 | 13.82% | 1 | 16.67% |
| Markos Chandras | 15 | 12.20% | 2 | 33.33% |
| Al Cooper | 2 | 1.63% | 1 | 16.67% |
| Huacai Chen | 1 | 0.81% | 1 | 16.67% |
| Total | 123 | 100.00% | 6 | 100.00% |
Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.