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Release 4.14 arch/powerpc/include/asm/hugetlb.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_HUGETLB_H

#define _ASM_POWERPC_HUGETLB_H

#ifdef CONFIG_HUGETLB_PAGE
#include <asm/page.h>
#include <asm-generic/hugetlb.h>

extern struct kmem_cache *hugepte_cache;

#ifdef CONFIG_PPC_BOOK3S_64

#include <asm/book3s/64/hugetlb.h>
/*
 * This should work for other subarchs too. But right now we use the
 * new format only for 64bit book3s
 */

static inline pte_t *hugepd_page(hugepd_t hpd) { BUG_ON(!hugepd_ok(hpd)); /* * We have only four bits to encode, MMU page size */ BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf); return __va(hpd_val(hpd) & HUGEPD_ADDR_MASK); }

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Aneesh Kumar K.V3990.70%266.67%
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static inline unsigned int hugepd_mmu_psize(hugepd_t hpd) { return (hpd_val(hpd) & HUGEPD_SHIFT_MASK) >> 2; }

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static inline unsigned int hugepd_shift(hugepd_t hpd) { return mmu_psize_to_shift(hugepd_mmu_psize(hpd)); }

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static inline void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { if (radix_enabled()) return radix__flush_hugetlb_page(vma, vmaddr); }

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static inline void __local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { if (radix_enabled()) return radix__local_flush_hugetlb_page(vma, vmaddr); }

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#else
static inline pte_t *hugepd_page(hugepd_t hpd) { BUG_ON(!hugepd_ok(hpd)); #ifdef CONFIG_PPC_8xx return (pte_t *)__va(hpd_val(hpd) & ~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK)); #else return (pte_t *)((hpd_val(hpd) & ~HUGEPD_SHIFT_MASK) | PD_HUGE); #endif }

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static inline unsigned int hugepd_shift(hugepd_t hpd) { #ifdef CONFIG_PPC_8xx return ((hpd_val(hpd) & _PMD_PAGE_MASK) >> 1) + 17; #else return hpd_val(hpd) & HUGEPD_SHIFT_MASK; #endif }

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Christophe Leroy2047.62%133.33%
Becky Bruce1638.10%133.33%
Aneesh Kumar K.V614.29%133.33%
Total42100.00%3100.00%

#endif /* CONFIG_PPC_BOOK3S_64 */
static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr, unsigned pdshift) { /* * On FSL BookE, we have multiple higher-level table entries that * point to the same hugepte. Just use the first one since they're all * identical. So for that case, idx=0. */ unsigned long idx = 0; pte_t *dir = hugepd_page(hpd); #ifndef CONFIG_PPC_FSL_BOOK3E idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(hpd); #endif return dir + idx; }

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pte_t *huge_pte_offset_and_shift(struct mm_struct *mm, unsigned long addr, unsigned *shift); void flush_dcache_icache_hugepage(struct page *page); #if defined(CONFIG_PPC_MM_SLICES) int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, unsigned long len); #else
static inline int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, unsigned long len) { return 0; }

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#endif void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea, pte_t pte); #ifdef CONFIG_PPC_8xx
static inline void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { flush_tlb_page(vma, vmaddr); }

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#else void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr); #endif void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, unsigned long end, unsigned long floor, unsigned long ceiling); /* * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs * to override the version in mm/hugetlb.c */ #define vma_mmu_pagesize vma_mmu_pagesize /* * If the arch doesn't supply something else, assume that hugepage * size aligned regions are ok without further preparation. */
static inline int prepare_hugepage_range(struct file *file, unsigned long addr, unsigned long len) { struct hstate *h = hstate_file(file); if (len & ~huge_page_mask(h)) return -EINVAL; if (addr & ~huge_page_mask(h)) return -EINVAL; return 0; }

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Gerald Schaefer3862.30%133.33%
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Andi Kleen58.20%133.33%
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static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) { set_pte_at(mm, addr, ptep, pte); }

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static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { #ifdef CONFIG_PPC64 return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1)); #else return __pte(pte_update(ptep, ~0UL, 0)); #endif }

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David Gibson3862.30%133.33%
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Aneesh Kumar K.V23.28%133.33%
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static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) { pte_t pte; pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep); flush_hugetlb_page(vma, addr); }

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David Gibson2455.81%133.33%
Gerald Schaefer1841.86%133.33%
Aneesh Kumar K.V12.33%133.33%
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static inline int huge_pte_none(pte_t pte) { return pte_none(pte); }

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Gerald Schaefer16100.00%1100.00%
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static inline pte_t huge_pte_wrprotect(pte_t pte) { return pte_wrprotect(pte); }

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Gerald Schaefer16100.00%1100.00%
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static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, pte_t pte, int dirty) { #ifdef HUGETLB_NEED_PRELOAD /* * The "return 1" forces a call of update_mmu_cache, which will write a * TLB entry. Without this, platforms that don't do a write of the TLB * entry in the TLB miss handler asm will fault ad infinitum. */ ptep_set_access_flags(vma, addr, ptep, pte, dirty); return 1; #else return ptep_set_access_flags(vma, addr, ptep, pte, dirty); #endif }

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Gerald Schaefer4062.50%133.33%
Becky Bruce2437.50%266.67%
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static inline pte_t huge_ptep_get(pte_t *ptep) { return *ptep; }

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Gerald Schaefer15100.00%1100.00%
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static inline void arch_clear_hugepage_flags(struct page *page) { }

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#else /* ! CONFIG_HUGETLB_PAGE */
static inline void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { }

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#define hugepd_shift(x) 0
static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr, unsigned pdshift) { return 0; }

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#endif /* CONFIG_HUGETLB_PAGE */ #endif /* _ASM_POWERPC_HUGETLB_H */

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Becky Bruce25128.17%622.22%
Gerald Schaefer20122.56%414.81%
Aneesh Kumar K.V19822.22%829.63%
David Gibson12313.80%27.41%
Christophe Leroy748.31%13.70%
Jon Tollefson182.02%13.70%
Will Deacon111.23%13.70%
Mel Gorman50.56%13.70%
Andi Kleen50.56%13.70%
Paul Mackerras40.45%13.70%
Greg Kroah-Hartman10.11%13.70%
Total891100.00%27100.00%
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