Release 4.14 arch/powerpc/kernel/traps.c
/*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Modified by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras (paulus@samba.org)
*/
/*
* This file handles the architecture-dependent parts of hardware exceptions
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/extable.h>
#include <linux/module.h> /* print_modules */
#include <linux/prctl.h>
#include <linux/delay.h>
#include <linux/kprobes.h>
#include <linux/kexec.h>
#include <linux/backlight.h>
#include <linux/bug.h>
#include <linux/kdebug.h>
#include <linux/ratelimit.h>
#include <linux/context_tracking.h>
#include <asm/emulated_ops.h>
#include <asm/pgtable.h>
#include <linux/uaccess.h>
#include <asm/debugfs.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/rtas.h>
#include <asm/pmc.h>
#include <asm/reg.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#ifdef CONFIG_PPC64
#include <asm/firmware.h>
#include <asm/processor.h>
#include <asm/tm.h>
#endif
#include <asm/kexec.h>
#include <asm/ppc-opcode.h>
#include <asm/rio.h>
#include <asm/fadump.h>
#include <asm/switch_to.h>
#include <asm/tm.h>
#include <asm/debug.h>
#include <asm/asm-prototypes.h>
#include <asm/hmi.h>
#include <sysdev/fsl_pci.h>
#include <asm/kprobes.h>
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
EXPORT_SYMBOL(__debugger);
EXPORT_SYMBOL(__debugger_ipi);
EXPORT_SYMBOL(__debugger_bpt);
EXPORT_SYMBOL(__debugger_sstep);
EXPORT_SYMBOL(__debugger_iabr_match);
EXPORT_SYMBOL(__debugger_break_match);
EXPORT_SYMBOL(__debugger_fault_handler);
#endif
/* Transactional Memory trap debug */
#ifdef TM_DEBUG_SW
#define TM_DEBUG(x...) printk(KERN_INFO x)
#else
#define TM_DEBUG(x...) do { } while(0)
#endif
/*
* Trap & Exception support
*/
#ifdef CONFIG_PMAC_BACKLIGHT
static void pmac_backlight_unblank(void)
{
mutex_lock(&pmac_backlight_mutex);
if (pmac_backlight) {
struct backlight_properties *props;
props = &pmac_backlight->props;
props->brightness = props->max_brightness;
props->power = FB_BLANK_UNBLANK;
backlight_update_status(pmac_backlight);
}
mutex_unlock(&pmac_backlight_mutex);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 57 | 100.00% | 1 | 100.00% |
Total | 57 | 100.00% | 1 | 100.00% |
#else
static inline void pmac_backlight_unblank(void) { }
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 8 | 100.00% | 1 | 100.00% |
Total | 8 | 100.00% | 1 | 100.00% |
#endif
/*
* If oops/die is expected to crash the machine, return true here.
*
* This should not be expected to be 100% accurate, there may be
* notifiers registered or other unexpected conditions that may bring
* down the kernel. Or if the current process in the kernel is holding
* locks or has other critical state, the kernel may become effectively
* unusable anyway.
*/
bool die_will_crash(void)
{
if (should_fadump_crash())
return true;
if (kexec_should_crash(current))
return true;
if (in_interrupt() || panic_on_oops ||
!current->pid || is_global_init(current))
return true;
return false;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nicholas Piggin | 48 | 100.00% | 1 | 100.00% |
Total | 48 | 100.00% | 1 | 100.00% |
static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
static int die_owner = -1;
static unsigned int die_nest_count;
static int die_counter;
static unsigned long oops_begin(struct pt_regs *regs)
{
int cpu;
unsigned long flags;
oops_enter();
/* racy, but better than risking deadlock. */
raw_local_irq_save(flags);
cpu = smp_processor_id();
if (!arch_spin_trylock(&die_lock)) {
if (cpu == die_owner)
/* nested oops. should stop eventually */;
else
arch_spin_lock(&die_lock);
}
die_nest_count++;
die_owner = cpu;
console_verbose();
bust_spinlocks(1);
if (machine_is(powermac))
pmac_backlight_unblank();
return flags;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 70 | 80.46% | 4 | 57.14% |
Paul Mackerras | 12 | 13.79% | 1 | 14.29% |
Benjamin Herrenschmidt | 4 | 4.60% | 1 | 14.29% |
Michael Hanselmann | 1 | 1.15% | 1 | 14.29% |
Total | 87 | 100.00% | 7 | 100.00% |
NOKPROBE_SYMBOL(oops_begin);
static void oops_end(unsigned long flags, struct pt_regs *regs,
int signr)
{
bust_spinlocks(0);
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
die_nest_count--;
oops_exit();
printk("\n");
if (!die_nest_count) {
/* Nest count reaches zero, release the lock. */
die_owner = -1;
arch_spin_unlock(&die_lock);
}
raw_local_irq_restore(flags);
crash_fadump(regs, "die oops");
if (kexec_should_crash(current))
crash_kexec(regs);
if (!signr)
return;
/*
* While our oops output is serialised by a spinlock, output
* from panic() called below can race and corrupt it. If we
* know we are going to panic, delay for 1 second so we have a
* chance to get clean backtraces from all CPUs that are oopsing.
*/
if (in_interrupt() || panic_on_oops || !current->pid ||
is_global_init(current)) {
mdelay(MSEC_PER_SEC);
}
if (in_interrupt())
panic("Fatal exception in interrupt");
if (panic_on_oops)
panic("Fatal exception");
do_exit(signr);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 123 | 88.49% | 2 | 40.00% |
Mahesh Salgaonkar | 7 | 5.04% | 1 | 20.00% |
Nicholas Piggin | 7 | 5.04% | 1 | 20.00% |
Rusty Russell | 2 | 1.44% | 1 | 20.00% |
Total | 139 | 100.00% | 5 | 100.00% |
NOKPROBE_SYMBOL(oops_end);
static int __die(const char *str, struct pt_regs *regs, long err)
{
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
printk("LE ");
else
printk("BE ");
if (IS_ENABLED(CONFIG_PREEMPT))
pr_cont("PREEMPT ");
if (IS_ENABLED(CONFIG_SMP))
pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
if (debug_pagealloc_enabled())
pr_cont("DEBUG_PAGEALLOC ");
if (IS_ENABLED(CONFIG_NUMA))
pr_cont("NUMA ");
pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
return 1;
print_modules();
show_regs(regs);
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 45 | 31.03% | 3 | 33.33% |
Paul Mackerras | 45 | 31.03% | 1 | 11.11% |
Michael Ellerman | 41 | 28.28% | 3 | 33.33% |
Benjamin Herrenschmidt | 9 | 6.21% | 1 | 11.11% |
JoonSoo Kim | 5 | 3.45% | 1 | 11.11% |
Total | 145 | 100.00% | 9 | 100.00% |
NOKPROBE_SYMBOL(__die);
void die(const char *str, struct pt_regs *regs, long err)
{
unsigned long flags;
if (debugger(regs))
return;
flags = oops_begin(regs);
if (__die(str, regs, err))
err = 0;
oops_end(flags, regs, err);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Anton Blanchard | 35 | 57.38% | 3 | 50.00% |
Paul Mackerras | 13 | 21.31% | 1 | 16.67% |
Nicholas Piggin | 12 | 19.67% | 1 | 16.67% |
David J. Wilder | 1 | 1.64% | 1 | 16.67% |
Total | 61 | 100.00% | 6 | 100.00% |
NOKPROBE_SYMBOL(die);
void user_single_step_siginfo(struct task_struct *tsk,
struct pt_regs *regs, siginfo_t *info)
{
memset(info, 0, sizeof(*info));
info->si_signo = SIGTRAP;
info->si_code = TRAP_TRACE;
info->si_addr = (void __user *)regs->nip;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Oleg Nesterov | 57 | 100.00% | 1 | 100.00% |
Total | 57 | 100.00% | 1 | 100.00% |
void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
{
siginfo_t info;
const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
"at %08lx nip %08lx lr %08lx code %x\n";
const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
"at %016lx nip %016lx lr %016lx code %x\n";
if (!user_mode(regs)) {
die("Exception in kernel mode", regs, signr);
return;
}
if (show_unhandled_signals && unhandled_signal(current, signr)) {
printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
current->comm, current->pid, signr,
addr, regs->nip, regs->link, code);
}
if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
local_irq_enable();
current->thread.trap_nr = code;
memset(&info, 0, sizeof(info));
info.si_signo = signr;
info.si_code = code;
info.si_addr = (void __user *) addr;
force_sig_info(signr, &info, current);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 88 | 49.16% | 1 | 12.50% |
Olof Johansson | 66 | 36.87% | 1 | 12.50% |
Benjamin Herrenschmidt | 14 | 7.82% | 2 | 25.00% |
Ananth N. Mavinakayanahalli | 8 | 4.47% | 1 | 12.50% |
Michael Ellerman | 1 | 0.56% | 1 | 12.50% |
Christian Dietrich | 1 | 0.56% | 1 | 12.50% |
Anton Blanchard | 1 | 0.56% | 1 | 12.50% |
Total | 179 | 100.00% | 8 | 100.00% |
void system_reset_exception(struct pt_regs *regs)
{
/*
* Avoid crashes in case of nested NMI exceptions. Recoverability
* is determined by RI and in_nmi
*/
bool nested = in_nmi();
if (!nested)
nmi_enter();
__this_cpu_inc(irq_stat.sreset_irqs);
/* See if any machine dependent calls */
if (ppc_md.system_reset_exception) {
if (ppc_md.system_reset_exception(regs))
goto out;
}
if (debugger(regs))
goto out;
/*
* A system reset is a request to dump, so we always send
* it through the crashdump code (if fadump or kdump are
* registered).
*/
crash_fadump(regs, "System Reset");
crash_kexec(regs);
/*
* We aren't the primary crash CPU. We need to send it
* to a holding pattern to avoid it ending up in the panic
* code.
*/
crash_kexec_secondary(regs);
/*
* No debugger or crash dump registered, print logs then
* panic.
*/
__die("System Reset", regs, SIGABRT);
mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
nmi_panic(regs, "System Reset");
out:
#ifdef CONFIG_PPC_BOOK3S_64
BUG_ON(get_paca()->in_nmi == 0);
if (get_paca()->in_nmi > 1)
nmi_panic(regs, "Unrecoverable nested System Reset");
#endif
/* Must die if the interrupt is not recoverable */
if (!(regs->msr & MSR_RI))
nmi_panic(regs, "Unrecoverable System Reset");
if (!nested)
nmi_exit();
/* What should we do here? We could issue a shutdown or hard reset. */
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Nicholas Piggin | 122 | 69.71% | 4 | 57.14% |
Paul Mackerras | 48 | 27.43% | 2 | 28.57% |
Arnd Bergmann | 5 | 2.86% | 1 | 14.29% |
Total | 175 | 100.00% | 7 | 100.00% |
/*
* I/O accesses can cause machine checks on powermacs.
* Check if the NIP corresponds to the address of a sync
* instruction for which there is an entry in the exception
* table.
* Note that the 601 only takes a machine check on TEA
* (transfer error ack) signal assertion, and does not
* set any of the top 16 bits of SRR1.
* -- paulus.
*/
static inline int check_io_access(struct pt_regs *regs)
{
#ifdef CONFIG_PPC32
unsigned long msr = regs->msr;
const struct exception_table_entry *entry;
unsigned int *nip = (unsigned int *)regs->nip;
if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
&& (entry = search_exception_tables(regs->nip)) != NULL) {
/*
* Check that it's a sync instruction, or somewhere
* in the twi; isync; nop sequence that inb/inw/inl uses.
* As the address is in the exception table
* we should be able to read the instr there.
* For the debug message, we look at the preceding
* load or store.
*/
if (*nip == PPC_INST_NOP)
nip -= 2;
else if (*nip == PPC_INST_ISYNC)
--nip;
if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
unsigned int rb;
--nip;
rb = (*nip >> 11) & 0x1f;
printk(KERN_DEBUG "%s bad port %lx at %p\n",
(*nip & 0x100)? "OUT to": "IN from",
regs->gpr[rb] - _IO_BASE, nip);
regs->msr |= MSR_RI;
regs->nip = extable_fixup(entry);
return 1;
}
}
#endif /* CONFIG_PPC32 */
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 180 | 94.24% | 1 | 20.00% |
Christophe Leroy | 4 | 2.09% | 1 | 20.00% |
Nicholas Piggin | 3 | 1.57% | 1 | 20.00% |
Benjamin Herrenschmidt | 3 | 1.57% | 1 | 20.00% |
Kumar Gala | 1 | 0.52% | 1 | 20.00% |
Total | 191 | 100.00% | 5 | 100.00% |
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
/* On 4xx, the reason for the machine check or program exception
is in the ESR. */
#define get_reason(regs) ((regs)->dsisr)
#define REASON_FP ESR_FP
#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
#define REASON_PRIVILEGED ESR_PPR
#define REASON_TRAP ESR_PTR
/* single-step stuff */
#define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
#define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
#else
/* On non-4xx, the reason for the machine check or program
exception is in the MSR. */
#define get_reason(regs) ((regs)->msr)
#define REASON_TM SRR1_PROGTM
#define REASON_FP SRR1_PROGFPE
#define REASON_ILLEGAL SRR1_PROGILL
#define REASON_PRIVILEGED SRR1_PROGPRIV
#define REASON_TRAP SRR1_PROGTRAP
#define single_stepping(regs) ((regs)->msr & MSR_SE)
#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
#endif
#if defined(CONFIG_E500)
int machine_check_e500mc(struct pt_regs *regs)
{
unsigned long mcsr = mfspr(SPRN_MCSR);
unsigned long pvr = mfspr(SPRN_PVR);
unsigned long reason = mcsr;
int recoverable = 1;
if (reason & MCSR_LD) {
recoverable = fsl_rio_mcheck_exception(regs);
if (recoverable == 1)
goto silent_out;
}
printk("Machine check in kernel mode.\n");
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
printk("Machine Check Signal\n");
if (reason & MCSR_ICPERR) {
printk("Instruction Cache Parity Error\n");
/*
* This is recoverable by invalidating the i-cache.
*/
mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
;
/*
* This will generally be accompanied by an instruction
* fetch error report -- only treat MCSR_IF as fatal
* if it wasn't due to an L1 parity error.
*/
reason &= ~MCSR_IF;
}
if (reason & MCSR_DCPERR_MC) {
printk("Data Cache Parity Error\n");
/*
* In write shadow mode we auto-recover from the error, but it
* may still get logged and cause a machine check. We should
* only treat the non-write shadow case as non-recoverable.
*/
/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
* is not implemented but L1 data cache always runs in write
* shadow mode. Hence on data cache parity errors HW will
* automatically invalidate the L1 Data Cache.
*/
if (PVR_VER(pvr) != PVR_VER_E6500) {
if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
recoverable = 0;
}
}
if (reason & MCSR_L2MMU_MHIT) {
printk("Hit on multiple TLB entries\n");
recoverable = 0;
}
if (reason & MCSR_NMI)
printk("Non-maskable interrupt\n");
if (reason & MCSR_IF) {
printk("Instruction Fetch Error Report\n");
recoverable = 0;
}
if (reason & MCSR_LD) {
printk("Load Error Report\n");
recoverable = 0;
}
if (reason & MCSR_ST) {
printk("Store Error Report\n");
recoverable = 0;
}
if (reason & MCSR_LDG) {
printk("Guarded Load Error Report\n");
recoverable = 0;
}
if (reason & MCSR_TLBSYNC)
printk("Simultaneous tlbsync operations\n");
if (reason & MCSR_BSL2_ERR) {
printk("Level 2 Cache Error\n");
recoverable = 0;
}
if (reason & MCSR_MAV) {
u64 addr;
addr = mfspr(SPRN_MCAR);
addr |= (u64)mfspr(SPRN_MCARU) << 32;
printk("Machine Check %s Address: %#llx\n",
reason & MCSR_MEA ? "Effective" : "Physical", addr);
}
silent_out:
mtspr(SPRN_MCSR, mcsr);
return mfspr(SPRN_MCSR) == 0 && recoverable;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Scott Wood | 299 | 83.52% | 2 | 40.00% |
Shaohui Xie | 25 | 6.98% | 1 | 20.00% |
Matt Weber | 21 | 5.87% | 1 | 20.00% |
Kumar Gala | 13 | 3.63% | 1 | 20.00% |
Total | 358 | 100.00% | 5 | 100.00% |
int machine_check_e500(struct pt_regs *regs)
{
unsigned long reason = mfspr(SPRN_MCSR);
if (reason & MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
if (fsl_pci_mcheck_exception(regs))
return 1;
}
printk("Machine check in kernel mode.\n");
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
printk("Machine Check Signal\n");
if (reason & MCSR_ICPERR)
printk("Instruction Cache Parity Error\n");
if (reason & MCSR_DCP_PERR)
printk("Data Cache Push Parity Error\n");
if (reason & MCSR_DCPERR)
printk("Data Cache Parity Error\n");
if (reason & MCSR_BUS_IAERR)
printk("Bus - Instruction Address Error\n");
if (reason & MCSR_BUS_RAERR)
printk("Bus - Read Address Error\n");
if (reason & MCSR_BUS_WAERR)
printk("Bus - Write Address Error\n");
if (reason & MCSR_BUS_IBERR)
printk("Bus - Instruction Data Error\n");
if (reason & MCSR_BUS_RBERR)
printk("Bus - Read Data Bus Error\n");
if (reason & MCSR_BUS_WBERR)
printk("Bus - Write Data Bus Error\n");
if (reason & MCSR_BUS_IPERR)
printk("Bus - Instruction Parity Error\n");
if (reason & MCSR_BUS_RPERR)
printk("Bus - Read Parity Error\n");
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 143 | 73.71% | 1 | 16.67% |
Benjamin Herrenschmidt | 20 | 10.31% | 1 | 16.67% |
Shaohui Xie | 18 | 9.28% | 1 | 16.67% |
Jia Hongtao | 10 | 5.15% | 1 | 16.67% |
Michael Ellerman | 2 | 1.03% | 1 | 16.67% |
Wladislav Wiebe | 1 | 0.52% | 1 | 16.67% |
Total | 194 | 100.00% | 6 | 100.00% |
int machine_check_generic(struct pt_regs *regs)
{
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Kumar Gala | 13 | 100.00% | 1 | 100.00% |
Total | 13 | 100.00% | 1 | 100.00% |
#elif defined(CONFIG_E200)
int machine_check_e200(struct pt_regs *regs)
{
unsigned long reason = mfspr(SPRN_MCSR);
printk("Machine check in kernel mode.\n");
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
printk("Machine Check Signal\n");
if (reason & MCSR_CP_PERR)
printk("Cache Push Parity Error\n");
if (reason & MCSR_CPERR)
printk("Cache Parity Error\n");
if (reason & MCSR_EXCP_ERR)
printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
if (reason & MCSR_BUS_IRERR)
printk("Bus - Read Bus Error on instruction fetch\n");
if (reason & MCSR_BUS_DRERR)
printk("Bus - Read Bus Error on data load\n");
if (reason & MCSR_BUS_WRERR)
printk("Bus - Write Bus Error on buffered store or cache line push\n");
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 89 | 80.18% | 1 | 33.33% |
Benjamin Herrenschmidt | 20 | 18.02% | 1 | 33.33% |
Michael Ellerman | 2 | 1.80% | 1 | 33.33% |
Total | 111 | 100.00% | 3 | 100.00% |
#elif defined(CONFIG_PPC32)
int machine_check_generic(struct pt_regs *regs)
{
unsigned long reason = regs->msr;
printk("Machine check in kernel mode.\n");
printk("Caused by (from SRR1=%lx): ", reason);
switch (reason & 0x601F0000) {
case 0x80000:
printk("Machine check signal\n");
break;
case 0: /* for 601 */
case 0x40000:
case 0x140000: /* 7450 MSS error and TEA */
printk("Transfer error ack signal\n");
break;
case 0x20000:
printk("Data parity error signal\n");
break;
case 0x10000:
printk("Address parity error signal\n");
break;
case 0x20000000:
printk("L1 Data Cache error\n");
break;
case 0x40000000:
printk("L1 Instruction Cache error\n");
break;
case 0x00100000:
printk("L2 data cache parity error\n");
break;
default:
printk("Unknown values in msr\n");
}
return 0;
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 97 | 82.20% | 1 | 25.00% |
Benjamin Herrenschmidt | 15 | 12.71% | 1 | 25.00% |
Olof Johansson | 4 | 3.39% | 1 | 25.00% |
Michael Ellerman | 2 | 1.69% | 1 | 25.00% |
Total | 118 | 100.00% | 4 | 100.00% |
#endif /* everything else */
void machine_check_exception(struct pt_regs *regs)
{
int recover = 0;
bool nested = in_nmi();
if (!nested)
nmi_enter();
/* 64s accounts the mce in machine_check_early when in HVMODE */
if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
__this_cpu_inc(irq_stat.mce_exceptions);
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
/* See if any machine dependent calls. In theory, we would want
* to call the CPU first, and call the ppc_md. one if the CPU
* one returns a positive number. However there is existing code
* that assumes the board gets a first chance, so let's keep it
* that way for now and fix things later. --BenH.
*/
if (ppc_md.machine_check_exception)
recover = ppc_md.machine_check_exception(regs);
else if (cur_cpu_spec->machine_check)
recover = cur_cpu_spec->machine_check(regs);
if (recover > 0)
goto bail;
if (debugger_fault_handler(regs))
goto bail;
if (check_io_access(regs))
goto bail;
die("Machine check", regs, SIGBUS);
/* Must die if the interrupt is not recoverable */
if (!(regs->msr & MSR_RI))
nmi_panic(regs, "Unrecoverable Machine check");
bail:
if (!nested)
nmi_exit();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Olof Johansson | 53 | 33.76% | 1 | 11.11% |
Nicholas Piggin | 39 | 24.84% | 2 | 22.22% |
Paul Mackerras | 26 | 16.56% | 1 | 11.11% |
Benjamin Herrenschmidt | 13 | 8.28% | 1 | 11.11% |
Li Zhong | 12 | 7.64% | 1 | 11.11% |
Mahesh Salgaonkar | 7 | 4.46% | 1 | 11.11% |
Anton Blanchard | 5 | 3.18% | 1 | 11.11% |
Christoph Lameter | 2 | 1.27% | 1 | 11.11% |
Total | 157 | 100.00% | 9 | 100.00% |
void SMIException(struct pt_regs *regs)
{
die("System Management Interrupt", regs, SIGABRT);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 19 | 100.00% | 1 | 100.00% |
Total | 19 | 100.00% | 1 | 100.00% |
void handle_hmi_exception(struct pt_regs *regs)
{
struct pt_regs *old_regs;
old_regs = set_irq_regs(regs);
irq_enter();
if (ppc_md.handle_hmi_exception)
ppc_md.handle_hmi_exception(regs);
irq_exit();
set_irq_regs(old_regs);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Mahesh Salgaonkar | 46 | 100.00% | 1 | 100.00% |
Total | 46 | 100.00% | 1 | 100.00% |
void unknown_exception(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(SIGTRAP, regs, 0, 0);
exception_exit(prev_state);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 37 | 74.00% | 1 | 33.33% |
Li Zhong | 12 | 24.00% | 1 | 33.33% |
Stephen Rothwell | 1 | 2.00% | 1 | 33.33% |
Total | 50 | 100.00% | 3 | 100.00% |
void instruction_breakpoint_exception(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
5, SIGTRAP) == NOTIFY_STOP)
goto bail;
if (debugger_iabr_match(regs))
goto bail;
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
bail:
exception_exit(prev_state);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 48 | 69.57% | 1 | 33.33% |
Li Zhong | 20 | 28.99% | 1 | 33.33% |
Stephen Rothwell | 1 | 1.45% | 1 | 33.33% |
Total | 69 | 100.00% | 3 | 100.00% |
void RunModeException(struct pt_regs *regs)
{
_exception(SIGTRAP, regs, 0, 0);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 21 | 100.00% | 1 | 100.00% |
Total | 21 | 100.00% | 1 | 100.00% |
void single_step_exception(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
clear_single_step(regs);
if (kprobe_post_handler(regs))
return;
if (notify_die(DIE_SSTEP, "single_step", regs, 5,
5, SIGTRAP) == NOTIFY_STOP)
goto bail;
if (debugger_sstep(regs))
goto bail;
_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
bail:
exception_exit(prev_state);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 50 | 60.98% | 1 | 20.00% |
Li Zhong | 20 | 24.39% | 1 | 20.00% |
Naveen N. Rao | 8 | 9.76% | 1 | 20.00% |
K.Prasad | 3 | 3.66% | 1 | 20.00% |
Stephen Rothwell | 1 | 1.22% | 1 | 20.00% |
Total | 82 | 100.00% | 5 | 100.00% |
NOKPROBE_SYMBOL(single_step_exception);
/*
* After we have successfully emulated an instruction, we have to
* check if the instruction was being single-stepped, and if so,
* pretend we got a single-step exception. This was pointed out
* by Kumar Gala. -- paulus
*/
static void emulate_single_step(struct pt_regs *regs)
{
if (single_stepping(regs))
single_step_exception(regs);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Paul Mackerras | 22 | 95.65% | 1 | 50.00% |
K.Prasad | 1 | 4.35% | 1 | 50.00% |
Total | 23 | 100.00% | 2 | 100.00% |
static inline int __parse_fpscr(unsigned long fpscr)
{
int ret = 0;