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Release 4.14 arch/powerpc/perf/imc-pmu.c

/*
 * In-Memory Collection (IMC) Performance Monitor counter support.
 *
 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
 *           (C) 2017 Anju T Sudhakar, IBM Corporation.
 *           (C) 2017 Hemant K Shaw, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or later version.
 */
#include <linux/perf_event.h>
#include <linux/slab.h>
#include <asm/opal.h>
#include <asm/imc-pmu.h>
#include <asm/cputhreads.h>
#include <asm/smp.h>
#include <linux/string.h>

/* Nest IMC data structures and variables */

/*
 * Used to avoid races in counting the nest-pmu units during hotplug
 * register and unregister
 */
static DEFINE_MUTEX(nest_init_lock);
static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);

static struct imc_pmu *per_nest_pmu_arr[IMC_MAX_PMUS];

static cpumask_t nest_imc_cpumask;

struct imc_pmu_ref *nest_imc_refc;

static int nest_pmus;

/* Core IMC data structures and variables */


static cpumask_t core_imc_cpumask;

struct imc_pmu_ref *core_imc_refc;

static struct imc_pmu *core_imc_pmu;

/* Thread IMC data structures and variables */

static DEFINE_PER_CPU(u64 *, thread_imc_mem);

static struct imc_pmu *thread_imc_pmu;

static int thread_imc_mem_size;


struct imc_pmu *imc_event_to_pmu(struct perf_event *event) { return container_of(event->pmu, struct imc_pmu, pmu); }

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PMU_FORMAT_ATTR(event, "config:0-40"); PMU_FORMAT_ATTR(offset, "config:0-31"); PMU_FORMAT_ATTR(rvalue, "config:32"); PMU_FORMAT_ATTR(mode, "config:33-40"); static struct attribute *imc_format_attrs[] = { &format_attr_event.attr, &format_attr_offset.attr, &format_attr_rvalue.attr, &format_attr_mode.attr, NULL, }; static struct attribute_group imc_format_group = { .name = "format", .attrs = imc_format_attrs, }; /* Get the cpumask printed to a buffer "buf" */
static ssize_t imc_pmu_cpumask_get_attr(struct device *dev, struct device_attribute *attr, char *buf) { struct pmu *pmu = dev_get_drvdata(dev); struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu); cpumask_t *active_mask; switch(imc_pmu->domain){ case IMC_DOMAIN_NEST: active_mask = &nest_imc_cpumask; break; case IMC_DOMAIN_CORE: active_mask = &core_imc_cpumask; break; default: return 0; } return cpumap_print_to_pagebuf(true, buf, active_mask); }

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static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL); static struct attribute *imc_pmu_cpumask_attrs[] = { &dev_attr_cpumask.attr, NULL, }; static struct attribute_group imc_pmu_cpumask_attr_group = { .attrs = imc_pmu_cpumask_attrs, }; /* device_str_attr_create : Populate event "name" and string "str" in attribute */
static struct attribute *device_str_attr_create(const char *name, const char *str) { struct perf_pmu_events_attr *attr; attr = kzalloc(sizeof(*attr), GFP_KERNEL); if (!attr) return NULL; sysfs_attr_init(&attr->attr.attr); attr->event_str = str; attr->attr.attr.name = name; attr->attr.attr.mode = 0444; attr->attr.show = perf_event_sysfs_show; return &attr->attr.attr; }

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struct imc_events *imc_parse_event(struct device_node *np, const char *scale, const char *unit, const char *prefix, u32 base) { struct imc_events *event; const char *s; u32 reg; event = kzalloc(sizeof(struct imc_events), GFP_KERNEL); if (!event) return NULL; if (of_property_read_u32(np, "reg", &reg)) goto error; /* Add the base_reg value to the "reg" */ event->value = base + reg; if (of_property_read_string(np, "event-name", &s)) goto error; event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s); if (!event->name) goto error; if (of_property_read_string(np, "scale", &s)) s = scale; if (s) { event->scale = kstrdup(s, GFP_KERNEL); if (!event->scale) goto error; } if (of_property_read_string(np, "unit", &s)) s = unit; if (s) { event->unit = kstrdup(s, GFP_KERNEL); if (!event->unit) goto error; } return event; error: kfree(event->unit); kfree(event->scale); kfree(event->name); kfree(event); return NULL; }

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/* * update_events_in_group: Update the "events" information in an attr_group * and assign the attr_group to the pmu "pmu". */
static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu) { struct attribute_group *attr_group; struct attribute **attrs, *dev_str; struct device_node *np, *pmu_events; struct imc_events *ev; u32 handle, base_reg; int i=0, j=0, ct; const char *prefix, *g_scale, *g_unit; const char *ev_val_str, *ev_scale_str, *ev_unit_str; if (!of_property_read_u32(node, "events", &handle)) pmu_events = of_find_node_by_phandle(handle); else return 0; /* Did not find any node with a given phandle */ if (!pmu_events) return 0; /* Get a count of number of child nodes */ ct = of_get_child_count(pmu_events); /* Get the event prefix */ if (of_property_read_string(node, "events-prefix", &prefix)) return 0; /* Get a global unit and scale data if available */ if (of_property_read_string(node, "scale", &g_scale)) g_scale = NULL; if (of_property_read_string(node, "unit", &g_unit)) g_unit = NULL; /* "reg" property gives out the base offset of the counters data */ of_property_read_u32(node, "reg", &base_reg); /* Allocate memory for the events */ pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL); if (!pmu->events) return -ENOMEM; ct = 0; /* Parse the events and update the struct */ for_each_child_of_node(pmu_events, np) { ev = imc_parse_event(np, g_scale, g_unit, prefix, base_reg); if (ev) pmu->events[ct++] = ev; } /* Allocate memory for attribute group */ attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL); if (!attr_group) return -ENOMEM; /* * Allocate memory for attributes. * Since we have count of events for this pmu, we also allocate * memory for the scale and unit attribute for now. * "ct" has the total event structs added from the events-parent node. * So allocate three times the "ct" (this includes event, event_scale and * event_unit). */ attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL); if (!attrs) { kfree(attr_group); kfree(pmu->events); return -ENOMEM; } attr_group->name = "events"; attr_group->attrs = attrs; do { ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i]->value); dev_str = device_str_attr_create(pmu->events[i]->name, ev_val_str); if (!dev_str) continue; attrs[j++] = dev_str; if (pmu->events[i]->scale) { ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale",pmu->events[i]->name); dev_str = device_str_attr_create(ev_scale_str, pmu->events[i]->scale); if (!dev_str) continue; attrs[j++] = dev_str; } if (pmu->events[i]->unit) { ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit",pmu->events[i]->name); dev_str = device_str_attr_create(ev_unit_str, pmu->events[i]->unit); if (!dev_str) continue; attrs[j++] = dev_str; } } while (++i < ct); /* Save the event attribute */ pmu->attr_groups[IMC_EVENT_ATTR] = attr_group; kfree(pmu->events); return 0; }

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/* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
static struct imc_pmu_ref *get_nest_pmu_ref(int cpu) { return per_cpu(local_nest_imc_refc, cpu); }

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static void nest_change_cpu_context(int old_cpu, int new_cpu) { struct imc_pmu **pn = per_nest_pmu_arr; int i; if (old_cpu < 0 || new_cpu < 0) return; for (i = 0; *pn && i < IMC_MAX_PMUS; i++, pn++) perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu); }

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static int ppc_nest_imc_cpu_offline(unsigned int cpu) { int nid, target = -1; const struct cpumask *l_cpumask; struct imc_pmu_ref *ref; /* * Check in the designated list for this cpu. Dont bother * if not one of them. */ if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask)) return 0; /* * Now that this cpu is one of the designated, * find a next cpu a) which is online and b) in same chip. */ nid = cpu_to_node(cpu); l_cpumask = cpumask_of_node(nid); target = cpumask_any_but(l_cpumask, cpu); /* * Update the cpumask with the target cpu and * migrate the context if needed */ if (target >= 0 && target < nr_cpu_ids) { cpumask_set_cpu(target, &nest_imc_cpumask); nest_change_cpu_context(cpu, target); } else { opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, get_hard_smp_processor_id(cpu)); /* * If this is the last cpu in this chip then, skip the reference * count mutex lock and make the reference count on this chip zero. */ ref = get_nest_pmu_ref(cpu); if (!ref) return -EINVAL; ref->refc = 0; } return 0; }

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static int ppc_nest_imc_cpu_online(unsigned int cpu) { const struct cpumask *l_cpumask; static struct cpumask tmp_mask; int res; /* Get the cpumask of this node */ l_cpumask = cpumask_of_node(cpu_to_node(cpu)); /* * If this is not the first online CPU on this node, then * just return. */ if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask)) return 0; /* * If this is the first online cpu on this node * disable the nest counters by making an OPAL call. */ res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, get_hard_smp_processor_id(cpu)); if (res) return res; /* Make this CPU the designated target for counter collection */ cpumask_set_cpu(cpu, &nest_imc_cpumask); return 0; }

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static int nest_pmu_cpumask_init(void) { return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE, "perf/powerpc/imc:online", ppc_nest_imc_cpu_online, ppc_nest_imc_cpu_offline); }

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static void nest_imc_counters_release(struct perf_event *event) { int rc, node_id; struct imc_pmu_ref *ref; if (event->cpu < 0) return; node_id = cpu_to_node(event->cpu); /* * See if we need to disable the nest PMU. * If no events are currently in use, then we have to take a * mutex to ensure that we don't race with another task doing * enable or disable the nest counters. */ ref = get_nest_pmu_ref(event->cpu); if (!ref) return; /* Take the mutex lock for this node and then decrement the reference count */ mutex_lock(&ref->lock); if (ref->refc == 0) { /* * The scenario where this is true is, when perf session is * started, followed by offlining of all cpus in a given node. * * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline() * function set the ref->count to zero, if the cpu which is * about to offline is the last cpu in a given node and make * an OPAL call to disable the engine in that node. * */ mutex_unlock(&ref->lock); return; } ref->refc--; if (ref->refc == 0) { rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, get_hard_smp_processor_id(event->cpu)); if (rc) { mutex_unlock(&ref->lock); pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id); return; } } else if (ref->refc < 0) { WARN(1, "nest-imc: Invalid event reference count\n"); ref->refc = 0; } mutex_unlock(&ref->lock); }

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static int nest_imc_event_init(struct perf_event *event) { int chip_id, rc, node_id; u32 l_config, config = event->attr.config; struct imc_mem_info *pcni; struct imc_pmu *pmu; struct imc_pmu_ref *ref; bool flag = false; if (event->attr.type != event->pmu->type) return -ENOENT; /* Sampling not supported */ if (event->hw.sample_period) return -EINVAL; /* unsupported modes and filters */ if (event->attr.exclude_user || event->attr.exclude_kernel || event->attr.exclude_hv || event->attr.exclude_idle || event->attr.exclude_host || event->attr.exclude_guest) return -EINVAL; if (event->cpu < 0) return -EINVAL; pmu = imc_event_to_pmu(event); /* Sanity check for config (event offset) */ if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size) return -EINVAL; /* * Nest HW counter memory resides in a per-chip reserve-memory (HOMER). * Get the base memory addresss for this cpu. */ chip_id = topology_physical_package_id(event->cpu); pcni = pmu->mem_info; do { if (pcni->id == chip_id) { flag = true; break; } pcni++; } while (pcni); if (!flag) return -ENODEV; /* * Add the event offset to the base address. */ l_config = config & IMC_EVENT_OFFSET_MASK; event->hw.event_base = (u64)pcni->vbase + l_config; node_id = cpu_to_node(event->cpu); /* * Get the imc_pmu_ref struct for this node. * Take the mutex lock and then increment the count of nest pmu events * inited. */ ref = get_nest_pmu_ref(event->cpu); if (!ref) return -EINVAL; mutex_lock(&ref->lock); if (ref->refc == 0) { rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST, get_hard_smp_processor_id(event->cpu)); if (rc) { mutex_unlock(&ref->lock); pr_err("nest-imc: Unable to start the counters for node %d\n", node_id); return rc; } } ++ref->refc; mutex_unlock(&ref->lock); event->destroy = nest_imc_counters_release; return 0; }

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/* * core_imc_mem_init : Initializes memory for the current core. * * Uses alloc_pages_node() and uses the returned address as an argument to * an opal call to configure the pdbar. The address sent as an argument is * converted to physical address before the opal call is made. This is the * base address at which the core imc counters are populated. */
static int core_imc_mem_init(int cpu, int size) { int phys_id, rc = 0, core_id = (cpu / threads_per_core); struct imc_mem_info *mem_info; /* * alloc_pages_node() will allocate memory for core in the * local node only. */ phys_id = topology_physical_package_id(cpu); mem_info = &core_imc_pmu->mem_info[core_id]; mem_info->id = core_id; /* We need only vbase for core counters */ mem_info->vbase = page_address(alloc_pages_node(phys_id, GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | __GFP_NOWARN, get_order(size))); if (!mem_info->vbase) return -ENOMEM; /* Init the mutex */ core_imc_refc[core_id].id = core_id; mutex_init(&core_imc_refc[core_id].lock); rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE, __pa((void *)mem_info->vbase), get_hard_smp_processor_id(cpu)); if (rc) { free_pages((u64)mem_info->vbase, get_order(size)); mem_info->vbase = NULL; } return rc; }

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static bool is_core_imc_mem_inited(int cpu) { struct imc_mem_info *mem_info; int core_id = (cpu / threads_per_core); mem_info = &core_imc_pmu->mem_info[core_id]; if (!mem_info->vbase) return false; return true; }

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static int ppc_core_imc_cpu_online(unsigned int cpu) { const struct cpumask *l_cpumask; static struct cpumask tmp_mask; int ret = 0; /* Get the cpumask for this core */ l_cpumask = cpu_sibling_mask(cpu); /* If a cpu for this core is already set, then, don't do anything */ if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask)) return 0; if (!is_core_imc_mem_inited(cpu)) { ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size); if (ret) { pr_info("core_imc memory allocation for cpu %d failed\n", cpu); return ret; } } /* set the cpu in the mask */ cpumask_set_cpu(cpu, &core_imc_cpumask); return 0; }

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static int ppc_core_imc_cpu_offline(unsigned int cpu) { unsigned int ncpu, core_id; struct imc_pmu_ref *ref; /* * clear this cpu out of the mask, if not present in the mask, * don't bother doing anything. */ if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask)) return 0; /* * Check whether core_imc is registered. We could end up here * if the cpuhotplug callback registration fails. i.e, callback * invokes the offline path for all sucessfully registered cpus. * At this stage, core_imc pmu will not be registered and we * should return here. * * We return with a zero since this is not an offline failure. * And cpuhp_setup_state() returns the actual failure reason * to the caller, which inturn will call the cleanup routine. */ if (!core_imc_pmu->pmu.event_init) return 0; /* Find any online cpu in that core except the current "cpu" */ ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu); if (ncpu >= 0 && ncpu < nr_cpu_ids) { cpumask_set_cpu(ncpu, &core_imc_cpumask); perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu); } else { /* * If this is the last cpu in this core then, skip taking refernce * count mutex lock for this core and directly zero "refc" for * this core. */ opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, get_hard_smp_processor_id(cpu)); core_id = cpu / threads_per_core; ref = &core_imc_refc[core_id]; if (!ref) return -EINVAL; ref->refc = 0; } return 0; }

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static int core_imc_pmu_cpumask_init(void) { return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE, "perf/powerpc/imc_core:online", ppc_core_imc_cpu_online, ppc_core_imc_cpu_offline); }

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static void core_imc_counters_release(struct perf_event *event) { int rc, core_id; struct imc_pmu_ref *ref; if (event->cpu < 0) return; /* * See if we need to disable the IMC PMU. * If no events are currently in use, then we have to take a * mutex to ensure that we don't race with another task doing * enable or disable the core counters. */ core_id = event->cpu / threads_per_core; /* Take the mutex lock and decrement the refernce count for this core */ ref = &core_imc_refc[core_id]; if (!ref) return; mutex_lock(&ref->lock); if (ref->refc == 0) { /* * The scenario where this is true is, when perf session is * started, followed by offlining of all cpus in a given core. * * In the cpuhotplug offline path, ppc_core_imc_cpu_offline() * function set the ref->count to zero, if the cpu which is * about to offline is the last cpu in a given core and make * an OPAL call to disable the engine in that core. * */ mutex_unlock(&ref->lock); return; } ref->refc--; if (ref->refc == 0) { rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, get_hard_smp_processor_id(event->cpu)); if (rc) { mutex_unlock(&ref->lock); pr_err("IMC: Unable to stop the counters for core %d\n", core_id); return; } } else if (ref->refc < 0) { WARN(1, "core-imc: Invalid event reference count\n"); ref->refc = 0; } mutex_unlock(&ref->lock); }

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static int core_imc_event_init(struct perf_event *event) { int core_id, rc; u64 config = event->attr.config; struct imc_mem_info *pcmi; struct imc_pmu *pmu; struct imc_pmu_ref *ref; if (event->attr.type != event->pmu->type) return -ENOENT; /* Sampling not supported */ if (event->hw.sample_period) return -EINVAL; /* unsupported modes and filters */ if (event->attr.exclude_user || event->attr.exclude_kernel || event->attr.exclude_hv || event->attr.exclude_idle || event->attr.exclude_host || event->attr.exclude_guest) return -EINVAL; if (event->cpu < 0) return -EINVAL; event->hw.idx = -1; pmu = imc_event_to_pmu(event); /* Sanity check for config (event offset) */ if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)) return -EINVAL; if (!is_core_imc_mem_inited(event->cpu)) return -ENODEV; core_id = event->cpu / threads_per_core; pcmi = &core_imc_pmu->mem_info[core_id]; if ((!pcmi->vbase)) return -ENODEV; /* Get the core_imc mutex for this core */ ref = &core_imc_refc[core_id]; if (!ref) return -EINVAL; /* * Core pmu units are enabled only when it is used. * See if this is triggered for the first time. * If yes, take the mutex lock and enable the core counters. * If not, just increment the count in core_imc_refc struct. */ mutex_lock(&ref->lock); if (ref->refc == 0) { rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE, get_hard_smp_processor_id(event->cpu)); if (rc) { mutex_unlock(&ref->lock); pr_err("core-imc: Unable to start the counters for core %d\n", core_id); return rc; } } ++ref->refc; mutex_unlock(&ref->lock); event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); event->destroy = core_imc_counters_release; return 0; }

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/* * Allocates a page of memory for each of the online cpus, and write the * physical base address of that page to the LDBAR for that cpu. * * LDBAR Register Layout: * * 0 4 8 12 16 20 24 28 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | * | | [ ] [ Counter Address [8:50] * | * Mode | * | * PB Scope * * Enable/Disable * * 32 36 40 44 48 52 56 60 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | * Counter Address [8:50] ] * */
static int thread_imc_mem_alloc(int cpu_id, int size) { u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id); int phys_id = topology_physical_package_id(cpu_id); if (!local_mem) { /* * This case could happen only once at start, since we dont * free the memory in cpu offline path. */ local_mem = page_address(alloc_pages_node(phys_id, GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | __GFP_NOWARN, get_order(size))); if (!local_mem) return -ENOMEM; per_cpu(thread_imc_mem, cpu_id) = local_mem; } ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE; mtspr(SPRN_LDBAR, ldbar_value); return 0; }

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static int ppc_thread_imc_cpu_online(unsigned int cpu) { return thread_imc_mem_alloc(cpu, thread_imc_mem_size); }

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static int ppc_thread_imc_cpu_offline(unsigned int cpu) { mtspr(SPRN_LDBAR, 0); return 0; }

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static int