Release 4.14 arch/powerpc/sysdev/xilinx_intc.c
/*
* Interrupt controller driver for Xilinx Virtex FPGAs
*
* Copyright (C) 2007 Secret Lab Technologies Ltd.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
/*
* This is a driver for the interrupt controller typically found in
* Xilinx Virtex FPGA designs.
*
* The interrupt sense levels are hard coded into the FPGA design with
* typically a 1:1 relationship between irq lines and devices (no shared
* irq lines). Therefore, this driver does not attempt to handle edge
* and level interrupts differently.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/i8259.h>
#include <asm/irq.h>
#include <linux/irqchip.h>
#if defined(CONFIG_PPC_I8259)
/*
* Support code for cascading to 8259 interrupt controllers
*/
static void xilinx_i8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq)
generic_handle_irq(cascade_irq);
/* Let xilinx_intc end the interrupt */
chip->irq_unmask(&desc->irq_data);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Grant C. Likely | 33 | 68.75% | 1 | 33.33% |
Lennert Buytenhek | 14 | 29.17% | 1 | 33.33% |
Thomas Gleixner | 1 | 2.08% | 1 | 33.33% |
Total | 48 | 100.00% | 3 | 100.00% |
static void __init xilinx_i8259_setup_cascade(void)
{
struct device_node *cascade_node;
int cascade_irq;
/* Initialize i8259 controller */
cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
if (!cascade_node)
return;
cascade_irq = irq_of_parse_and_map(cascade_node, 0);
if (!cascade_irq) {
pr_err("virtex_ml510: Failed to map cascade interrupt\n");
goto out;
}
i8259_init(cascade_node, 0);
irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
/* This looks like a dirty hack to me --gcl */
outb(0xc0, 0x4d0);
outb(0xc0, 0x4d1);
out:
of_node_put(cascade_node);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Grant C. Likely | 71 | 73.96% | 2 | 40.00% |
Roderick Colenbrander | 16 | 16.67% | 1 | 20.00% |
Stephen Neuendorffer | 8 | 8.33% | 1 | 20.00% |
Thomas Gleixner | 1 | 1.04% | 1 | 20.00% |
Total | 96 | 100.00% | 5 | 100.00% |
#else
static inline void xilinx_i8259_setup_cascade(void) { return; }
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Grant C. Likely | 10 | 100.00% | 1 | 100.00% |
Total | 10 | 100.00% | 1 | 100.00% |
#endif /* defined(CONFIG_PPC_I8259) */
/*
* Initialize master Xilinx interrupt controller
*/
void __init xilinx_intc_init_tree(void)
{
irqchip_init();
xilinx_i8259_setup_cascade();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Grant C. Likely | 12 | 85.71% | 2 | 66.67% |
Zubair Lutfullah Kakakhel | 2 | 14.29% | 1 | 33.33% |
Total | 14 | 100.00% | 3 | 100.00% |
Overall Contributors
Person | Tokens | Prop | Commits | CommitProp |
Grant C. Likely | 165 | 76.39% | 2 | 22.22% |
Roderick Colenbrander | 16 | 7.41% | 1 | 11.11% |
Lennert Buytenhek | 14 | 6.48% | 1 | 11.11% |
Stephen Neuendorffer | 8 | 3.70% | 1 | 11.11% |
Rob Herring | 6 | 2.78% | 2 | 22.22% |
Zubair Lutfullah Kakakhel | 5 | 2.31% | 1 | 11.11% |
Thomas Gleixner | 2 | 0.93% | 1 | 11.11% |
Total | 216 | 100.00% | 9 | 100.00% |
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