cregit-Linux how code gets into the kernel

Release 4.14 arch/x86/kernel/cpu/amd.c

Directory: arch/x86/kernel/cpu
#include <linux/export.h>
#include <linux/bitops.h>
#include <linux/elf.h>
#include <linux/mm.h>

#include <linux/io.h>
#include <linux/sched.h>
#include <linux/sched/clock.h>
#include <linux/random.h>
#include <asm/processor.h>
#include <asm/apic.h>
#include <asm/cpu.h>
#include <asm/smp.h>
#include <asm/pci-direct.h>
#include <asm/delay.h>

#ifdef CONFIG_X86_64
# include <asm/mmconfig.h>
# include <asm/set_memory.h>
#endif

#include "cpu.h"


static const int amd_erratum_383[];

static const int amd_erratum_400[];
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);

/*
 * nodes_per_socket: Stores the number of nodes per socket.
 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
 * Node Identifiers[10:8]
 */

static u32 nodes_per_socket = 1;




static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
{
	u32 gprs[8] = { 0 };
	int err;

	WARN_ONCE((boot_cpu_data.x86 != 0xf),
		  "%s should only be used on K8!\n", __func__);

	gprs[1] = msr;
	gprs[7] = 0x9c5a203a;

	err = rdmsr_safe_regs(gprs);

	*p = gprs[0] | ((u64)gprs[2] << 32);

	return err;
}


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static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
{
	u32 gprs[8] = { 0 };

	WARN_ONCE((boot_cpu_data.x86 != 0xf),
		  "%s should only be used on K8!\n", __func__);

	gprs[0] = (u32)val;
	gprs[1] = msr;
	gprs[2] = val >> 32;
	gprs[7] = 0x9c5a203a;

	return wrmsr_safe_regs(gprs);
}


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/*
 *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *      misexecution of code under Linux. Owners of such processors should
 *      contact AMD for precise details and a CPU swap.
 *
 *      See     http://www.multimania.com/poulot/k6bug.html
 *      and     section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
 *              (Publication # 21266  Issue Date: August 1998)
 *
 *      The following test is erm.. interesting. AMD neglected to up
 *      the chip setting when fixing the bug but they also tweaked some
 *      performance at the same time..
 */

extern __visible void vide(void);
__asm__(".globl vide\n"
        ".type vide, @function\n"
        ".align 4\n"
        "vide: ret\n");




static void init_amd_k5(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
/*
 * General Systems BIOSen alias the cpu frequency registers
 * of the Elan at 0x000df000. Unfortunately, one of the Linux
 * drivers subsequently pokes it, and changes the CPU speed.
 * Workaround : Remove the unneeded alias.
 */

#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */

#define CBAR_ENB	(0x80000000)

#define CBAR_KEY	(0X000000CB)
	if (c->x86_model == 9 || c->x86_model == 10) {
		if (inl(CBAR) & CBAR_ENB)
			outl(0 | CBAR_KEY, CBAR);
	}
#endif
}


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static void init_amd_k6(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	u32 l, h;
	int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);

	if (c->x86_model < 6) {
		/* Based on AMD doc 20734R - June 2000 */
		if (c->x86_model == 0) {
			clear_cpu_cap(c, X86_FEATURE_APIC);
			set_cpu_cap(c, X86_FEATURE_PGE);
		}
		return;
	}

	if (c->x86_model == 6 && c->x86_mask == 1) {
		const int K6_BUG_LOOP = 1000000;
		int n;
		void (*f_vide)(void);
		u64 d, d2;

		pr_info("AMD K6 stepping B detected - ");

		/*
                 * It looks like AMD fixed the 2.6.2 bug and improved indirect
                 * calls at the same time.
                 */

		n = K6_BUG_LOOP;
		f_vide = vide;
		OPTIMIZER_HIDE_VAR(f_vide);
		d = rdtsc();
		while (n--)
			f_vide();
		d2 = rdtsc();
		d = d2-d;

		if (d > 20*K6_BUG_LOOP)
			pr_cont("system stability may be impaired when more than 32 MB are used.\n");
		else
			pr_cont("probably OK (after B9730xxxx).\n");
	}

	/* K6 with old style WHCR */
	if (c->x86_model < 8 ||
	   (c->x86_model == 8 && c->x86_mask < 8)) {
		/* We can only write allocate on the low 508Mb */
		if (mbytes > 508)
			mbytes = 508;

		rdmsr(MSR_K6_WHCR, l, h);
		if ((l&0x0000FFFF) == 0) {
			unsigned long flags;
			l = (1<<0)|((mbytes/4)<<1);
			local_irq_save(flags);
			wbinvd();
			wrmsr(MSR_K6_WHCR, l, h);
			local_irq_restore(flags);
			pr_info("Enabling old style K6 write allocation for %d Mb\n",
				mbytes);
		}
		return;
	}

	if ((c->x86_model == 8 && c->x86_mask > 7) ||
	     c->x86_model == 9 || c->x86_model == 13) {
		/* The more serious chips .. */

		if (mbytes > 4092)
			mbytes = 4092;

		rdmsr(MSR_K6_WHCR, l, h);
		if ((l&0xFFFF0000) == 0) {
			unsigned long flags;
			l = ((mbytes>>2)<<22)|(1<<16);
			local_irq_save(flags);
			wbinvd();
			wrmsr(MSR_K6_WHCR, l, h);
			local_irq_restore(flags);
			pr_info("Enabling new style K6 write allocation for %d Mb\n",
				mbytes);
		}

		return;
	}

	if (c->x86_model == 10) {
		/* AMD Geode LX is model 10 */
		/* placeholder for any needed mods */
		return;
	}
#endif
}


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Total406100.00%11100.00%






static void init_amd_k7(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	u32 l, h;

	/*
         * Bit 15 of Athlon specific MSR 15, needs to be 0
         * to enable SSE on Palomino/Morgan/Barton CPU's.
         * If the BIOS didn't enable it already, enable it here.
         */
	if (c->x86_model >= 6 && c->x86_model <= 10) {
		if (!cpu_has(c, X86_FEATURE_XMM)) {
			pr_info("Enabling disabled K7/SSE Support.\n");
			msr_clear_bit(MSR_K7_HWCR, 15);
			set_cpu_cap(c, X86_FEATURE_XMM);
		}
	}

	/*
         * It's been determined by AMD that Athlons since model 8 stepping 1
         * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
         * As per AMD technical note 27212 0.2
         */
	if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
		rdmsr(MSR_K7_CLK_CTL, l, h);
		if ((l & 0xfff00000) != 0x20000000) {
			pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
				l, ((l & 0x000fffff)|0x20000000));
			wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
		}
	}

	set_cpu_cap(c, X86_FEATURE_K7);

	/* calling is from identify_secondary_cpu() ? */
	if (!c->cpu_index)
		return;

	/*
         * Certain Athlons might work (for various values of 'work') in SMP
         * but they are not certified as MP capable.
         */
	/* Athlon 660/661 is valid. */
	if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
	    (c->x86_mask == 1)))
		return;

	/* Duron 670 is valid */
	if ((c->x86_model == 7) && (c->x86_mask == 0))
		return;

	/*
         * Athlon 662, Duron 671, and Athlon >model 7 have capability
         * bit. It's worth noting that the A5 stepping (662) of some
         * Athlon XP's have the MP bit set.
         * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
         * more.
         */
	if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
	    ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
	     (c->x86_model > 7))
		if (cpu_has(c, X86_FEATURE_MP))
			return;

	/* If we get here, not a certified SMP capable AMD system. */

	/*
         * Don't taint if we are running SMP kernel on a single non-MP
         * approved Athlon
         */
	WARN_ONCE(1, "WARNING: This combination of AMD"
		" processors is not suitable for SMP.\n");
	add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
#endif
}


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Total290100.00%12100.00%



#ifdef CONFIG_NUMA
/*
 * To workaround broken NUMA config.  Read the comment in
 * srat_detect_node().
 */



static int nearby_node(int apicid)
{
	int i, node;

	for (i = apicid - 1; i >= 0; i--) {
		node = __apicid_to_node[i];
		if (node != NUMA_NO_NODE && node_online(node))
			return node;
	}
	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
		node = __apicid_to_node[i];
		if (node != NUMA_NO_NODE && node_online(node))
			return node;
	}
	return first_node(node_online_map); /* Shouldn't happen */
}

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#endif

#ifdef CONFIG_SMP
/*
 * Fix up cpu_core_id for pre-F17h systems to be in the
 * [0 .. cores_per_node - 1] range. Not really needed but
 * kept so as not to break existing setups.
 */



static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
{
	u32 cus_per_node;

	if (c->x86 >= 0x17)
		return;

	cus_per_node = c->x86_max_cores / nodes_per_socket;
	c->cpu_core_id %= cus_per_node;
}


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/*
 * Fixup core topology information for
 * (1) AMD multi-node processors
 *     Assumption: Number of cores in each internal node is the same.
 * (2) AMD processors supporting compute units
 */



static void amd_get_topology(struct cpuinfo_x86 *c)
{
	u8 node_id;
	int cpu = smp_processor_id();

	/* get information required for multi-node processors */
	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
		u32 eax, ebx, ecx, edx;

		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);

		node_id  = ecx & 0xff;
		smp_num_siblings = ((ebx >> 8) & 0xff) + 1;

		if (c->x86 == 0x15)
			c->cu_id = ebx & 0xff;

		if (c->x86 >= 0x17) {
			c->cpu_core_id = ebx & 0xff;

			if (smp_num_siblings > 1)
				c->x86_max_cores /= smp_num_siblings;
		}

		/*
                 * We may have multiple LLCs if L3 caches exist, so check if we
                 * have an L3 cache by looking at the L3 cache CPUID leaf.
                 */
		if (cpuid_edx(0x80000006)) {
			if (c->x86 == 0x17) {
				/*
                                 * LLC is at the core complex level.
                                 * Core complex id is ApicId[3].
                                 */
				per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
			} else {
				/* LLC is at the node level. */
				per_cpu(cpu_llc_id, cpu) = node_id;
			}
		}
	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
		u64 value;

		rdmsrl(MSR_FAM10H_NODE_ID, value);
		node_id = value & 7;

		per_cpu(cpu_llc_id, cpu) = node_id;
	} else
		return;

	if (nodes_per_socket > 1) {
		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
		legacy_fixup_core_id(c);
	}
}

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#endif

/*
 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
 * Assumes number of cores is a power of two.
 */



static void amd_detect_cmp(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	unsigned bits;
	int cpu = smp_processor_id();

	bits = c->x86_coreid_bits;
	/* Low order bits define the core id (index of core in socket) */
	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
	/* Convert the initial APIC ID into the socket ID */
	c->phys_proc_id = c->initial_apicid >> bits;
	/* use socket ID also for last level cache */
	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
	amd_get_topology(c);
#endif
}


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u16 amd_get_nb_id(int cpu)
{
	u16 id = 0;
#ifdef CONFIG_SMP
	id = per_cpu(cpu_llc_id, cpu);
#endif
	return id;
}

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EXPORT_SYMBOL_GPL(amd_get_nb_id);




u32 amd_get_nodes_per_socket(void)
{
	return nodes_per_socket;
}

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EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);




static void srat_detect_node(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_NUMA
	int cpu = smp_processor_id();
	int node;
	unsigned apicid = c->apicid;

	node = numa_cpu_node(cpu);
	if (node == NUMA_NO_NODE)
		node = per_cpu(cpu_llc_id, cpu);

	/*
         * On multi-fabric platform (e.g. Numascale NumaChip) a
         * platform-specific handler needs to be called to fixup some
         * IDs of the CPU.
         */
	if (x86_cpuinit.fixup_cpu_id)
		x86_cpuinit.fixup_cpu_id(c, node);

	if (!node_online(node)) {
		/*
                 * Two possibilities here:
                 *
                 * - The CPU is missing memory and no node was created.  In
                 *   that case try picking one from a nearby CPU.
                 *
                 * - The APIC IDs differ from the HyperTransport node IDs
                 *   which the K8 northbridge parsing fills in.  Assume
                 *   they are all increased by a constant offset, but in
                 *   the same order as the HT nodeids.  If that doesn't
                 *   result in a usable node fall back to the path for the
                 *   previous case.
                 *
                 * This workaround operates directly on the mapping between
                 * APIC ID and NUMA node, assuming certain relationship
                 * between APIC ID, HT node ID and NUMA topology.  As going
                 * through CPU mapping may alter the outcome, directly
                 * access __apicid_to_node[].
                 */
		int ht_nodeid = c->initial_apicid;

		if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
			node = __apicid_to_node[ht_nodeid];
		/* Pick a nearby node */
		if (!node_online(node))
			node = nearby_node(apicid);
	}
	numa_set_node(cpu, node);
#endif
}


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Total127100.00%7100.00%






static void early_init_amd_mc(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	unsigned bits, ecx;

	/* Multi core CPU? */
	if (c->extended_cpuid_level < 0x80000008)
		return;

	ecx = cpuid_ecx(0x80000008);

	c->x86_max_cores = (ecx & 0xff) + 1;

	/* CPU telling us the core id bits shift? */
	bits = (ecx >> 12) & 0xF;

	/* Otherwise recompute */
	if (bits == 0) {
		while ((1 << bits) < c->x86_max_cores)
			bits++;
	}

	c->x86_coreid_bits = bits;
#endif
}


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static void bsp_init_amd(struct cpuinfo_x86 *c)
{

#ifdef CONFIG_X86_64
	if (c->x86 >= 0xf) {
		unsigned long long tseg;

		/*
                 * Split up direct mapping around the TSEG SMM area.
                 * Don't do it for gbpages because there seems very little
                 * benefit in doing so.
                 */
		if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
			unsigned long pfn = tseg >> PAGE_SHIFT;

			pr_debug("tseg: %010llx\n", tseg);
			if (pfn_range_is_mapped(pfn, pfn + 1))
				set_memory_4k((unsigned long)__va(tseg), 1);
		}
	}
#endif

	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {

		if (c->x86 > 0x10 ||
		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
			u64 val;

			rdmsrl(MSR_K7_HWCR, val);
			if (!(val & BIT(24)))
				pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
		}
	}

	if (c->x86 == 0x15) {
		unsigned long upperbit;
		u32 cpuid, assoc;

		cpuid	 = cpuid_edx(0x80000005);
		assoc	 = cpuid >> 16 & 0xff;
		upperbit = ((cpuid >> 24) << 10) / assoc;

		va_align.mask	  = (upperbit - 1) & PAGE_MASK;
		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;

		/* A random value per boot for bit slice [12:upper_bit) */
		va_align.bits = get_random_int() & va_align.mask;
	}

	if (cpu_has(c, X86_FEATURE_MWAITX))
		use_mwaitx_delay();

	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
		u32 ecx;

		ecx = cpuid_ecx(0x8000001e);
		nodes_per_socket = ((ecx >> 8) & 7) + 1;
	} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
		u64 value;

		rdmsrl(MSR_FAM10H_NODE_ID, value);
		nodes_per_socket = ((value >> 3) & 7) + 1;
	}
}


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Total307100.00%6100.00%






static void early_init_amd(struct cpuinfo_x86 *c)
{
	u32 dummy;

	early_init_amd_mc(c);

	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);

	/*
         * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
         * with P/T states and does not stop in deep C-states
         */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	}

	/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
	if (c->x86_power & BIT(12))
		set_cpu_cap(c, X86_FEATURE_ACC_POWER);

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
#else
	/*  Set MTRR capability flag if appropriate */
	if (c->x86 == 5)
		if (c->x86_model == 13 || c->x86_model == 9 ||
		    (c->x86_model == 8 && c->x86_mask >= 8))
			set_cpu_cap(c, X86_FEATURE_K6_MTRR);
#endif
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
	/*
         * ApicID can always be treated as an 8-bit value for AMD APIC versions
         * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
         * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
         * after 16h.
         */
	if (boot_cpu_has(X86_FEATURE_APIC)) {
		if (c->x86 > 0x16)
			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
		else if (c->x86 >= 0xf) {
			/* check CPU config space for extended APIC ID */
			unsigned int val;

			val = read_pci_config(0, 24, 0, 0x68);
			if ((val >> 17 & 0x3) == 0x3)
				set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
		}
	}
#endif

	/*
         * This is only needed to tell the kernel whether to use VMCALL
         * and VMMCALL.  VMMCALL is never executed except under virt, so
         * we can set it unconditionally.
         */
	set_cpu_cap(c, X86_FEATURE_VMMCALL);

	/* F16h erratum 793, CVE-2013-6885 */
	if (c->x86 == 0x16 && c->x86_model <= 0xf)
		msr_set_bit(MSR_AMD64_LS_CFG, 15);

	/*
         * Check whether the machine is affected by erratum 400. This is
         * used to select the proper idle routine and to enable the check
         * whether the machine is affected in arch_post_acpi_init(), which
         * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
         */
	if (cpu_has_amd_erratum(c, amd_erratum_400))
		set_cpu_bug(c, X86_BUG_AMD_E400);

	/*
         * BIOS support is required for SME. If BIOS has enabled SME then
         * adjust x86_phys_bits by the SME physical address space reduction
         * value. If BIOS has not enabled SME then don't advertise the
         * feature (set in scattered.c). Also, since the SME support requires
         * long mode, don't advertise the feature under CONFIG_X86_32.
         */
	if (cpu_has(c, X86_FEATURE_SME)) {
		u64 msr;

		/* Check if SME is enabled */
		rdmsrl(MSR_K8_SYSCFG, msr);
		if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) {
			c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
			if (IS_ENABLED(CONFIG_X86_32))
				clear_cpu_cap(c, X86_FEATURE_SME);
		} else {
			clear_cpu_cap(c, X86_FEATURE_SME);
		}
	}
}


Contributors
PersonTokensPropCommitsCommitProp
Tom Lendacky8625.22%317.65%


Yinghai Lu8324.34%211.76%


Andreas Herrmann5516.13%15.88%


Borislav Petkov3610.56%423.53%


Huang Rui195.57%15.88%


Aravind Gopalakrishnan185.28%15.88%


Thomas Gleixner174.99%15.88%


Venkatesh Pallipadi102.93%15.88%


Paolo Bonzini82.35%15.88%


Andi Kleen72.05%15.88%


Rohit Seth20.59%15.88%


Total341100.00%17100.00%






static void init_amd_k8(struct cpuinfo_x86 *c)
{
	u32 level;
	u64 value;

	/* On C+ stepping K8 rep microcode works well for copy/memset */
	level = cpuid_eax(1);
	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);

	/*
         * Some BIOSes incorrectly force this feature, but only K8 revision D
         * (model = 0x14) and later actually support it.
         * (AMD Erratum #110, docId: 25759).
         */
	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
		clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
		if (!rdmsrl_amd_safe(0xc001100d, &value)) {
			value &= ~BIT_64(32);
			wrmsrl_amd_safe(0xc001100d, value);
		}
	}

	if (!c->x86_model_id[0])
		strcpy(c->x86_model_id, "Hammer");

#ifdef CONFIG_SMP
	/*
         * Disable TLB flush filter by setting HWCR.FFDIS on K8
         * bit 6 of msr C001_0015
         *
         * Errata 63 for SH-B3 steppings
         * Errata 122 for all steppings (F+ have it disabled by default)
         */
	msr_set_bit(MSR_K7_HWCR, 6);
#endif
	set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
}


Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov6848.57%444.44%


Yinghai Lu5237.14%222.22%


Kevin Winchester1510.71%111.11%


Boris Ostrovsky32.14%111.11%


Linus Torvalds21.43%111.11%


Total140100.00%9100.00%






static void init_amd_gh(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_64
	/* do this for boot cpu */
	if (c == &boot_cpu_data)
		check_enable_amd_mmconf_dmi();

	fam10h_check_enable_mmcfg();
#endif

	/*
         * Disable GART TLB Walk Errors on Fam10h. We do this here because this
         * is always needed when GART is enabled, even in a kernel which has no
         * MCE support built in. BIOS should disable GartTlbWlk Errors already.
         * If it doesn't, we do it here as suggested by the BKDG.
         *
         * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
         */
	msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);

	/*
         * On family 10h BIOS may not have properly enabled WC+ support, causing
         * it to be converted to CD memtype. This may result in performance
         * degradation for certain nested-paging guests. Prevent this conversion
         * by clearing bit 24 in MSR_AMD64_BU_CFG2.
         *
         * NOTE: we want to use the _safe accessors so as not to #GP kvm
         * guests on older kvm hosts.
         */
	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);

	if (cpu_has_amd_erratum(c, amd_erratum_383))
		set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
}


Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov4366.15%240.00%


Yinghai Lu2030.77%240.00%


Andi Kleen23.08%120.00%


Total65100.00%5100.00%




#define MSR_AMD64_DE_CFG	0xC0011029




static void init_amd_ln(struct cpuinfo_x86 *c)
{
	/*
         * Apply erratum 665 fix unconditionally so machines without a BIOS
         * fix work.
         */
	msr_set_bit(MSR_AMD64_DE_CFG, 31);
}


Contributors
PersonTokensPropCommitsCommitProp
Emanuel Czirai19100.00%1100.00%


Total19100.00%1100.00%






static void init_amd_bd(struct cpuinfo_x86 *c)
{
	u64 value;

	/* re-enable TopologyExtensions if switched off by BIOS */
	if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
	    !cpu_has(c, X86_FEATURE_TOPOEXT)) {

		if (msr_set_bit(0xc0011005, 54) > 0) {
			rdmsrl(0xc0011005, value);
			if (value & BIT_64(54)) {
				set_cpu_cap(c, X86_FEATURE_TOPOEXT);
				pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
			}
		}
	}

	/*
         * The way access filter has a performance penalty on some workloads.
         * Disable it on the affected CPUs.
         */
	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
		if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
			value |= 0x1E;
			wrmsrl_safe(MSR_F15H_IC_CFG, value);
		}
	}
}


Contributors
PersonTokensPropCommitsCommitProp
Andreas Herrmann5942.45%112.50%


Andre Przywara4633.09%112.50%


Borislav Petkov2618.71%450.00%


Boris Ostrovsky64.32%112.50%


Yinghai Lu21.44%112.50%


Total139100.00%8100.00%






static void init_amd_zn(struct cpuinfo_x86 *c)
{
	/*
         * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
         * all up to and including B1.
         */
	if (c->x86_model <= 1 && c->x86_mask <= 1)
		set_cpu_cap(c, X86_FEATURE_CPB);
}


Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov33100.00%1100.00%


Total33100.00%1100.00%






static void init_amd(struct cpuinfo_x86 *c)
{
	early_init_amd(c);

	/*
         * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
         * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
         */
	clear_cpu_cap(c, 0*32+31);

	if (c->x86 >= 0x10)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);

	/* get apicid instead of initial apic id from cpuid */
	c->apicid = hard_smp_processor_id();

	/* K6s reports MCEs but don't actually have all the MSRs */
	if (c->x86 < 6)
		clear_cpu_cap(c, X86_FEATURE_MCE);

	switch (c->x86) {
	case 4:    init_amd_k5(c); break;
	case 5:    init_amd_k6(c); break;
	case 6:	   init_amd_k7(c); break;
	case 0xf:  init_amd_k8(c); break;
	case 0x10: init_amd_gh(c); break;
	case 0x12: init_amd_ln(c); break;
	case 0x15: init_amd_bd(c); break;
	case 0x17: init_amd_zn(c); break;
	}

	/* Enable workaround for FXSAVE leak */
	if (c->x86 >= 6)
		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);

	cpu_detect_cache_sizes(c);

	/* Multi core CPU? */
	if (c->extended_cpuid_level >= 0x80000008) {
		amd_detect_cmp(c);
		srat_detect_node(c);
	}

#ifdef CONFIG_X86_32
	detect_ht(c);
#endif

	init_amd_cacheinfo(c);

	if (c->x86 >= 0xf)
		set_cpu_cap(c, X86_FEATURE_K8);

	if (cpu_has(c, X86_FEATURE_XMM2)) {
		/* MFENCE stops RDTSC speculation */
		set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
	}

	/*
         * Family 0x12 and above processors have APIC timer
         * running in deep C states.
         */
	if (c->x86 > 0x11)
		set_cpu_cap(c, X86_FEATURE_ARAT);

	/* 3DNow or LM implies PREFETCHW */
	if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
		if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
			set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);

	/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
	if (!cpu_has(c, X86_FEATURE_XENPV))
		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
}


Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov19463.40%523.81%


Yinghai Lu3812.42%29.52%


Andi Kleen227.19%419.05%


Boris Ostrovsky165.23%29.52%


Juergen Gross113.59%14.76%


Emanuel Czirai92.94%14.76%


Andrew Lutomirski72.29%14.76%


Joerg Roedel51.63%29.52%


Ingo Molnar20.65%14.76%


Torsten Kaiser10.33%14.76%


Andreas Herrmann10.33%14.76%


Total306100.00%21100.00%



#ifdef CONFIG_X86_32



static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if ((c->x86 == 6)) {
		/* Duron Rev A0 */
		if (c->x86_model == 3 && c->x86_mask == 0)
			size = 64;
		/* Tbird rev A1/A2 */
		if (c->x86_model == 4 &&
			(c->x86_mask == 0 || c->x86_mask == 1))
			size = 256;
	}
	return size;
}

Contributors
PersonTokensPropCommitsCommitProp
Dave Jones7697.44%150.00%


Alan Cox22.56%150.00%


Total78100.00%2100.00%



#endif




static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
{
	u32 ebx, eax, ecx, edx;
	u16 mask = 0xfff;

	if (c->x86 < 0xf)
		return;

	if (c->extended_cpuid_level < 0x80000006)
		return;

	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);

	tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
	tlb_lli_4k[ENTRIES] = ebx & mask;

	/*
         * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
         * characteristics from the CPUID function 0x80000005 instead.
         */
	if (c->x86 == 0xf) {
		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
		mask = 0xff;
	}

	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
	if (!((eax >> 16) & mask))
		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
	else
		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;

	/* a 4M entry uses two 2M entries */
	tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;

	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
	if (!(eax & mask)) {
		/* Erratum 658 */
		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
			tlb_lli_2m[ENTRIES] = 1024;
		} else {
			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
			tlb_lli_2m[ENTRIES] = eax & 0xff;
		}
	} else
		tlb_lli_2m[ENTRIES] = eax & mask;

	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
}


Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov258100.00%2100.00%


Total258100.00%2100.00%




static const struct cpu_dev amd_cpu_dev = {
	.c_vendor	= "AMD",
	.c_ident	= { "AuthenticAMD" },
#ifdef CONFIG_X86_32
	.legacy_models = {
		{ .family = 4, .model_names =
		  {
			  [3] = "486 DX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB",
			  [14] = "Am5x86-WT",
			  [15] = "Am5x86-WB"
		  }
		},
        },
	.legacy_cache_size = amd_size_cache,
#endif
	.c_early_init   = early_init_amd,
	.c_detect_tlb	= cpu_detect_tlb_amd,
	.c_bsp_init	= bsp_init_amd,
	.c_init		= init_amd,
	.c_x86_vendor	= X86_VENDOR_AMD,
};


cpu_dev_register(amd_cpu_dev);

/*
 * AMD errata checking
 *
 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
 * have an OSVW id assigned, which it takes as first argument. Both take a
 * variable number of family-specific model-stepping ranges created by
 * AMD_MODEL_RANGE().
 *
 * Example:
 *
 * const int amd_erratum_319[] =
 *      AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
 *                         AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
 *                         AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
 */


#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)


static const int amd_erratum_400[] =
	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));


static const int amd_erratum_383[] =
	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));





static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
{
	int osvw_id = *erratum++;
	u32 range;
	u32 ms;

	if (osvw_id >= 0 && osvw_id < 65536 &&
	    cpu_has(cpu, X86_FEATURE_OSVW)) {
		u64 osvw_len;

		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
		if (osvw_id < osvw_len) {
			u64 osvw_bits;

			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
			    osvw_bits);
			return osvw_bits & (1ULL << (osvw_id & 0x3f));
		}
	}

	/* OSVW unavailable or ID unknown, match family-model-stepping range */
	ms = (cpu->x86_model << 4) | cpu->x86_mask;
	while ((range = *erratum++))
		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
		    (ms >= AMD_MODEL_RANGE_START(range)) &&
		    (ms <= AMD_MODEL_RANGE_END(range)))
			return true;

	return false;
}


Contributors
PersonTokensPropCommitsCommitProp
Hans Rosenfeld15196.18%250.00%


Torsten Kaiser53.18%125.00%


Borislav Petkov10.64%125.00%


Total157100.00%4100.00%






void set_dr_addr_mask(unsigned long mask, int dr)
{
	if (!boot_cpu_has(X86_FEATURE_BPEXT))
		return;

	switch (dr) {
	case 0:
		wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
		break;
	case 1:
	case 2:
	case 3:
		wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
		break;
	default:
		break;
	}
}

Contributors
PersonTokensPropCommitsCommitProp
Jacob Shin6193.85%150.00%


Borislav Petkov46.15%150.00%


Total65100.00%2100.00%




Overall Contributors
PersonTokensPropCommitsCommitProp
Borislav Petkov138435.54%2621.31%


Dave Jones66116.97%54.10%


Yinghai Lu51113.12%75.74%


Andreas Herrmann2626.73%119.02%


Hans Rosenfeld2085.34%43.28%


Huang Rui1012.59%32.46%


Tom Lendacky862.21%32.46%


Yazen Ghannam862.21%21.64%


Andi Kleen852.18%1310.66%


Jacob Shin611.57%10.82%


Andre Przywara461.18%10.82%


Thomas Gleixner441.13%10.82%


Suravee Suthikulpanit411.05%10.82%


Aravind Gopalakrishnan411.05%21.64%


Emanuel Czirai320.82%10.82%


Boris Ostrovsky250.64%32.46%


Ingo Molnar170.44%21.64%


Kevin Winchester150.39%10.82%


Hector Marco-Gisbert150.39%10.82%


Tejun Heo150.39%21.64%


Art Haas140.36%10.82%


Andrew Lutomirski140.36%32.46%


Daniel J Blueman140.36%21.64%


Jordan Crouse120.31%10.82%


Chen Yucong120.31%10.82%


Juergen Gross110.28%10.82%


Venkatesh Pallipadi100.26%10.82%


Thomas Petazzoni90.23%10.82%


Paolo Bonzini80.21%10.82%


Rusty Russell70.18%10.82%


Torsten Kaiser60.15%10.82%


Joerg Roedel50.13%21.64%


Mikulas Patocka50.13%10.82%


Rohit Seth40.10%10.82%


Stephen Rothwell30.08%10.82%


Paul Gortmaker30.08%10.82%


Arnd Bergmann30.08%10.82%


Alan Cox30.08%10.82%


Jan Beulich30.08%21.64%


Tom Rini30.08%10.82%


Linus Torvalds20.05%10.82%


Jiang Liu20.05%10.82%


Suresh B. Siddha10.03%10.82%


Adam Buchbinder10.03%10.82%


Michael Opdenacker10.03%10.82%


Josh Poimboeuf10.03%10.82%


Laura Abbott10.03%10.82%


Total3894100.00%122100.00%


Directory: arch/x86/kernel/cpu



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