Release 4.14 arch/x86/kernel/cpu/common.c

#include <linux/bootmem.h>
#include <linux/linkage.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/percpu.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/sched/mm.h>
#include <linux/sched/clock.h>
#include <linux/sched/task.h>
#include <linux/init.h>
#include <linux/kprobes.h>
#include <linux/kgdb.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>

#include <asm/stackprotector.h>
#include <asm/perf_event.h>
#include <asm/mmu_context.h>
#include <asm/archrandom.h>
#include <asm/hypervisor.h>
#include <asm/processor.h>
#include <asm/tlbflush.h>
#include <asm/debugreg.h>
#include <asm/sections.h>
#include <asm/vsyscall.h>
#include <linux/topology.h>
#include <linux/cpumask.h>
#include <asm/pgtable.h>
#include <linux/atomic.h>
#include <asm/proto.h>
#include <asm/setup.h>
#include <asm/apic.h>
#include <asm/desc.h>
#include <asm/fpu/internal.h>
#include <asm/mtrr.h>
#include <asm/hwcap2.h>
#include <linux/numa.h>
#include <asm/asm.h>
#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/mce.h>
#include <asm/msr.h>
#include <asm/pat.h>
#include <asm/microcode.h>
#include <asm/microcode_intel.h>

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/uv/uv.h>
#endif

#include "cpu.h"


u32 elf_hwcap2 __read_mostly;

/* all of these masks are initialized in setup_cpu_local_masks() */

cpumask_var_t cpu_initialized_mask;

cpumask_var_t cpu_callout_mask;

cpumask_var_t cpu_callin_mask;

/* representing cpus for which sibling maps can be computed */

cpumask_var_t cpu_sibling_setup_mask;

/* correctly size the local cpu masks */


void __init setup_cpu_local_masks(void)
{
	alloc_bootmem_cpumask_var(&cpu_initialized_mask);
	alloc_bootmem_cpumask_var(&cpu_callin_mask);
	alloc_bootmem_cpumask_var(&cpu_callout_mask);
	alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
}

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static void default_init(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_64
	cpu_detect_cache_sizes(c);
#else
	/* Not much we can do here... */
	/* Check if at least it has cpuid */
	if (c->cpuid_level == -1) {
		/* No cpuid. It must be an ancient CPU */
		if (c->x86 == 4)
			strcpy(c->x86_model_id, "486");
		else if (c->x86 == 3)
			strcpy(c->x86_model_id, "386");
	}
#endif
}

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static const struct cpu_dev default_cpu = {
	.c_init		= default_init,
	.c_vendor	= "Unknown",
	.c_x86_vendor	= X86_VENDOR_UNKNOWN,
};


static const struct cpu_dev *this_cpu = &default_cpu;

DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
#ifdef CONFIG_X86_64
	/*
         * We need valid kernel segments for data and code in long mode too
         * IRET will check the segment types  kkeil 2000/10/28
         * Also sysret mandates a special GDT layout
         *
         * TLS descriptors are currently at a different place compared to i386.
         * Hopefully nobody expects them at a fixed place (Wine?)
         */
	[GDT_ENTRY_KERNEL32_CS]		= GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER32_CS]	= GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
#else
	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
	/*
         * Segments used for calling PnP BIOS have byte granularity.
         * They code segments and data segments have fixed 64k limits,
         * the transfer segment sizes are set at run time.
         */
	/* 32-bit code */
	[GDT_ENTRY_PNPBIOS_CS32]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
	/* 16-bit code */
	[GDT_ENTRY_PNPBIOS_CS16]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_DS]		= GDT_ENTRY_INIT(0x0092, 0, 0xffff),
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_TS1]		= GDT_ENTRY_INIT(0x0092, 0, 0),
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_TS2]		= GDT_ENTRY_INIT(0x0092, 0, 0),
	/*
         * The APM segments have byte granularity and their bases
         * are set at run time.  All have 64k limits.
         */
	/* 32-bit code */
	[GDT_ENTRY_APMBIOS_BASE]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
	/* 16-bit code */
	[GDT_ENTRY_APMBIOS_BASE+1]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
	/* data */
	[GDT_ENTRY_APMBIOS_BASE+2]	= GDT_ENTRY_INIT(0x4092, 0, 0xffff),

	[GDT_ENTRY_ESPFIX_SS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
	[GDT_ENTRY_PERCPU]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
	GDT_STACK_CANARY_INIT
#endif
} };

EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);



static int __init x86_mpx_setup(char *s)
{
	/* require an exact match without trailing characters */
	if (strlen(s))
		return 0;

	/* do not emit a message if the feature is not present */
	if (!boot_cpu_has(X86_FEATURE_MPX))
		return 1;

	setup_clear_cpu_cap(X86_FEATURE_MPX);
	pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
	return 1;
}
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__setup("nompx", x86_mpx_setup);

#ifdef CONFIG_X86_64


static int __init x86_nopcid_setup(char *s)
{
	/* nopcid doesn't accept parameters */
	if (s)
		return -EINVAL;

	/* do not emit a message if the feature is not present */
	if (!boot_cpu_has(X86_FEATURE_PCID))
		return 0;

	setup_clear_cpu_cap(X86_FEATURE_PCID);
	pr_info("nopcid: PCID feature disabled\n");
	return 0;
}
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early_param("nopcid", x86_nopcid_setup);
#endif



static int __init x86_noinvpcid_setup(char *s)
{
	/* noinvpcid doesn't accept parameters */
	if (s)
		return -EINVAL;

	/* do not emit a message if the feature is not present */
	if (!boot_cpu_has(X86_FEATURE_INVPCID))
		return 0;

	setup_clear_cpu_cap(X86_FEATURE_INVPCID);
	pr_info("noinvpcid: INVPCID feature disabled\n");
	return 0;
}
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early_param("noinvpcid", x86_noinvpcid_setup);

#ifdef CONFIG_X86_32

static int cachesize_override = -1;

static int disable_x86_serial_nr = 1;



static int __init cachesize_setup(char *str)
{
	get_option(&str, &cachesize_override);
	return 1;
}
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__setup("cachesize=", cachesize_setup);



static int __init x86_sep_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_SEP);
	return 1;
}
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__setup("nosep", x86_sep_setup);

/* Standard macro to see if a specific flag is changeable */


static inline int flag_is_changeable_p(u32 flag)
{
	u32 f1, f2;

	/*
         * Cyrix and IDT cpus allow disabling of CPUID
         * so the code below may return different results
         * when it is executed before and after enabling
         * the CPUID. Add "volatile" to not allow gcc to
         * optimize the subsequent calls to this function.
         */
	asm volatile ("pushfl                \n\t"
                      "pushfl           \n\t"
                      "popl %0          \n\t"
                      "movl %0, %1      \n\t"
                      "xorl %2, %0      \n\t"
                      "pushl %0         \n\t"
                      "popfl            \n\t"
                      "pushfl           \n\t"
                      "popl %0          \n\t"
                      "popfl            \n\t"

                      : "=&r" (f1), "=&r" (f2)
                      : "ir" (flag));

	return ((f1^f2) & flag) != 0;
}

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/* Probe for the CPUID instruction */


int have_cpuid_p(void)
{
	return flag_is_changeable_p(X86_EFLAGS_ID);
}

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static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

	if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
		return;

	/* Disable processor serial number: */

	rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
	lo |= 0x200000;
	wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);

	pr_notice("CPU serial number disabled.\n");
	clear_cpu_cap(c, X86_FEATURE_PN);

	/* Disabling the serial number may affect the cpuid level */
	c->cpuid_level = cpuid_eax(0);
}

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static int __init x86_serial_nr_setup(char *s)
{
	disable_x86_serial_nr = 0;
	return 1;
}
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__setup("serialnumber", x86_serial_nr_setup);
#else


static inline int flag_is_changeable_p(u32 flag)
{
	return 1;
}
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static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
}
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#endif



static __init int setup_disable_smep(char *arg)
{
	setup_clear_cpu_cap(X86_FEATURE_SMEP);
	/* Check for things that depend on SMEP being enabled: */
	check_mpx_erratum(&boot_cpu_data);
	return 1;
}
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__setup("nosmep", setup_disable_smep);



static __always_inline void setup_smep(struct cpuinfo_x86 *c)
{
	if (cpu_has(c, X86_FEATURE_SMEP))
		cr4_set_bits(X86_CR4_SMEP);
}

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static __init int setup_disable_smap(char *arg)
{
	setup_clear_cpu_cap(X86_FEATURE_SMAP);
	return 1;
}
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__setup("nosmap", setup_disable_smap);



static __always_inline void setup_smap(struct cpuinfo_x86 *c)
{
	unsigned long eflags = native_save_fl();

	/* This should have been cleared long ago */
	BUG_ON(eflags & X86_EFLAGS_AC);

	if (cpu_has(c, X86_FEATURE_SMAP)) {
#ifdef CONFIG_X86_SMAP
		cr4_set_bits(X86_CR4_SMAP);
#else
		cr4_clear_bits(X86_CR4_SMAP);
#endif
	}
}

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/*
 * Protection Keys are not available in 32-bit mode.
 */

static bool pku_disabled;



static __always_inline void setup_pku(struct cpuinfo_x86 *c)
{
	/* check the boot processor, plus compile options for PKU: */
	if (!cpu_feature_enabled(X86_FEATURE_PKU))
		return;
	/* checks the actual processor's cpuid bits: */
	if (!cpu_has(c, X86_FEATURE_PKU))
		return;
	if (pku_disabled)
		return;

	cr4_set_bits(X86_CR4_PKE);
	/*
         * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
         * cpuid bit to be set.  We need to ensure that we
         * update that bit in this CPU's "cpu_info".
         */
	get_cpu_cap(c);
}

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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS


static __init int setup_disable_pku(char *arg)
{
	/*
         * Do not clear the X86_FEATURE_PKU bit.  All of the
         * runtime checks are against OSPKE so clearing the
         * bit does nothing.
         *
         * This way, we will see "pku" in cpuinfo, but not
         * "ospke", which is exactly what we want.  It shows
         * that the CPU has PKU, but the OS has not enabled it.
         * This happens to be exactly how a system would look
         * if we disabled the config option.
         */
	pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
	pku_disabled = true;
	return 1;
}
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__setup("nopku", setup_disable_pku);
#endif /* CONFIG_X86_64 */

/*
 * Some CPU features depend on higher CPUID levels, which may not always
 * be available due to CPUID level capping or broken virtualization
 * software.  Add those features to this table to auto-disable them.
 */

struct cpuid_dependent_feature {
	
u32 feature;
	
u32 level;
};

static const struct cpuid_dependent_feature

cpuid_dependent_features[] = {
	{ X86_FEATURE_MWAIT,		0x00000005 },
	{ X86_FEATURE_DCA,		0x00000009 },
	{ X86_FEATURE_XSAVE,		0x0000000d },
	{ 0, 0 }
};



static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
{
	const struct cpuid_dependent_feature *df;

	for (df = cpuid_dependent_features; df->feature; df++) {

		if (!cpu_has(c, df->feature))
			continue;
		/*
                 * Note: cpuid_level is set to -1 if unavailable, but
                 * extended_extended_level is set to 0 if unavailable
                 * and the legitimate extended levels are all negative
                 * when signed; hence the weird messing around with
                 * signs here...
                 */
		if (!((s32)df->level < 0 ?
		     (u32)df->level > (u32)c->extended_cpuid_level :
		     (s32)df->level > (s32)c->cpuid_level))
			continue;

		clear_cpu_cap(c, df->feature);
		if (!warn)
			continue;

		pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
			x86_cap_flag(df->feature), df->level);
	}
}

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/*
 * Naming convention should be: <Name> [(<Codename>)]
 * This table only is used unless init_<vendor>() below doesn't set it;
 * in particular, if CPUID levels 0x80000002..4 are supported, this
 * isn't used
 */

/* Look up CPU names by table lookup. */


static const char *table_lookup_model(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	const struct legacy_cpu_model_info *info;

	if (c->x86_model >= 16)
		return NULL;	/* Range check */

	if (!this_cpu)
		return NULL;

	info = this_cpu->legacy_models;

	while (info->family) {
		if (info->family == c->x86)
			return info->model_names[c->x86_model];
		info++;
	}
#endif
	return NULL;		/* Not found */
}

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__u32 cpu_caps_cleared[NCAPINTS];

__u32 cpu_caps_set[NCAPINTS];



void load_percpu_segment(int cpu)
{
#ifdef CONFIG_X86_32
	loadsegment(fs, __KERNEL_PERCPU);
#else
	__loadsegment_simple(gs, 0);
	wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
#endif
	load_stack_canary_segment();
}

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/* Setup the fixmap mapping only once per-processor */


static inline void setup_fixmap_gdt(int cpu)
{
#ifdef CONFIG_X86_64
	/* On 64-bit systems, we use a read-only fixmap GDT. */
	pgprot_t prot = PAGE_KERNEL_RO;
#else
	/*
         * On native 32-bit systems, the GDT cannot be read-only because
         * our double fault handler uses a task gate, and entering through
         * a task gate needs to change an available TSS to busy.  If the GDT
         * is read-only, that will triple fault.
         *
         * On Xen PV, the GDT must be read-only because the hypervisor requires
         * it.
         */
	pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ?
		PAGE_KERNEL_RO : PAGE_KERNEL;
#endif

	__set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot);
}

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/* Load the original GDT from the per-cpu structure */


void load_direct_gdt(int cpu)
{
	struct desc_ptr gdt_descr;

	gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
	gdt_descr.size = GDT_SIZE - 1;
	load_gdt(&gdt_descr);
}
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100.00%
2
100.00%
Total
38
100.00%
2
100.00%


EXPORT_SYMBOL_GPL(load_direct_gdt);

/* Load a fixmap remapping of the per-cpu GDT */


void load_fixmap_gdt(int cpu)
{
	struct desc_ptr gdt_descr;

	gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
	gdt_descr.size = GDT_SIZE - 1;
	load_gdt(&gdt_descr);
}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
25
65.79%
1
20.00%
Dave Jones
7
18.42%
1
20.00%
Brian Gerst
3
7.89%
2
40.00%
Thomas Garnier
3
7.89%
1
20.00%
Total
38
100.00%
5
100.00%


EXPORT_SYMBOL_GPL(load_fixmap_gdt);

/*
 * Current gdt points %fs at the "master" per-cpu area: after this,
 * it's on the real one.
 */


void switch_to_new_gdt(int cpu)
{
	/* Load the original GDT */
	load_direct_gdt(cpu);
	/* Reload the per-cpu base */
	load_percpu_segment(cpu);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Thomas Garnier
13
65.00%
1
25.00%
Brian Gerst
5
25.00%
1
25.00%
Jeremy Fitzhardinge
1
5.00%
1
25.00%
Dave Jones
1
5.00%
1
25.00%
Total
20
100.00%
4
100.00%


static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};



static void get_model_name(struct cpuinfo_x86 *c)
{
	unsigned int *v;
	char *p, *q, *s;

	if (c->extended_cpuid_level < 0x80000004)
		return;

	v = (unsigned int *)c->x86_model_id;
	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
	c->x86_model_id[48] = 0;

	/* Trim whitespace */
	p = q = s = &c->x86_model_id[0];

	while (*p == ' ')
		p++;

	while (*p) {
		/* Note the last non-whitespace index */
		if (!isspace(*p))
			s = q;

		*q++ = *p++;
	}

	*(s + 1) = '\0';
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Dave Jones
110
53.66%
1
12.50%
Borislav Petkov
67
32.68%
1
12.50%
Andrew Morton
18
8.78%
1
12.50%
Yinghai Lu
6
2.93%
2
25.00%
Prarit Bhargava
2
0.98%
1
12.50%
Chuck Ebbert
1
0.49%
1
12.50%
Rusty Russell
1
0.49%
1
12.50%
Total
205
100.00%
8
100.00%



void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
{
	unsigned int n, dummy, ebx, ecx, edx, l2size;

	n = c->extended_cpuid_level;

	if (n >= 0x80000005) {
		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
		c->x86_cache_size = (ecx>>24) + (edx>>24);
#ifdef CONFIG_X86_64
		/* On K8 L1 TLB is inclusive, so don't count it */
		c->x86_tlbsize = 0;
#endif
	}

	if (n < 0x80000006)	/* Some chips just has a large L1. */
		return;

	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
	l2size = ecx >> 16;

#ifdef CONFIG_X86_64
	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
#else
	/* do processor-specific cache resizing */
	if (this_cpu->legacy_cache_size)
		l2size = this_cpu->legacy_cache_size(c, l2size);

	/* Allow user to override all this if necessary. */
	if (cachesize_override != -1)
		l2size = cachesize_override;

	if (l2size == 0)
		return;		/* Again, no L2 cache is possible */
#endif

	c->x86_cache_size = l2size;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Dave Jones
79
42.70%
1
8.33%
Andrew Morton
50
27.03%
1
8.33%
Yinghai Lu
44
23.78%
4
33.33%
Chuck Ebbert
3
1.62%
1
8.33%
Suresh B. Siddha
3
1.62%
1
8.33%
Andi Kleen
2
1.08%
1
8.33%
Jan Beulich
2
1.08%
1
8.33%
Borislav Petkov
1
0.54%
1
8.33%
Huang Ying
1
0.54%
1
8.33%
Total
185
100.00%
12
100.00%


u16 __read_mostly tlb_lli_4k[NR_INFO];

u16 __read_mostly tlb_lli_2m[NR_INFO];

u16 __read_mostly tlb_lli_4m[NR_INFO];

u16 __read_mostly tlb_lld_4k[NR_INFO];

u16 __read_mostly tlb_lld_2m[NR_INFO];

u16 __read_mostly tlb_lld_4m[NR_INFO];

u16 __read_mostly tlb_lld_1g[NR_INFO];



static void cpu_detect_tlb(struct cpuinfo_x86 *c)
{
	if (this_cpu->c_detect_tlb)
		this_cpu->c_detect_tlb(c);

	pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
		tlb_lli_4m[ENTRIES]);

	pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
		tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
		tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Alex Shi
58
84.06%
2
50.00%
Steven Honeyman
7
10.14%
1
25.00%
Kirill A. Shutemov
4
5.80%
1
25.00%
Total
69
100.00%
4
100.00%



void detect_ht(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	u32 eax, ebx, ecx, edx;
	int index_msb, core_bits;
	static bool printed;

	if (!cpu_has(c, X86_FEATURE_HT))
		return;

	if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
		goto out;

	if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
		return;

	cpuid(1, &eax, &ebx, &ecx, &edx);

	smp_num_siblings = (ebx & 0xff0000) >> 16;

	if (smp_num_siblings == 1) {
		pr_info_once("CPU0: Hyper-Threading is disabled\n");
		goto out;
	}

	if (smp_num_siblings <= 1)
		goto out;

	index_msb = get_count_order(smp_num_siblings);
	c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);

	smp_num_siblings = smp_num_siblings / c->x86_max_cores;

	index_msb = get_count_order(smp_num_siblings);

	core_bits = get_count_order(c->x86_max_cores);

	c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
				       ((1 << core_bits) - 1);

out:
	if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
		pr_info("CPU: Physical Processor ID: %d\n",
			c->phys_proc_id);
		pr_info("CPU: Processor Core ID: %d\n",
			c->cpu_core_id);
		printed = 1;
	}
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
152
66.09%
5
33.33%
Andrew Morton
39
16.96%
1
6.67%
Mike Travis
12
5.22%
1
6.67%
Ingo Molnar
9
3.91%
2
13.33%
Huang Ying
6
2.61%
1
6.67%
Suresh B. Siddha
4
1.74%
1
6.67%
Chen Yucong
3
1.30%
1
6.67%
Chuck Ebbert
3
1.30%
1
6.67%
Borislav Petkov
1
0.43%
1
6.67%
Linus Torvalds
1
0.43%
1
6.67%
Total
230
100.00%
15
100.00%



static void get_cpu_vendor(struct cpuinfo_x86 *c)
{
	char *v = c->x86_vendor_id;
	int i;

	for (i = 0; i < X86_VENDOR_NUM; i++) {
		if (!cpu_devs[i])
			break;

		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
		    (cpu_devs[i]->c_ident[1] &&
		     !strcmp(v, cpu_devs[i]->c_ident[1]))) {

			this_cpu = cpu_devs[i];
			c->x86_vendor = this_cpu->c_x86_vendor;
			return;
		}
	}

	pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
		    "CPU: Your system may be unstable.\n", v);

	c->x86_vendor = X86_VENDOR_UNKNOWN;
	this_cpu = &default_cpu;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
88
67.69%
4
28.57%
Rusty Russell
12
9.23%
1
7.14%
Thomas Petazzoni
9
6.92%
1
7.14%
Huang Ying
5
3.85%
1
7.14%
Andi Kleen
5
3.85%
1
7.14%
Ingo Molnar
3
2.31%
1
7.14%
MinChan Kim
2
1.54%
1
7.14%
Dave Jones
2
1.54%
1
7.14%
Hans Schou
2
1.54%
1
7.14%
Chen Yucong
1
0.77%
1
7.14%
Chuck Ebbert
1
0.77%
1
7.14%
Total
130
100.00%
14
100.00%



void cpu_detect(struct cpuinfo_x86 *c)
{
	/* Get vendor name */
	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
	      (unsigned int *)&c->x86_vendor_id[0],
	      (unsigned int *)&c->x86_vendor_id[8],
	      (unsigned int *)&c->x86_vendor_id[4]);

	c->x86 = 4;
	/* Intel-defined flags: level 0x00000001 */
	if (c->cpuid_level >= 0x00000001) {
		u32 junk, tfms, cap0, misc;

		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
		c->x86		= x86_family(tfms);
		c->x86_model	= x86_model(tfms);
		c->x86_mask	= x86_stepping(tfms);

		if (cap0 & (1<<19)) {
			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
			c->x86_cache_alignment = c->x86_clflush_size;
		}
	}
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Dave Jones
82
47.95%
1
7.14%
Andrew Morton
33
19.30%
1
7.14%
Yinghai Lu
16
9.36%
3
21.43%
H. Peter Anvin
11
6.43%
2
14.29%
Borislav Petkov
9
5.26%
1
7.14%
Harvey Harrison
8
4.68%
1
7.14%
Suresh B. Siddha
8
4.68%
1
7.14%
Alan Cox
1
0.58%
1
7.14%
Rusty Russell
1
0.58%
1
7.14%
Huang Ying
1
0.58%
1
7.14%
Jeff Garzik
1
0.58%
1
7.14%
Total
171
100.00%
14
100.00%



static void apply_forced_caps(struct cpuinfo_x86 *c)
{
	int i;

	for (i = 0; i < NCAPINTS; i++) {
		c->x86_capability[i] &= ~cpu_caps_cleared[i];
		c->x86_capability[i] |= cpu_caps_set[i];
	}
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Andrew Lutomirski
54
100.00%
1
100.00%
Total
54
100.00%
1
100.00%



void get_cpu_cap(struct cpuinfo_x86 *c)
{
	u32 eax, ebx, ecx, edx;

	/* Intel-defined flags: level 0x00000001 */
	if (c->cpuid_level >= 0x00000001) {
		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);

		c->x86_capability[CPUID_1_ECX] = ecx;
		c->x86_capability[CPUID_1_EDX] = edx;
	}

	/* Thermal and Power Management Leaf: level 0x00000006 (eax) */
	if (c->cpuid_level >= 0x00000006)
		c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);

	/* Additional Intel-defined flags: level 0x00000007 */
	if (c->cpuid_level >= 0x00000007) {
		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
		c->x86_capability[CPUID_7_0_EBX] = ebx;
		c->x86_capability[CPUID_7_ECX] = ecx;
	}

	/* Extended state features: level 0x0000000d */
	if (c->cpuid_level >= 0x0000000d) {
		cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);

		c->x86_capability[CPUID_D_1_EAX] = eax;
	}

	/* Additional Intel-defined flags: level 0x0000000F */
	if (c->cpuid_level >= 0x0000000F) {

		/* QoS sub-leaf, EAX=0Fh, ECX=0 */
		cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
		c->x86_capability[CPUID_F_0_EDX] = edx;

		if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
			/* will be overridden if occupancy monitoring exists */
			c->x86_cache_max_rmid = ebx;

			/* QoS sub-leaf, EAX=0Fh, ECX=1 */
			cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
			c->x86_capability[CPUID_F_1_EDX] = edx;

			if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
			      ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
			       (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
				c->x86_cache_max_rmid = ecx;
				c->x86_cache_occ_scale = ebx;
			}
		} else {
			c->x86_cache_max_rmid = -1;
			c->x86_cache_occ_scale = -1;
		}
	}

	/* AMD-defined flags: level 0x80000001 */
	eax = cpuid_eax(0x80000000);
	c->extended_cpuid_level = eax;

	if ((eax & 0xffff0000) == 0x80000000) {
		if (eax >= 0x80000001) {
			cpuid(0x80000001, &eax, &ebx, &ecx, &edx);

			c->x86_capability[CPUID_8000_0001_ECX] = ecx;
			c->x86_capability[CPUID_8000_0001_EDX] = edx;
		}
	}

	if (c->extended_cpuid_level >= 0x80000007) {
		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);

		c->x86_capability[CPUID_8000_0007_EBX] = ebx;
		c->x86_power = edx;
	}

	if (c->extended_cpuid_level >= 0x80000008) {
		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);

		c->x86_virt_bits = (eax >> 8) & 0xff;
		c->x86_phys_bits = eax & 0xff;
		c->x86_capability[CPUID_8000_0008_EBX] = ebx;
	}
#ifdef CONFIG_X86_32
	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
		c->x86_phys_bits = 36;
#endif

	if (c->extended_cpuid_level >= 0x8000000a)
		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);

	init_scattered_cpuid_features(c);

	/*
         * Clear/Set all flags overridden by options, after probe.
         * This needs to happen each time we re-probe, which may happen
         * several times during CPU initialization.
         */
	apply_forced_caps(c);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Peter P. Waskiewicz Jr
125
22.81%
1
4.00%
H. Peter Anvin
76
13.87%
2
8.00%
Borislav Petkov
75
13.69%
2
8.00%
Yazen Ghannam
42
7.66%
1
4.00%
Yinghai Lu
38
6.93%
5
20.00%
Dave Jones
38
6.93%
1
4.00%
Fenghua Yu
38
6.93%
1
4.00%
Andrew Lutomirski
27
4.93%
2
8.00%
Jan Beulich
26
4.74%
1
4.00%
Vikas Shivappa
22
4.01%
1
4.00%
Andi Kleen
16
2.92%
2
8.00%
Zongshun (Vincent) Wan
7
1.28%
1
4.00%
Dave Hansen
5
0.91%
1
4.00%
Jacob jun Pan
5
0.91%
1
4.00%
Jeff Garzik
4
0.73%
1
4.00%
Ingo Molnar
2
0.36%
1
4.00%
Suresh B. Siddha
2
0.36%
1
4.00%
Total
548
100.00%
25
100.00%



static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	int i;

	/*
         * First of all, decide if this is a 486 or higher
         * It's a 486 if we can modify the AC flag
         */
	if (flag_is_changeable_p(X86_EFLAGS_AC))
		c->x86 = 4;
	else
		c->x86 = 3;

	for (i = 0; i < X86_VENDOR_NUM; i++)
		if (cpu_devs[i] && cpu_devs[i]->c_identify) {
			c->x86_vendor_id[0] = 0;
			cpu_devs[i]->c_identify(c);
			if (c->x86_vendor_id[0]) {
				get_cpu_vendor(c);
				break;
			}
		}
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
105
100.00%
1
100.00%
Total
105
100.00%
1
100.00%

/*
 * Do minimum CPU detection early.
 * Fields really needed: vendor, cpuid_level, family, model, mask,
 * cache alignment.
 * The others are not touched to avoid unwanted side effects.
 *
 * WARNING: this function is only called on the BP.  Don't add code here
 * that is supposed to run on all CPUs.
 */


static void __init early_identify_cpu(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_64
	c->x86_clflush_size = 64;
	c->x86_phys_bits = 36;
	c->x86_virt_bits = 48;
#else
	c->x86_clflush_size = 32;
	c->x86_phys_bits = 32;
	c->x86_virt_bits = 32;
#endif
	c->x86_cache_alignment = c->x86_clflush_size;

	memset(&c->x86_capability, 0, sizeof c->x86_capability);
	c->extended_cpuid_level = 0;

	/* cyrix could have cpuid enabled via c_identify()*/
	if (have_cpuid_p()) {
		cpu_detect(c);
		get_cpu_vendor(c);
		get_cpu_cap(c);
		setup_force_cpu_cap(X86_FEATURE_CPUID);

		if (this_cpu->c_early_init)
			this_cpu->c_early_init(c);

		c->cpu_index = 0;
		filter_cpuid_features(c, false);

		if (this_cpu->c_bsp_init)
			this_cpu->c_bsp_init(c);
	} else {
		identify_cpu_without_cpuid(c);
		setup_clear_cpu_cap(X86_FEATURE_CPUID);
	}

	setup_force_cpu_cap(X86_FEATURE_ALWAYS);
	fpu__init_system(c);

#ifdef CONFIG_X86_32
	/*
         * Regardless of whether PCID is enumerated, the SDM says
         * that it can't be enabled in 32-bit mode.
         */
	setup_clear_cpu_cap(X86_FEATURE_PCID);
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
57
30.81%
7
28.00%
Borislav Petkov
36
19.46%
3
12.00%
Jan Beulich
24
12.97%
1
4.00%
Rusty Russell
17
9.19%
1
4.00%
Andrew Lutomirski
13
7.03%
2
8.00%
Suresh B. Siddha
10
5.41%
1
4.00%
H. Peter Anvin
7
3.78%
1
4.00%
Ingo Molnar
6
3.24%
2
8.00%
James Bottomley
5
2.70%
1
4.00%
Krzysztof Helt
3
1.62%
1
4.00%
Thomas Petazzoni
2
1.08%
1
4.00%
Andi Kleen
2
1.08%
1
4.00%
Robert Richter
1
0.54%
1
4.00%
Huang Ying
1
0.54%
1
4.00%
Dave Jones
1
0.54%
1
4.00%
Total
185
100.00%
25
100.00%



void __init early_cpu_init(void)
{
	const struct cpu_dev *const *cdev;
	int count = 0;

#ifdef CONFIG_PROCESSOR_SELECT
	pr_info("KERNEL supported cpus:\n");
#endif

	for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
		const struct cpu_dev *cpudev = *cdev;

		if (count >= X86_VENDOR_NUM)
			break;
		cpu_devs[count] = cpudev;
		count++;

#ifdef CONFIG_PROCESSOR_SELECT
		{
			unsigned int j;

			for (j = 0; j < 2; j++) {
				if (!cpudev->c_ident[j])
					continue;
				pr_info("  %s %s\n", cpudev->c_vendor,
					cpudev->c_ident[j]);
			}
		}
#endif
	}
	early_identify_cpu(&boot_cpu_data);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Yinghai Lu
86
65.65%
2
20.00%
H. Peter Anvin
16
12.21%
1
10.00%
Ingo Molnar
12
9.16%
1
10.00%
Andi Kleen
7
5.34%
1
10.00%
Jan Beulich
5
3.82%
2
20.00%
Dave Jones
3
2.29%
2
20.00%
Chen Yucong
2
1.53%
1
10.00%
Total
131
100.00%
10
100.00%

/*
 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
 * unfortunately, that's not true in practice because of early VIA
 * chips and (more importantly) broken virtualizers that are not easy
 * to detect. In the latter case it doesn't even *fail* reliably, so
 * probing for it doesn't even work. Disable it completely on 32-bit
 * unless we can find a reliable way to detect all the broken cases.
 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
 */


static void detect_nopl(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	clear_cpu_cap(c, X86_FEATURE_NOPL);
#else
	set_cpu_cap(c, X86_FEATURE_NOPL);
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Borislav Petkov
14
43.75%
1
25.00%
H. Peter Anvin
13
40.62%
1
25.00%
Venkatesh Pallipadi
4
12.50%
1
25.00%
Dave Jones
1
3.12%
1
25.00%
Total
32
100.00%
4
100.00%



static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_64
	/*
         * Empirically, writing zero to a segment selector on AMD does
         * not clear the base, whereas writing zero to a segment
         * selector on Intel does clear the base.  Intel's behavior
         * allows slightly faster context switches in the common case
         * where GS is unused by the prev and next threads.
         *
         * Since neither vendor documents this anywhere that I can see,
         * detect it directly instead of hardcoding the choice by
         * vendor.
         *
         * I've designated AMD's behavior as the "bug" because it's
         * counterintuitive and less friendly.
         */

	unsigned long old_base, tmp;
	rdmsrl(MSR_FS_BASE, old_base);
	wrmsrl(MSR_FS_BASE, 1);
	loadsegment(fs, 0);
	rdmsrl(MSR_FS_BASE, tmp);
	if (tmp != 0)
		set_cpu_bug(c, X86_BUG_NULL_SEG);
	wrmsrl(MSR_FS_BASE, old_base);
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Andrew Lutomirski
70
98.59%
2
66.67%
Dave Jones
1
1.41%
1
33.33%
Total
71
100.00%
3
100.00%



static void generic_identify(struct cpuinfo_x86 *c)
{
	c->extended_cpuid_level = 0;

	if (!have_cpuid_p())
		identify_cpu_without_cpuid(c);

	/* cyrix could have cpuid enabled via c_identify()*/
	if (!have_cpuid_p())
		return;

	cpu_detect(c);

	get_cpu_vendor(c);

	get_cpu_cap(c);

	if (c->cpuid_level >= 0x00000001) {
		c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
#ifdef CONFIG_X86_32
# ifdef CONFIG_SMP
		c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
# else
		c->apicid = c->initial_apicid;
# endif
#endif
		c->phys_proc_id = c->initial_apicid;
	}

	get_model_name(c); /* Default name */

	detect_nopl(c);

	detect_null_seg_behavior(c);

	/*
         * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
         * systems that run Linux at CPL > 0 may or may not have the
         * issue, but, even if they have the issue, there's absolutely
         * nothing we can do about it because we can't use the real IRET
         * instruction.
         *
         * NB: For the time being, only 32-bit kernels support
         * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
         * whether to apply espfix using paravirt hooks.  If any
         * non-paravirt system ever shows up that does *not* have the
         * ESPFIX issue, we can change this.
         */
#ifdef CONFIG_X86_32
# ifdef CONFIG_PARAVIRT
	do {
		extern void native_iret(void);
		if (pv_cpu_ops.iret == native_iret)
			set_cpu_bug(c, X86_BUG_ESPFIX);
	} while (0);
# else
	set_cpu_bug(c, X86_BUG_ESPFIX);
# endif
#endif
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Andrew Lutomirski
55
29.73%
2
12.50%
Yinghai Lu
52
28.11%
4
25.00%
Dave Jones
47
25.41%
2
12.50%
Suresh B. Siddha
12
6.49%
1
6.25%
H. Peter Anvin
8
4.32%
2
12.50%
David Shaohua Li
6
3.24%
1
6.25%
Ingo Molnar
4
2.16%
3
18.75%
Borislav Petkov
1
0.54%
1
6.25%
Total
185
100.00%
16
100.00%



static void x86_init_cache_qos(struct cpuinfo_x86 *c)
{
	/*
         * The heavy lifting of max_rmid and cache_occ_scale are handled
         * in get_cpu_cap().  Here we just set the max_rmid for the boot_cpu
         * in case CQM bits really aren't there in this CPU.
         */
	if (c != &boot_cpu_data) {
		boot_cpu_data.x86_cache_max_rmid =
			min(boot_cpu_data.x86_cache_max_rmid,
			    c->x86_cache_max_rmid);
	}
}

Contributors
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CommitProp
Peter P. Waskiewicz Jr
36
100.00%
1
100.00%
Total
36
100.00%
1
100.00%

/*
 * Validate that ACPI/mptables have the same information about the
 * effective APIC id and update the package map.
 */


static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	unsigned int apicid, cpu = smp_processor_id();

	apicid = apic->cpu_present_to_apicid(cpu);

	if (apicid != c->apicid) {
		pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
		       cpu, apicid, c->initial_apicid);
	}
	BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
#else
	c->logical_proc_id = 0;
#endif
}

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Thomas Gleixner
78
100.00%
2
100.00%
Total
78
100.00%
2
100.00%

/*
 * This does the hard work of actually picking apart the CPU stuff...
 */


static void identify_cpu(struct cpuinfo_x86 *c)
{
	int i;

	c->loops_per_jiffy = loops_per_jiffy;
	c->x86_cache_size = -1;
	c->x86_vendor = X86_VENDOR_UNKNOWN;
	c->x86_model = c->x86_mask = 0;	/* So far unknown... */
	c->x86_vendor_id[0] = '\0'; /* Unset */
	c->x86_model_id[0] = '\0';  /* Unset */
	c->x86_max_cores = 1;
	c->x86_coreid_bits = 0;
	c->cu_id = 0xff;
#ifdef CONFIG_X86_64
	c->x86_clflush_size = 64;
	c->x86_phys_bits = 36;
	c->x86_virt_bits = 48;
#else
	c->cpuid_level = -1;	/* CPUID not detected */
	c->x86_clflush_size = 32;
	c->x86_phys_bits = 32;
	c->x86_virt_bits = 32;
#endif
	c->x86_cache_alignment = c->x86_clflush_size;
	memset(&c->x86_capability, 0, sizeof c->x86_capability);

	generic_identify(c);

	if (this_cpu->c_identify)
		this_cpu->c_identify(c);

	/* Clear/Set all flags overridden by options, after probe */
	apply_forced_caps(c);

#ifdef CONFIG_X86_64
	c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
#endif

	/*
         * Vendor-specific initialization.  In this section we
         * canonicalize the feature flags, meaning if there are
         * features a certain CPU supports which CPUID doesn't
         * tell us, CPUID claiming incorrect flags, or other bugs,
         * we handle them here.
         *
         * At the end of this section, c->x86_capability better
         * indicate the features this CPU genuinely supports!
         */
	if (this_cpu->c_init)
		this_cpu->c_init(c);

	/* Disable the PN if appropriate */
	squash_the_stupid_serial_number(c);

	/* Set up SMEP/SMAP */
	setup_smep(c);
	setup_smap(c);

	/*
         * The vendor-specific functions might have changed features.
         * Now we do "generic changes."
         */

	/* Filter out anything that depends on CPUID levels we don't have */
	filter_cpuid_features(c, true);

	/* If the model name is still unset, do table lookup. */
	if (!c->x86_model_id[0]) {
		const char *p;
		p = table_lookup_model(c);
		if (p)
			strcpy(c->x86_model_id, p);
		else
			/* Last resort... */
			sprintf(c->x86_model_id, "%02x/%02x",
				c->x86, c->x86_model);
	}

#ifdef CONFIG_X86_64
	detect_ht(c);
#endif

	x86_init_rdrand(c);
	x86_init_cache_qos(c);
	setup_pku(c);

	/*
         * Clear/Set all flags overridden by options, need do it
         * before following smp all cpus cap AND.
         */
	apply_forced_caps(c);

	/*
         * On SMP, boot_cpu_data holds the common feature set between
         * all CPUs; so make sure that we indicate which features are
         * common between the CPUs.  The first time this routine gets
         * executed, c == &boot_cpu_data.
         */
	if (c != &boot_cpu_data) {
		/* AND the already accumulated flags with these */
		for (i = 0; i < NCAPINTS; i++)
			boot_cpu_data.x86_capability[i] &= c->x86_capability[i];

		/* OR, i.e. replicate the bug flags */
		for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
			c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
	}

	/* Init Machine Check Exception if available. */
	mcheck_cpu_init(c);

	select_idle_routine(c);

#ifdef CONFIG_NUMA
	numa_add_cpu(smp_processor_id());
#endif
}

Contributors
Person
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CommitProp
Dave Jones
177
42.34%
4
12.12%
Yinghai Lu
89
21.29%
5
15.15%
Borislav Petkov
37
8.85%
3
9.09%
Andi Kleen
37
8.85%
4
12.12%
H. Peter Anvin
24
5.74%
3
9.09%
Jan Beulich
23
5.50%
2
6.06%
Ingo Molnar
7
1.67%
3
9.09%
Andrew Lutomirski
6
1.44%
1
3.03%
Peter P. Waskiewicz Jr
5
1.20%
1
3.03%
Dave Hansen
5
1.20%
1
3.03%
Tejun Heo
2
0.48%
1
3.03%
Adam Buchbinder
2
0.48%
1
3.03%
Mikael Pettersson
1
0.24%
1
3.03%
Suresh B. Siddha
1
0.24%
1
3.03%
Chuck Ebbert
1
0.24%
1
3.03%
Jeremy Fitzhardinge
1
0.24%
1
3.03%
Total
418
100.00%
33
100.00%

/*
 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
 * on 32-bit kernels:
 */
#ifdef CONFIG_X86_32


void enable_sep_cpu(void)
{
	struct tss_struct *tss;
	int cpu;

	if (!boot_cpu_has(X86_FEATURE_SEP))
		return;

	cpu = get_cpu();
	tss = &per_cpu(cpu_tss, cpu);

	/*
         * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
         * see the big comment in struct x86_hw_tss's definition.
         */

	tss->x86_tss.ss1 = __KERNEL_CS;
	wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);

	wrmsr(MSR_IA32_SYSENTER_ESP,
	      (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
	      0);

	wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);

	put_cpu();
}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Andrew Lutomirski
56
57.14%
3
42.86%
Ingo Molnar
25
25.51%
2
28.57%
Borislav Petkov
9
9.18%
1
14.29%
Denys Vlasenko
8
8.16%
1
14.29%
Total
98
100.00%
7
100.00%

#endif



void __init identify_boot_cpu(void)
{
	identify_cpu(&boot_cpu_data);
#ifdef CONFIG_X86_32
	sysenter_setup();
	enable_sep_cpu();
#endif
	cpu_detect_tlb(&boot_cpu_data);
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Jeremy Fitzhardinge
12
38.71%
1
25.00%
David Shaohua Li
8
25.81%
1
25.00%
Alex Shi
6
19.35%
1
25.00%
Yinghai Lu
5
16.13%
1
25.00%
Total
31
100.00%
4
100.00%



void identify_secondary_cpu(struct cpuinfo_x86 *c)
{
	BUG_ON(c == &boot_cpu_data);
	identify_cpu(c);
#ifdef CONFIG_X86_32
	enable_sep_cpu();
#endif
	mtrr_ap_init();
	validate_apic_and_package_id(c);
}

Contributors
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Tokens
Prop
Commits
CommitProp
Jeremy Fitzhardinge
19
48.72%
1
20.00%
David Shaohua Li
9
23.08%
1
20.00%
Yinghai Lu
5
12.82%
1
20.00%
Thomas Gleixner
5
12.82%
1
20.00%
Dave Jones
1
2.56%
1
20.00%
Total
39
100.00%
5
100.00%



static __init int setup_noclflush(char *arg)
{
	setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
	setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
	return 1;
}
Contributors
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Tokens
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CommitProp
Dave Jones
12
50.00%
1
25.00%
Andi Kleen
6
25.00%
1
25.00%
H. Peter Anvin
6
25.00%
2
50.00%
Total
24
100.00%
4
100.00%

__setup("noclflush", setup_noclflush);



void print_cpu_info(struct cpuinfo_x86 *c)
{
	const char *vendor = NULL;

	if (c->x86_vendor < X86_VENDOR_NUM) {
		vendor = this_cpu->c_vendor;
	} else {
		if (c->cpuid_level >= 0)
			vendor = c->x86_vendor_id;
	}

	if (vendor && !strstr(c->x86_model_id, vendor))
		pr_cont("%s ", vendor);

	if (c->x86_model_id[0])
		pr_cont("%s", c->x86_model_id);
	else
		pr_cont("%d86", c->x86);

	pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);

	if (c->x86_mask || c->cpuid_level >= 0)
		pr_cont(", stepping: 0x%x)\n", c->x86_mask);
	else
		pr_cont(")\n");
}

Contributors
Person
Tokens
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CommitProp
Dave Jones
98
70.50%
2
15.38%
Borislav Petkov
14
10.07%
2
15.38%
Chen Yucong
6
4.32%
1
7.69%
Andi Kleen
6
4.32%
2
15.38%
Ingo Molnar
5
3.60%
1
7.69%
Jeremy Fitzhardinge
4
2.88%
1
7.69%
Yinghai Lu
4
2.88%
2
15.38%
Jan Beulich
1
0.72%
1
7.69%
Chuck Ebbert
1
0.72%
1
7.69%
Total
139
100.00%
13
100.00%



static __init int setup_disablecpuid(char *arg)
{
	int bit;

	if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
		setup_clear_cpu_cap(bit);
	else
		return 0;

	return 1;
}
Contributors
Person
Tokens
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Commits
CommitProp
Andi Kleen
34
72.34%
1
20.00%
Jeremy Fitzhardinge
7
14.89%
1
20.00%
Lukasz Odzioba
4
8.51%
1
20.00%
Dave Jones
1
2.13%
1
20.00%
David Shaohua Li
1
2.13%
1
20.00%
Total
47
100.00%
5
100.00%

__setup("clearcpuid=", setup_disablecpuid);

#ifdef CONFIG_X86_64
DEFINE_PER_CPU_FIRST(union irq_stack_union,
		     irq_stack_union) __aligned(PAGE_SIZE) __visible;

/*
 * The following percpu variables are hot.  Align current_task to
 * cacheline size such that they fall in the same cacheline.
 */
DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
	&init_task;

EXPORT_PER_CPU_SYMBOL(current_task);

DEFINE_PER_CPU(char *, irq_stack_ptr) =
	init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;

DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;

DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;

EXPORT_PER_CPU_SYMBOL(__preempt_count);

/*
 * Special IST stacks which the CPU switches to when it calls
 * an IST-marked descriptor entry. Up to 7 stacks (hardware
 * limit), all of them are 4K, except the debug stack which
 * is 8K.
 */

static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
	  [0 ... N_EXCEPTION_STACKS - 1]	= EXCEPTION_STKSZ,
	  [DEBUG_STACK - 1]			= DEBUG_STKSZ
};

static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
	[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);

/* May not be marked __init: used by software suspend */


void syscall_init(void)
{
	wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
	wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);

#ifdef CONFIG_IA32_EMULATION
	wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
	/*
         * This only works on Intel CPUs.
         * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
         * This does not cause SYSENTER to jump to the wrong location, because
         * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
         */
	wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
	wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
#else
	wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
	wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
	wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
#endif

	/* Flags to clear on syscall */
	wrmsrl(MSR_SYSCALL_MASK,
	       X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
	       X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
}

Contributors
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Commits
CommitProp
Yinghai Lu
37
28.03%
1
7.69%
Ingo Molnar
34
25.76%
4
30.77%
Denys Vlasenko
29
21.97%
2
15.38%
Andrew Lutomirski
14
10.61%
2
15.38%
Borislav Petkov
9
6.82%
2
15.38%
Andi Kleen
7
5.30%
1
7.69%
H. Peter Anvin
2
1.52%
1
7.69%
Total
132
100.00%
13
100.00%

/*
 * Copies of the original ist values from the tss are only accessed during
 * debugging, no special alignment required.
 */
DEFINE_PER_CPU(struct orig_ist, orig_ist);

static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
DEFINE_PER_CPU(int, debug_stack_usage);



int is_debug_stack(unsigned long addr)
{
	return __this_cpu_read(debug_stack_usage) ||
		(addr <= __this_cpu_read(debug_stack_addr) &&
		 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
}
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Steven Rostedt
32
91.43%
2
66.67%
Christoph Lameter
3
8.57%
1
33.33%
Total
35
100.00%
3
100.00%


NOKPROBE_SYMBOL(is_debug_stack);

DEFINE_PER_CPU(u32, debug_idt_ctr);



void debug_stack_set_zero(void)
{
	this_cpu_inc(debug_idt_ctr);
	load_current_idt();
}
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Steven Rostedt
12
80.00%
2
66.67%
Seiji Aguchi
3
20.00%
1
33.33%
Total
15
100.00%
3
100.00%


NOKPROBE_SYMBOL(debug_stack_set_zero);



void debug_stack_reset(void)
{
	if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
		return;
	if (this_cpu_dec_return(debug_idt_ctr) == 0)
		load_current_idt();
}
Contributors
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Steven Rostedt
27
87.10%
2
66.67%
Seiji Aguchi
4
12.90%
1
33.33%
Total
31
100.00%
3
100.00%


NOKPROBE_SYMBOL(debug_stack_reset);

#else	/* CONFIG_X86_64 */

DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;

EXPORT_PER_CPU_SYMBOL(current_task);
DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;

EXPORT_PER_CPU_SYMBOL(__preempt_count);

/*
 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
 * the top of the kernel stack.  Use an extra percpu variable to track the
 * top of the kernel stack directly.
 */
DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
	(unsigned long)&init_thread_union + THREAD_SIZE;

EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);

#ifdef CONFIG_CC_STACKPROTECTOR
DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
#endif

#endif	/* CONFIG_X86_64 */

/*
 * Clear all 6 debug registers:
 */


static void clear_all_debug_regs(void)
{
	int i;

	for (i = 0; i < 8; i++) {
		/* Ignore db4, db5 */
		if ((i == 4) || (i == 5))
			continue;

		set_debugreg(0, i);
	}
}

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1
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#ifdef CONFIG_KGDB
/*
 * Restore debug regs if using kgdbwait and you have a kernel debugger
 * connection established.
 */


static void dbg_restore_debug_regs(void)
{
	if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
		arch_kgdb_ops.correct_hw_break();
}
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#else /* ! CONFIG_KGDB */

#define dbg_restore_debug_regs()
#endif /* ! CONFIG_KGDB */



static void wait_for_master_cpu(int cpu)
{
#ifdef CONFIG_SMP
	/*
         * wait for ACK from master CPU before continuing
         * with AP initialization
         */
	WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
	while (!cpumask_test_cpu(cpu, cpu_callout_mask))
		cpu_relax();
#endif
}

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/*
 * cpu_init() initializes state that is per-CPU. Some data is already
 * initialized (naturally) in the bootstrap process, such as the GDT
 * and IDT. We reload them nevertheless, this function acts as a
 * 'CPU state barrier', nothing should get across.
 * A lot of state is already set up in PDA init for 64 bit
 */
#ifdef CONFIG_X86_64



void cpu_init(void)
{
	struct orig_ist *oist;
	struct task_struct *me;
	struct tss_struct *t;
	unsigned long v;
	int cpu = raw_smp_processor_id();
	int i;

	wait_for_master_cpu(cpu);

	/*
         * Initialize the CR4 shadow before doing anything that could
         * try to read it.
         */
	cr4_init_shadow();

	if (cpu)
		load_ucode_ap();

	t = &per_cpu(cpu_tss, cpu);
	oist = &per_cpu(orig_ist, cpu);

#ifdef CONFIG_NUMA
	if (this_cpu_read(numa_node) == 0 &&
	    early_cpu_to_node(cpu) != NUMA_NO_NODE)
		set_numa_node(early_cpu_to_node(cpu));
#endif

	me = current;

	pr_debug("Initializing CPU#%d\n", cpu);

	cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

	/*
         * Initialize the per-CPU GDT with the boot GDT,
         * and set up the GDT descriptor:
         */

	switch_to_new_gdt(cpu);
	loadsegment(fs, 0);

	load_current_idt();

	memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
	syscall_init();

	wrmsrl(MSR_FS_BASE, 0);
	wrmsrl(MSR_KERNEL_GS_BASE, 0);
	barrier();

	x86_configure_nx();
	x2apic_setup();

	/*
         * set up and load the per-CPU TSS
         */
	if (!oist->ist[0]) {
		char *estacks = per_cpu(exception_stacks, cpu);

		for (v = 0; v < N_EXCEPTION_STACKS; v++) {
			estacks += exception_stack_sizes[v];
			oist->ist[v] = t->x86_tss.ist[v] =
					(unsigned long)estacks;
			if (v == DEBUG_STACK-1)
				per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
		}
	}

	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);

	/*
         * <= is required because the CPU will access up to
         * 8 bits beyond the end of the IO permission bitmap.
         */
	for (i = 0; i <= IO_BITMAP_LONGS; i++)
		t->io_bitmap[i] = ~0UL;

	mmgrab(&init_mm);
	me->active_mm = &init_mm;
	BUG_ON(me->mm);
	initialize_tlbstate_and_flush();
	enter_lazy_tlb(&init_mm, me);

	load_sp0(t, &current->thread);
	set_tss_desc(cpu, t);
	load_TR_desc();
	load_mm_ldt(&init_mm);

	clear_all_debug_regs();
	dbg_restore_debug_regs();

	fpu__init_cpu();

	if (is_uv_system())
		uv_cpu_init();

	setup_fixmap_gdt(cpu);
	load_fixmap_gdt(cpu);
}

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Yinghai Lu
203
52.05%
1
2.86%
Brian Gerst
43
11.03%
4
11.43%
Ingo Molnar
26
6.67%
2
5.71%
Steven Rostedt
21
5.38%
1
2.86%
Dave Jones
18
4.62%
1
2.86%
Thomas Petazzoni
11
2.82%
1
2.86%
Andrew Lutomirski
11
2.82%
6
17.14%
Thomas Garnier
10
2.56%
1
2.86%
Igor Mammedov
7
1.79%
1
2.86%
Thomas Gleixner
5
1.28%
2
5.71%
Borislav Petkov
4
1.03%
1
2.86%
Lee Schermerhorn
4
1.03%
1
2.86%
Tejun Heo
4
1.03%
1
2.86%
Andi Kleen
4
1.03%
1
2.86%
Fenghua Yu
3
0.77%
1
2.86%
Stoyan Gaydarov
3
0.77%
1
2.86%
Jeremy Fitzhardinge
3
0.77%
1
2.86%
Jason Wessel
2
0.51%
1
2.86%
Seiji Aguchi
2
0.51%
1
2.86%
H. Peter Anvin
1
0.26%
1
2.86%
Vegard Nossum
1
0.26%
1
2.86%
Andrew Morton
1
0.26%
1
2.86%
Mike Travis
1
0.26%
1
2.86%
Jaswinder Singh Rajput
1
0.26%
1
2.86%
Alex Shi
1
0.26%
1
2.86%
Total
390
100.00%
35
100.00%

#else



void cpu_init(void)
{
	int cpu = smp_processor_id();
	struct task_struct *curr = current;
	struct tss_struct *t = &per_cpu(cpu_tss, cpu);
	struct thread_struct *thread = &curr->thread;

	wait_for_master_cpu(cpu);

	/*
         * Initialize the CR4 shadow before doing anything that could
         * try to read it.
         */
	cr4_init_shadow();

	show_ucode_info_early();

	pr_info("Initializing CPU#%d\n", cpu);

	if (cpu_feature_enabled(X86_FEATURE_VME) ||
	    boot_cpu_has(X86_FEATURE_TSC) ||
	    boot_cpu_has(X86_FEATURE_DE))
		cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

	load_current_idt();
	switch_to_new_gdt(cpu);

	/*
         * Set up and load the per-CPU TSS and LDT
         */
	mmgrab(&init_mm);
	curr->active_mm = &init_mm;
	BUG_ON(curr->mm);
	initialize_tlbstate_and_flush();
	enter_lazy_tlb(&init_mm, curr);

	load_sp0(t, thread);
	set_tss_desc(cpu, t);
	load_TR_desc();
	load_mm_ldt(&init_mm);

	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);

#ifdef CONFIG_DOUBLEFAULT
	/* Set up doublefault TSS pointer in the GDT */
	__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
#endif

	clear_all_debug_regs();
	dbg_restore_debug_regs();

	fpu__init_cpu();

	setup_fixmap_gdt(cpu);
	load_fixmap_gdt(cpu);
}
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2
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Dave Jones
38
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1
3.33%
Thomas Gleixner
14
6.93%
1
3.33%
Linus Torvalds
14
6.93%
2
6.67%
Rusty Russell
11
5.45%
1
3.33%
Thomas Garnier
10
4.95%
1
3.33%
Borislav Petkov
8
3.96%
2
6.67%
Andrew Lutomirski
6
2.97%
4
13.33%
Ingo Molnar
5
2.48%
2
6.67%
Matt Mackall
5
2.48%
1
3.33%
Steven Rostedt
4
1.98%
1
3.33%
Dave Hansen
4
1.98%
1
3.33%
Brian Gerst
3
1.49%
1
3.33%
Jason Wessel
3
1.49%
1
3.33%
Stoyan Gaydarov
3
1.49%
1
3.33%
Seiji Aguchi
2
0.99%
1
3.33%
Jaswinder Singh Rajput
2
0.99%
1
3.33%
Igor Mammedov
2
0.99%
1
3.33%
Suresh B. Siddha
2
0.99%
1
3.33%
Chen Yucong
1
0.50%
1
3.33%
Zachary Amsden
1
0.50%
1
3.33%
H. Peter Anvin
1
0.50%
1
3.33%
Vegard Nossum
1
0.50%
1
3.33%
Total
202
100.00%
30
100.00%

#endif



static void bsp_resume(void)
{
	if (this_cpu->c_bsp_resume)
		this_cpu->c_bsp_resume(&boot_cpu_data);
}

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static struct syscore_ops cpu_syscore_ops = {
	.resume		= bsp_resume,
};



static int __init init_cpu_syscore(void)
{
	register_syscore_ops(&cpu_syscore_ops);
	return 0;
}
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core_initcall(init_cpu_syscore);
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1225
19.53%
27
9.93%
Dave Jones
923
14.72%
5
1.84%
Andrew Lutomirski
480
7.65%
26
9.56%
H. Peter Anvin
389
6.20%
14
5.15%
Borislav Petkov
290
4.62%
21
7.72%
Ingo Molnar
209
3.33%
24
8.82%
Jeremy Fitzhardinge
169
2.69%
8
2.94%
Peter P. Waskiewicz Jr
166
2.65%
1
0.37%
Andi Kleen
160
2.55%
12
4.41%
Akinobu Mita
159
2.54%
1
0.37%
Andrew Morton
141
2.25%
2
0.74%
Dave Hansen
140
2.23%
7
2.57%
Rusty Russell
129
2.06%
5
1.84%
Steven Rostedt
117
1.87%
4
1.47%
Fenghua Yu
117
1.87%
5
1.84%
Brian Gerst
117
1.87%
9
3.31%
Thomas Garnier
116
1.85%
2
0.74%
Alex Shi
107
1.71%
3
1.10%
Thomas Gleixner
105
1.67%
5
1.84%
Ondrej Zary
97
1.55%
1
0.37%
Jan Beulich
92
1.47%
4
1.47%
Jaswinder Singh Rajput
91
1.45%
4
1.47%
Tejun Heo
74
1.18%
5
1.84%
Laura Abbott
60
0.96%
1
0.37%
Suresh B. Siddha
60
0.96%
7
2.57%
Igor Mammedov
47
0.75%
1
0.37%
Jason Wessel
43
0.69%
1
0.37%
Yazen Ghannam
42
0.67%
1
0.37%
Denys Vlasenko
37
0.59%
3
1.10%
Chuck Ebbert
30
0.48%
3
1.10%
Mike Travis
25
0.40%
2
0.74%
David Shaohua Li
24
0.38%
3
1.10%
Peter Zijlstra
24
0.38%
1
0.37%
Vikas Shivappa
22
0.35%
1
0.37%
Thomas Petazzoni
22
0.35%
1
0.37%
Linus Torvalds
21
0.33%
6
2.21%
Masami Hiramatsu
18
0.29%
1
0.37%
Chen Yucong
15
0.24%
1
0.37%
Huang Ying
14
0.22%
1
0.37%
Seiji Aguchi
12
0.19%
2
0.74%
Kirill A. Shutemov
11
0.18%
1
0.37%
James Bottomley
9
0.14%
2
0.74%
Harvey Harrison
8
0.13%
1
0.37%
Grzegorz Andrejczuk
7
0.11%
1
0.37%
Zongshun (Vincent) Wan
7
0.11%
1
0.37%
Steven Honeyman
7
0.11%
1
0.37%
Glauber de Oliveira Costa
7
0.11%
2
0.74%
Krzysztof Helt
6
0.10%
2
0.74%
Josh Triplett
6
0.10%
1
0.37%
Stoyan Gaydarov
6
0.10%
1
0.37%
Jeff Garzik
5
0.08%
1
0.37%
Jacob jun Pan
5
0.08%
1
0.37%
Matt Mackall
5
0.08%
1
0.37%
Lukasz Odzioba
4
0.06%
1
0.37%
Lee Schermerhorn
4
0.06%
1
0.37%
Alexey Dobriyan
4
0.06%
2
0.74%
Venkatesh Pallipadi
4
0.06%
1
0.37%
Alan Cox
4
0.06%
2
0.74%
Shai Fultheim
4
0.06%
1
0.37%
Paul Gortmaker
4
0.06%
2
0.74%
Christoph Lameter
3
0.05%
1
0.37%
Andrew Cooper
3
0.05%
1
0.37%
MinChan Kim
2
0.03%
1
0.37%
Alok N Kataria
2
0.03%
1
0.37%
Adam Buchbinder
2
0.03%
1
0.37%
Nitin A. Kamble
2
0.03%
1
0.37%
Prarit Bhargava
2
0.03%
1
0.37%
Hans Schou
2
0.03%
1
0.37%
Vegard Nossum
2
0.03%
1
0.37%
Arun Sharma
1
0.02%
1
0.37%
Zachary Amsden
1
0.02%
1
0.37%
Robert Richter
1
0.02%
1
0.37%
Adrian Bunk
1
0.02%
1
0.37%
Mikael Pettersson
1
0.02%
1
0.37%
Paolo Ciarrocchi
1
0.02%
1
0.37%
Total
6272
100.00%
272
100.00%
Directory: arch/x86/kernel/cpu

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