Release 4.14 arch/x86/kernel/irqinit.c
// SPDX-License-Identifier: GPL-2.0
#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/kprobes.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/device.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/setup.h>
#include <asm/i8259.h>
#include <asm/traps.h>
#include <asm/prom.h>
/*
* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
* (these are usually mapped to vectors 0x30-0x3f)
*/
/*
* The IO-APIC gives us many more interrupt sources. Most of these
* are unused but an SMP system is supposed to have enough memory ...
* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
* across the spectrum, so we really want to be prepared to get all
* of these. Plus, more powerful systems might have more than 64
* IO-APIC registers.
*
* (these are usually mapped into the 0x30-0xff vector range)
*/
/*
* IRQ2 is cascade interrupt to second interrupt controller
*/
static struct irqaction irq2 = {
.handler = no_action,
.name = "cascade",
.flags = IRQF_NO_THREAD,
};
DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
[0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
};
void __init init_ISA_irqs(void)
{
struct irq_chip *chip = legacy_pic->chip;
int i;
#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
init_bsp_APIC();
#endif
legacy_pic->init(0);
for (i = 0; i < nr_legacy_irqs(); i++)
irq_set_chip_and_handler(i, chip, handle_level_irq);
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Linus Torvalds (pre-git) | 27 | 40.91% | 1 | 10.00% |
Pekka J Enberg | 13 | 19.70% | 1 | 10.00% |
Thomas Gleixner | 10 | 15.15% | 1 | 10.00% |
Andi Kleen | 7 | 10.61% | 1 | 10.00% |
Jacob jun Pan | 3 | 4.55% | 1 | 10.00% |
Ingo Molnar | 2 | 3.03% | 1 | 10.00% |
Yinghai Lu | 2 | 3.03% | 2 | 20.00% |
Maciej W. Rozycki | 1 | 1.52% | 1 | 10.00% |
Jiang Liu | 1 | 1.52% | 1 | 10.00% |
Total | 66 | 100.00% | 10 | 100.00% |
void __init init_IRQ(void)
{
int i;
/*
* On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
* If these IRQ's are handled by legacy interrupt-controllers like PIC,
* then this configuration will likely be static after the boot. If
* these IRQ's are handled by more mordern controllers like IO-APIC,
* then this vector space can be freed and re-used dynamically as the
* irq's migrate etc.
*/
for (i = 0; i < nr_legacy_irqs(); i++)
per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
x86_init.irqs.intr_init();
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Suresh B. Siddha | 28 | 54.90% | 1 | 14.29% |
Thomas Gleixner | 13 | 25.49% | 3 | 42.86% |
Glauber de Oliveira Costa | 5 | 9.80% | 1 | 14.29% |
Brian Gerst | 4 | 7.84% | 1 | 14.29% |
Jiang Liu | 1 | 1.96% | 1 | 14.29% |
Total | 51 | 100.00% | 7 | 100.00% |
void __init native_init_IRQ(void)
{
/* Execute any quirks before the call gates are initialised: */
x86_init.irqs.pre_vector_init();
idt_setup_apic_and_irq_gates();
if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
setup_irq(2, &irq2);
irq_ctx_init(smp_processor_id());
}
Contributors
Person | Tokens | Prop | Commits | CommitProp |
Cyrill V. Gorcunov | 13 | 29.55% | 1 | 8.33% |
Glauber de Oliveira Costa | 7 | 15.91% | 1 | 8.33% |
Thomas Gleixner | 6 | 13.64% | 2 | 16.67% |
Sebastian Andrzej Siewior | 3 | 6.82% | 1 | 8.33% |
Andy Shevchenko | 3 | 6.82% | 1 | 8.33% |
Andrew Morton | 3 | 6.82% | 1 | 8.33% |
Pekka J Enberg | 3 | 6.82% | 1 | 8.33% |
James Bottomley | 2 | 4.55% | 1 | 8.33% |
Yinghai Lu | 2 | 4.55% | 1 | 8.33% |
Mikael Pettersson | 1 | 2.27% | 1 | 8.33% |
Linus Torvalds (pre-git) | 1 | 2.27% | 1 | 8.33% |
Total | 44 | 100.00% | 12 | 100.00% |
Overall Contributors
Person | Tokens | Prop | Commits | CommitProp |
Linus Torvalds (pre-git) | 65 | 22.89% | 2 | 4.35% |
Thomas Gleixner | 35 | 12.32% | 8 | 17.39% |
Cyrill V. Gorcunov | 31 | 10.92% | 1 | 2.17% |
Suresh B. Siddha | 29 | 10.21% | 1 | 2.17% |
Yinghai Lu | 22 | 7.75% | 4 | 8.70% |
Pekka J Enberg | 16 | 5.63% | 2 | 4.35% |
Andi Kleen | 15 | 5.28% | 1 | 2.17% |
Glauber de Oliveira Costa | 12 | 4.23% | 2 | 4.35% |
Jaswinder Singh Rajput | 9 | 3.17% | 2 | 4.35% |
Sebastian Andrzej Siewior | 6 | 2.11% | 1 | 2.17% |
Ingo Molnar | 6 | 2.11% | 3 | 6.52% |
Linus Torvalds | 5 | 1.76% | 2 | 4.35% |
Brian Gerst | 4 | 1.41% | 1 | 2.17% |
James Bottomley | 4 | 1.41% | 2 | 4.35% |
Andrew Morton | 4 | 1.41% | 2 | 4.35% |
Adrian Bunk | 3 | 1.06% | 1 | 2.17% |
Andy Shevchenko | 3 | 1.06% | 1 | 2.17% |
Jacob jun Pan | 3 | 1.06% | 1 | 2.17% |
Jiang Liu | 2 | 0.70% | 1 | 2.17% |
Pavel Machek | 2 | 0.70% | 1 | 2.17% |
Len Brown | 2 | 0.70% | 1 | 2.17% |
Paul Jimenez | 1 | 0.35% | 1 | 2.17% |
Arun Sharma | 1 | 0.35% | 1 | 2.17% |
Greg Kroah-Hartman | 1 | 0.35% | 1 | 2.17% |
Mikael Pettersson | 1 | 0.35% | 1 | 2.17% |
Kay Sievers | 1 | 0.35% | 1 | 2.17% |
Maciej W. Rozycki | 1 | 0.35% | 1 | 2.17% |
Total | 284 | 100.00% | 46 | 100.00% |
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