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Release 4.14 drivers/bus/mvebu-mbus.c

Directory: drivers/bus
/*
 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
 * 370/XP, Dove, Orion5x and MV78xx0)
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Marvell EBU SoCs have a configurable physical address space:
 * the physical address at which certain devices (PCIe, NOR, NAND,
 * etc.) sit can be configured. The configuration takes place through
 * two sets of registers:
 *
 * - One to configure the access of the CPU to the devices. Depending
 *   on the families, there are between 8 and 20 configurable windows,
 *   each can be use to create a physical memory window that maps to a
 *   specific device. Devices are identified by a tuple (target,
 *   attribute).
 *
 * - One to configure the access to the CPU to the SDRAM. There are
 *   either 2 (for Dove) or 4 (for other families) windows to map the
 *   SDRAM into the physical address space.
 *
 * This driver:
 *
 * - Reads out the SDRAM address decoding windows at initialization
 *   time, and fills the mvebu_mbus_dram_info structure with these
 *   informations. The exported function mv_mbus_dram_info() allow
 *   device drivers to get those informations related to the SDRAM
 *   address decoding windows. This is because devices also have their
 *   own windows (configured through registers that are part of each
 *   device register space), and therefore the drivers for Marvell
 *   devices have to configure those device -> SDRAM windows to ensure
 *   that DMA works properly.
 *
 * - Provides an API for platform code or device drivers to
 *   dynamically add or remove address decoding windows for the CPU ->
 *   device accesses. This API is mvebu_mbus_add_window_by_id(),
 *   mvebu_mbus_add_window_remap_by_id() and
 *   mvebu_mbus_del_window().
 *
 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
 *   see the list of CPU -> SDRAM windows and their configuration
 *   (file 'sdram') and the list of CPU -> devices windows and their
 *   configuration (file 'devices').
 */


#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/debugfs.h>
#include <linux/log2.h>
#include <linux/memblock.h>
#include <linux/syscore_ops.h>

/*
 * DDR target is the same on all platforms.
 */

#define TARGET_DDR		0

/*
 * CPU Address Decode Windows registers
 */

#define WIN_CTRL_OFF		0x0000

#define   WIN_CTRL_ENABLE       BIT(0)
/* Only on HW I/O coherency capable platforms */

#define   WIN_CTRL_SYNCBARRIER  BIT(1)

#define   WIN_CTRL_TGT_MASK     0xf0

#define   WIN_CTRL_TGT_SHIFT    4

#define   WIN_CTRL_ATTR_MASK    0xff00

#define   WIN_CTRL_ATTR_SHIFT   8

#define   WIN_CTRL_SIZE_MASK    0xffff0000

#define   WIN_CTRL_SIZE_SHIFT   16

#define WIN_BASE_OFF		0x0004

#define   WIN_BASE_LOW          0xffff0000

#define   WIN_BASE_HIGH         0xf

#define WIN_REMAP_LO_OFF	0x0008

#define   WIN_REMAP_LOW         0xffff0000

#define WIN_REMAP_HI_OFF	0x000c


#define UNIT_SYNC_BARRIER_OFF   0x84

#define   UNIT_SYNC_BARRIER_ALL 0xFFFF


#define ATTR_HW_COHERENCY	(0x1 << 4)


#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))

#define  DDR_BASE_CS_HIGH_MASK  0xf

#define  DDR_BASE_CS_LOW_MASK   0xff000000

#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))

#define  DDR_SIZE_ENABLED       BIT(0)

#define  DDR_SIZE_CS_MASK       0x1c

#define  DDR_SIZE_CS_SHIFT      2

#define  DDR_SIZE_MASK          0xff000000


#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)

/* Relative to mbusbridge_base */

#define MBUS_BRIDGE_CTRL_OFF	0x0

#define MBUS_BRIDGE_BASE_OFF	0x4

/* Maximum number of windows, for all known platforms */

#define MBUS_WINS_MAX           20

struct mvebu_mbus_state;


struct mvebu_mbus_soc_data {
	
unsigned int num_wins;
	
bool has_mbus_bridge;
	
unsigned int (*win_cfg_offset)(const int win);
	
unsigned int (*win_remap_offset)(const int win);
	
void (*setup_cpu_target)(struct mvebu_mbus_state *s);
	
int (*save_cpu_target)(struct mvebu_mbus_state *s,
			       u32 __iomem *store_addr);
	
int (*show_cpu_target)(struct mvebu_mbus_state *s,
			       struct seq_file *seq, void *v);
};

/*
 * Used to store the state of one MBus window accross suspend/resume.
 */

struct mvebu_mbus_win_data {
	
u32 ctrl;
	
u32 base;
	
u32 remap_lo;
	
u32 remap_hi;
};


struct mvebu_mbus_state {
	
void __iomem *mbuswins_base;
	
void __iomem *sdramwins_base;
	
void __iomem *mbusbridge_base;
	
phys_addr_t sdramwins_phys_base;
	
struct dentry *debugfs_root;
	
struct dentry *debugfs_sdram;
	
struct dentry *debugfs_devs;
	
struct resource pcie_mem_aperture;
	
struct resource pcie_io_aperture;
	
const struct mvebu_mbus_soc_data *soc;
	
int hw_io_coherency;

	/* Used during suspend/resume */
	
u32 mbus_bridge_ctrl;
	
u32 mbus_bridge_base;
	
struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
};


static struct mvebu_mbus_state mbus_state;

/*
 * We provide two variants of the mv_mbus_dram_info() function:
 *
 * - The normal one, where the described DRAM ranges may overlap with
 *   the I/O windows, but for which the DRAM ranges are guaranteed to
 *   have a power of two size. Such ranges are suitable for the DMA
 *   masters that only DMA between the RAM and the device, which is
 *   actually all devices except the crypto engines.
 *
 * - The 'nooverlap' one, where the described DRAM ranges are
 *   guaranteed to not overlap with the I/O windows, but for which the
 *   DRAM ranges will not have power of two sizes. They will only be
 *   aligned on a 64 KB boundary, and have a size multiple of 64
 *   KB. Such ranges are suitable for the DMA masters that DMA between
 *   the crypto SRAM (which is mapped through an I/O window) and a
 *   device. This is the case for the crypto engines.
 */


static struct mbus_dram_target_info mvebu_mbus_dram_info;

static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;


const struct mbus_dram_target_info *mv_mbus_dram_info(void) { return &mvebu_mbus_dram_info; }

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EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void) { return &mvebu_mbus_dram_info_nooverlap; }

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EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap); /* Checks whether the given window has remap capability */
static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus, const int win) { return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP; }

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/* * Functions to manipulate the address decoding windows */
static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, int win, int *enabled, u64 *base, u32 *size, u8 *target, u8 *attr, u64 *remap) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 basereg = readl(addr + WIN_BASE_OFF); u32 ctrlreg = readl(addr + WIN_CTRL_OFF); if (!(ctrlreg & WIN_CTRL_ENABLE)) { *enabled = 0; return; } *enabled = 1; *base = ((u64)basereg & WIN_BASE_HIGH) << 32; *base |= (basereg & WIN_BASE_LOW); *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; if (target) *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; if (attr) *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; if (remap) { if (mvebu_mbus_window_is_remappable(mbus, win)) { u32 remap_low, remap_hi; void __iomem *addr_rmp = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF); remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); *remap = ((u64)remap_hi << 32) | remap_low; } else *remap = 0; } }

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static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, int win) { void __iomem *addr; addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); writel(0, addr + WIN_BASE_OFF); writel(0, addr + WIN_CTRL_OFF); if (mvebu_mbus_window_is_remappable(mbus, win)) { addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); writel(0, addr + WIN_REMAP_LO_OFF); writel(0, addr + WIN_REMAP_HI_OFF); } }

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/* Checks whether the given window number is available */
static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, const int win) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 ctrl = readl(addr + WIN_CTRL_OFF); return !(ctrl & WIN_CTRL_ENABLE); }

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/* * Checks whether the given (base, base+size) area doesn't overlap an * existing region */
static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, u8 target, u8 attr) { u64 end = (u64)base + size; int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase, wend; u32 wsize; u8 wtarget, wattr; int enabled; mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, &wtarget, &wattr, NULL); if (!enabled) continue; wend = wbase + wsize; /* * Check if the current window overlaps with the * proposed physical range */ if ((u64)base < wend && end > wbase) return 0; } return 1; }

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static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size) { int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase; u32 wsize; int enabled; mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, NULL, NULL, NULL); if (!enabled) continue; if (base == wbase && size == wsize) return win; } return -ENODEV; }

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static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, int win, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 ctrl, remap_addr; if (!is_power_of_2(size)) { WARN(true, "Invalid MBus window size: 0x%zx\n", size); return -EINVAL; } if ((base & (phys_addr_t)(size - 1)) != 0) { WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base, size); return -EINVAL; } ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | (attr << WIN_CTRL_ATTR_SHIFT) | (target << WIN_CTRL_TGT_SHIFT) | WIN_CTRL_ENABLE; if (mbus->hw_io_coherency) ctrl |= WIN_CTRL_SYNCBARRIER; writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); writel(ctrl, addr + WIN_CTRL_OFF); if (mvebu_mbus_window_is_remappable(mbus, win)) { void __iomem *addr_rmp = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); if (remap == MVEBU_MBUS_NO_REMAP) remap_addr = base; else remap_addr = remap; writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF); writel(0, addr_rmp + WIN_REMAP_HI_OFF); } return 0; }

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static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) { int win; if (remap == MVEBU_MBUS_NO_REMAP) { for (win = 0; win < mbus->soc->num_wins; win++) { if (mvebu_mbus_window_is_remappable(mbus, win)) continue; if (mvebu_mbus_window_is_free(mbus, win)) return mvebu_mbus_setup_window(mbus, win, base, size, remap, target, attr); } } for (win = 0; win < mbus->soc->num_wins; win++) { /* Skip window if need remap but is not supported */ if ((remap != MVEBU_MBUS_NO_REMAP) && !mvebu_mbus_window_is_remappable(mbus, win)) continue; if (mvebu_mbus_window_is_free(mbus, win)) return mvebu_mbus_setup_window(mbus, win, base, size, remap, target, attr); } return -ENOMEM; }

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/* * Debugfs debugging */ /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus, struct seq_file *seq, void *v) { int i; for (i = 0; i < 4; i++) { u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); u64 base; u32 size; if (!(sizereg & DDR_SIZE_ENABLED)) { seq_printf(seq, "[%d] disabled\n", i); continue; } base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; base |= basereg & DDR_BASE_CS_LOW_MASK; size = (sizereg | ~DDR_SIZE_MASK); seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", i, (unsigned long long)base, (unsigned long long)base + size + 1, (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT); } return 0; }

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/* Special function for Dove */
static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus, struct seq_file *seq, void *v) { int i; for (i = 0; i < 2; i++) { u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); u64 base; u32 size; if (!(map & 1)) { seq_printf(seq, "[%d] disabled\n", i); continue; } base = map & 0xff800000; size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", i, (unsigned long long)base, (unsigned long long)base + size, i); } return 0; }

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static int mvebu_sdram_debug_show(struct seq_file *seq, void *v) { struct mvebu_mbus_state *mbus = &mbus_state; return mbus->soc->show_cpu_target(mbus, seq, v); }

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static int mvebu_sdram_debug_open(struct inode *inode, struct file *file) { return single_open(file, mvebu_sdram_debug_show, inode->i_private); }

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static const struct file_operations mvebu_sdram_debug_fops = { .open = mvebu_sdram_debug_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, };
static int mvebu_devs_debug_show(struct seq_file *seq, void *v) { struct mvebu_mbus_state *mbus = &mbus_state; int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase, wremap; u32 wsize; u8 wtarget, wattr; int enabled; mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, &wtarget, &wattr, &wremap); if (!enabled) { seq_printf(seq, "[%02d] disabled\n", win); continue; } seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x", win, (unsigned long long)wbase, (unsigned long long)(wbase + wsize), wtarget, wattr); if (!is_power_of_2(wsize) || ((wbase & (u64)(wsize - 1)) != 0)) seq_puts(seq, " (Invalid base/size!!)"); if (mvebu_mbus_window_is_remappable(mbus, win)) { seq_printf(seq, " (remap %016llx)\n", (unsigned long long)wremap); } else seq_printf(seq, "\n"); } return 0; }

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static int mvebu_devs_debug_open(struct inode *inode, struct file *file) { return single_open(file, mvebu_devs_debug_show, inode->i_private); }

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static const struct file_operations mvebu_devs_debug_fops = { .open = mvebu_devs_debug_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; /* * SoC-specific functions and definitions */
static unsigned int generic_mbus_win_cfg_offset(int win) { return win << 4; }

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static unsigned int armada_370_xp_mbus_win_cfg_offset(int win) { /* The register layout is a bit annoying and the below code * tries to cope with it. * - At offset 0x0, there are the registers for the first 8 * windows, with 4 registers of 32 bits per window (ctrl, * base, remap low, remap high) * - Then at offset 0x80, there is a hole of 0x10 bytes for * the internal registers base address and internal units * sync barrier register. * - Then at offset 0x90, there the registers for 12 * windows, with only 2 registers of 32 bits per window * (ctrl, base). */ if (win < 8) return win << 4; else return 0x90 + ((win - 8) << 3); }

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static unsigned int mv78xx0_mbus_win_cfg_offset(int win) { if (win < 8) return win << 4; else return 0x900 + ((win - 8) << 4); }

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static unsigned int generic_mbus_win_remap_2_offset(int win) { if (win < 2) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; }

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static unsigned int generic_mbus_win_remap_4_offset(int win) { if (win < 4) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; }

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static unsigned int generic_mbus_win_remap_8_offset(int win) { if (win < 8) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; }

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static unsigned int armada_xp_mbus_win_remap_offset(int win) { if (win < 8) return generic_mbus_win_cfg_offset(win); else if (win == 13) return 0xF0 - WIN_REMAP_LO_OFF; else return MVEBU_MBUS_NO_REMAP; }

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/* * Use the memblock information to find the MBus bridge hole in the * physical address space. */
static void __init mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end) { struct memblock_region *r; uint64_t s = 0; for_each_memblock(memory, r) { /* * This part of the memory is above 4 GB, so we don't * care for the MBus bridge hole. */ if (r->base >= 0x100000000ULL) continue; /* * The MBus bridge hole is at the end of the RAM under * the 4 GB limit. */ if (r->base + r->size > s) s = r->base + r->size; } *start = s; *end = 0x100000000ULL; }

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/* * This function fills in the mvebu_mbus_dram_info_nooverlap data * structure, by looking at the mvebu_mbus_dram_info data, and * removing the parts of it that overlap with I/O windows. */
static void __init mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus) { uint64_t mbus_bridge_base, mbus_bridge_end; int cs_nooverlap = 0; int i; mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end); for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) { struct mbus_dram_window *w; u64 base, size, end; w = &mvebu_mbus_dram_info.cs[i]; base = w->base; size = w->size; end = base + size; /* * The CS is fully enclosed inside the MBus bridge * area, so ignore it. */ if (base >= mbus_bridge_base && end <= mbus_bridge_end) continue; /* * Beginning of CS overlaps with end of MBus, raise CS * base address, and shrink its size. */ if (base >= mbus_bridge_base && end > mbus_bridge_end) { size -= mbus_bridge_end - base; base = mbus_bridge_end; } /* * End of CS overlaps with beginning of MBus, shrink * CS size. */ if (base < mbus_bridge_base && end > mbus_bridge_base) size -= end - mbus_bridge_base; w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); if (mbus->hw_io_coherency) w->mbus_attr |= ATTR_HW_COHERENCY; w->base = base; w->size = size; } mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR; mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap; }

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Thomas Petazzoni209100.00%1100.00%
Total209100.00%1100.00%


static void __init mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) { int i; int cs; mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); /* * We only take care of entries for which the chip * select is enabled, and that don't have high base * address bits set (devices can only access the first * 32 bits of the memory). */ if ((size & DDR_SIZE_ENABLED) && !(base & DDR_BASE_CS_HIGH_MASK)) { struct mbus_dram_window *w; w = &mvebu_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); if (mbus->hw_io_coherency) w->mbus_attr |= ATTR_HW_COHERENCY; w->base = base & DDR_BASE_CS_LOW_MASK; w->size = (u64)(size | ~DDR_SIZE_MASK) + 1; } } mvebu_mbus_dram_info.num_cs = cs; }

Contributors

PersonTokensPropCommitsCommitProp
Thomas Petazzoni16397.02%266.67%
Jan Lübbe52.98%133.33%
Total168100.00%3100.00%


static int mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus, u32 __iomem *store_addr) { int i; for (i = 0; i < 4; i++) { u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i), store_addr++); writel(base, store_addr++); writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i), store_addr++); writel(size, store_addr++); } /* We've written 16 words to the store address */ return 16; }

Contributors

PersonTokensPropCommitsCommitProp
Thomas Petazzoni11399.12%266.67%
Ben Dooks10.88%133.33%
Total114100.00%3100.00%


static void __init mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus) { int i; int cs; mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 2; i++) { u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); /* * Chip select enabled? */ if (map &