Release 4.14 drivers/clocksource/timer-atmel-st.c
/*
* linux/arch/arm/mach-at91/at91rm9200_time.c
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/atmel-st.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
static unsigned long last_crtr;
static u32 irqmask;
static struct clock_event_device clkevt;
static struct regmap *regmap_st;
static int timer_latch;
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
* the updates as seen by the CPU don't seem to be strictly monotonic.
* Waiting until we read the same value twice avoids glitching.
*/
static inline unsigned long read_CRTR(void)
{
unsigned int x1, x2;
regmap_read(regmap_st, AT91_ST_CRTR, &x1);
do {
regmap_read(regmap_st, AT91_ST_CRTR, &x2);
if (x1 == x2)
break;
x1 = x2;
} while (1);
return x1;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Andrew Victor | 32 | 55.17% | 1 | 33.33% |
| David Brownell | 13 | 22.41% | 1 | 33.33% |
| Alexandre Belloni | 13 | 22.41% | 1 | 33.33% |
| Total | 58 | 100.00% | 3 | 100.00% |
/*
* IRQ handler for the timer.
*/
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
{
u32 sr;
regmap_read(regmap_st, AT91_ST_SR, &sr);
sr &= irqmask;
/*
* irqs should be disabled here, but as the irq is shared they are only
* guaranteed to be off if the timer irq is registered first.
*/
WARN_ON_ONCE(!irqs_disabled());
/* simulate "oneshot" timer with alarm */
if (sr & AT91_ST_ALMS) {
clkevt.event_handler(&clkevt);
return IRQ_HANDLED;
}
/* periodic mode should handle delayed ticks */
if (sr & AT91_ST_PITS) {
u32 crtr = read_CRTR();
while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
last_crtr += timer_latch;
clkevt.event_handler(&clkevt);
}
return IRQ_HANDLED;
}
/* this irq is shared ... */
return IRQ_NONE;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Andrew Victor | 47 | 43.52% | 3 | 42.86% |
| David Brownell | 40 | 37.04% | 1 | 14.29% |
| Alexandre Belloni | 13 | 12.04% | 2 | 28.57% |
| Uwe Kleine-König | 8 | 7.41% | 1 | 14.29% |
| Total | 108 | 100.00% | 7 | 100.00% |
static u64 read_clk32k(struct clocksource *cs)
{
return read_CRTR();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| David Brownell | 7 | 46.67% | 1 | 25.00% |
| Magnus Damm | 4 | 26.67% | 1 | 25.00% |
| Andrew Victor | 3 | 20.00% | 1 | 25.00% |
| Thomas Gleixner | 1 | 6.67% | 1 | 25.00% |
| Total | 15 | 100.00% | 4 | 100.00% |
static struct clocksource clk32k = {
.name = "32k_counter",
.rating = 150,
.read = read_clk32k,
.mask = CLOCKSOURCE_MASK(20),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void clkdev32k_disable_and_flush_irq(void)
{
unsigned int val;
/* Disable and flush pending timer interrupts */
regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
regmap_read(regmap_st, AT91_ST_SR, &val);
last_crtr = read_CRTR();
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| David Brownell | 23 | 58.97% | 1 | 33.33% |
| Alexandre Belloni | 13 | 33.33% | 1 | 33.33% |
| Viresh Kumar | 3 | 7.69% | 1 | 33.33% |
| Total | 39 | 100.00% | 3 | 100.00% |
static int clkevt32k_shutdown(struct clock_event_device *evt)
{
clkdev32k_disable_and_flush_irq();
irqmask = 0;
regmap_write(regmap_st, AT91_ST_IER, irqmask);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Viresh Kumar | 19 | 63.33% | 1 | 33.33% |
| David Brownell | 8 | 26.67% | 1 | 33.33% |
| Alexandre Belloni | 3 | 10.00% | 1 | 33.33% |
| Total | 30 | 100.00% | 3 | 100.00% |
static int clkevt32k_set_oneshot(struct clock_event_device *dev)
{
clkdev32k_disable_and_flush_irq();
/*
* ALM for oneshot irqs, set by next_event()
* before 32 seconds have passed.
*/
irqmask = AT91_ST_ALMS;
regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
regmap_write(regmap_st, AT91_ST_IER, irqmask);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Viresh Kumar | 24 | 60.00% | 1 | 25.00% |
| David Brownell | 11 | 27.50% | 1 | 25.00% |
| Alexandre Belloni | 3 | 7.50% | 1 | 25.00% |
| Andrew Victor | 2 | 5.00% | 1 | 25.00% |
| Total | 40 | 100.00% | 4 | 100.00% |
static int clkevt32k_set_periodic(struct clock_event_device *dev)
{
clkdev32k_disable_and_flush_irq();
/* PIT for periodic irqs; fixed rate of 1/HZ */
irqmask = AT91_ST_PITS;
regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
regmap_write(regmap_st, AT91_ST_IER, irqmask);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Viresh Kumar | 29 | 72.50% | 1 | 20.00% |
| Alexandre Belloni | 4 | 10.00% | 2 | 40.00% |
| Andrew Victor | 4 | 10.00% | 1 | 20.00% |
| David Brownell | 3 | 7.50% | 1 | 20.00% |
| Total | 40 | 100.00% | 5 | 100.00% |
static int
clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
{
u32 alm;
int status = 0;
unsigned int val;
BUG_ON(delta < 2);
/* The alarm IRQ uses absolute time (now+delta), not the relative
* time (delta) in our calling convention. Like all clockevents
* using such "match" hardware, we have a race to defend against.
*
* Our defense here is to have set up the clockevent device so the
* delta is at least two. That way we never end up writing RTAR
* with the value then held in CRTR ... which would mean the match
* wouldn't trigger until 32 seconds later, after CRTR wraps.
*/
alm = read_CRTR();
/* Cancel any pending alarm; flush any pending IRQ */
regmap_write(regmap_st, AT91_ST_RTAR, alm);
regmap_read(regmap_st, AT91_ST_SR, &val);
/* Schedule alarm by writing RTAR. */
alm += delta;
regmap_write(regmap_st, AT91_ST_RTAR, alm);
return status;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| David Brownell | 50 | 64.94% | 1 | 25.00% |
| Alexandre Belloni | 16 | 20.78% | 1 | 25.00% |
| Andrew Victor | 11 | 14.29% | 2 | 50.00% |
| Total | 77 | 100.00% | 4 | 100.00% |
static struct clock_event_device clkevt = {
.name = "at91_tick",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 150,
.set_next_event = clkevt32k_next_event,
.set_state_shutdown = clkevt32k_shutdown,
.set_state_periodic = clkevt32k_set_periodic,
.set_state_oneshot = clkevt32k_set_oneshot,
.tick_resume = clkevt32k_shutdown,
};
/*
* ST (system timer) module supports both clockevents and clocksource.
*/
static int __init atmel_st_timer_init(struct device_node *node)
{
struct clk *sclk;
unsigned int sclk_rate, val;
int irq, ret;
regmap_st = syscon_node_to_regmap(node);
if (IS_ERR(regmap_st)) {
pr_err("Unable to get regmap\n");
return PTR_ERR(regmap_st);
}
/* Disable all timer interrupts, and clear any pending ones */
regmap_write(regmap_st, AT91_ST_IDR,
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
regmap_read(regmap_st, AT91_ST_SR, &val);
/* Get the interrupts property */
irq = irq_of_parse_and_map(node, 0);
if (!irq) {
pr_err("Unable to get IRQ from DT\n");
return -EINVAL;
}
/* Make IRQs happen for the system timer */
ret = request_irq(irq, at91rm9200_timer_interrupt,
IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
"at91_tick", regmap_st);
if (ret) {
pr_err("Unable to setup IRQ\n");
return ret;
}
sclk = of_clk_get(node, 0);
if (IS_ERR(sclk)) {
pr_err("Unable to get slow clock\n");
return PTR_ERR(sclk);
}
ret = clk_prepare_enable(sclk);
if (ret) {
pr_err("Could not enable slow clock\n");
return ret;
}
sclk_rate = clk_get_rate(sclk);
if (!sclk_rate) {
pr_err("Invalid slow clock rate\n");
return -EINVAL;
}
timer_latch = (sclk_rate + HZ / 2) / HZ;
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
regmap_write(regmap_st, AT91_ST_RTMR, 1);
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&clkevt, sclk_rate,
2, AT91_ST_ALMV);
/* register clocksource */
return clocksource_register_hz(&clk32k, sclk_rate);
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Alexandre Belloni | 142 | 52.99% | 3 | 27.27% |
| Daniel Lezcano | 49 | 18.28% | 1 | 9.09% |
| David Brownell | 26 | 9.70% | 1 | 9.09% |
| Joachim Eastwood | 21 | 7.84% | 1 | 9.09% |
| Andrew Victor | 21 | 7.84% | 2 | 18.18% |
| Uwe Kleine-König | 6 | 2.24% | 1 | 9.09% |
| Russell King | 2 | 0.75% | 1 | 9.09% |
| Rusty Russell | 1 | 0.37% | 1 | 9.09% |
| Total | 268 | 100.00% | 11 | 100.00% |
TIMER_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
atmel_st_timer_init);
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| David Brownell | 260 | 31.48% | 1 | 4.35% |
| Alexandre Belloni | 232 | 28.09% | 4 | 17.39% |
| Andrew Victor | 138 | 16.71% | 6 | 26.09% |
| Viresh Kumar | 92 | 11.14% | 1 | 4.35% |
| Daniel Lezcano | 50 | 6.05% | 2 | 8.70% |
| Joachim Eastwood | 31 | 3.75% | 2 | 8.70% |
| Uwe Kleine-König | 14 | 1.69% | 2 | 8.70% |
| Magnus Damm | 4 | 0.48% | 1 | 4.35% |
| Russell King | 2 | 0.24% | 1 | 4.35% |
| Thomas Gleixner | 2 | 0.24% | 2 | 8.70% |
| Rusty Russell | 1 | 0.12% | 1 | 4.35% |
| Total | 826 | 100.00% | 23 | 100.00% |
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