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Release 4.14 drivers/memory/omap-gpmc.c

Directory: drivers/memory
/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/omap-gpmc.h>
#include <linux/pm_runtime.h>

#include <linux/platform_data/mtd-nand-omap2.h>
#include <linux/platform_data/mtd-onenand-omap2.h>

#include <asm/mach-types.h>


#define	DEVICE_NAME		"omap-gpmc"

/* GPMC register offsets */

#define GPMC_REVISION		0x00

#define GPMC_SYSCONFIG		0x10

#define GPMC_SYSSTATUS		0x14

#define GPMC_IRQSTATUS		0x18

#define GPMC_IRQENABLE		0x1c

#define GPMC_TIMEOUT_CONTROL	0x40

#define GPMC_ERR_ADDRESS	0x44

#define GPMC_ERR_TYPE		0x48

#define GPMC_CONFIG		0x50

#define GPMC_STATUS		0x54

#define GPMC_PREFETCH_CONFIG1	0x1e0

#define GPMC_PREFETCH_CONFIG2	0x1e4

#define GPMC_PREFETCH_CONTROL	0x1ec

#define GPMC_PREFETCH_STATUS	0x1f0

#define GPMC_ECC_CONFIG		0x1f4

#define GPMC_ECC_CONTROL	0x1f8

#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_ECC1_RESULT        0x200

#define GPMC_ECC_BCH_RESULT_0   0x240   
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_1	0x244	
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_2	0x248	
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_3	0x24c	
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_4	0x300	
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_5	0x304	
/* not available on OMAP2 */

#define	GPMC_ECC_BCH_RESULT_6	0x308	
/* not available on OMAP2 */

/* GPMC ECC control settings */

#define GPMC_ECC_CTRL_ECCCLEAR		0x100

#define GPMC_ECC_CTRL_ECCDISABLE	0x000

#define GPMC_ECC_CTRL_ECCREG1		0x001

#define GPMC_ECC_CTRL_ECCREG2		0x002

#define GPMC_ECC_CTRL_ECCREG3		0x003

#define GPMC_ECC_CTRL_ECCREG4		0x004

#define GPMC_ECC_CTRL_ECCREG5		0x005

#define GPMC_ECC_CTRL_ECCREG6		0x006

#define GPMC_ECC_CTRL_ECCREG7		0x007

#define GPMC_ECC_CTRL_ECCREG8		0x008

#define GPMC_ECC_CTRL_ECCREG9		0x009


#define GPMC_CONFIG_LIMITEDADDRESS		BIT(1)


#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS	BIT(0)


#define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)

#define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)

#define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)

#define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)

#define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)

#define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)


#define GPMC_CS0_OFFSET		0x60

#define GPMC_CS_SIZE		0x30

#define	GPMC_BCH_SIZE		0x10

/*
 * The first 1MB of GPMC address space is typically mapped to
 * the internal ROM. Never allocate the first page, to
 * facilitate bug detection; even if we didn't boot from ROM.
 * As GPMC minimum partition size is 16MB we can only start from
 * there.
 */

#define GPMC_MEM_START		0x1000000

#define GPMC_MEM_END		0x3FFFFFFF


#define GPMC_CHUNK_SHIFT	24		
/* 16 MB */

#define GPMC_SECTION_SHIFT	28		
/* 128 MB */


#define CS_NUM_SHIFT		24

#define ENABLE_PREFETCH		(0x1 << 7)

#define DMA_MPU_MODE		2


#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)

#define	GPMC_REVISION_MINOR(l)		(l & 0xf)


#define	GPMC_HAS_WR_ACCESS		0x1

#define	GPMC_HAS_WR_DATA_MUX_BUS	0x2

#define	GPMC_HAS_MUX_AAD		0x4


#define GPMC_NR_WAITPINS		4


#define GPMC_CS_CONFIG1		0x00

#define GPMC_CS_CONFIG2		0x04

#define GPMC_CS_CONFIG3		0x08

#define GPMC_CS_CONFIG4		0x0c

#define GPMC_CS_CONFIG5		0x10

#define GPMC_CS_CONFIG6		0x14

#define GPMC_CS_CONFIG7		0x18

#define GPMC_CS_NAND_COMMAND	0x1c

#define GPMC_CS_NAND_ADDRESS	0x20

#define GPMC_CS_NAND_DATA	0x24

/* Control Commands */

#define GPMC_CONFIG_RDY_BSY	0x00000001

#define GPMC_CONFIG_DEV_SIZE	0x00000002

#define GPMC_CONFIG_DEV_TYPE	0x00000003


#define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)

#define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)

#define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)

#define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)

#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)

#define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)

#define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)

#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
/** CLKACTIVATIONTIME Max Ticks */

#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2

#define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
/** ATTACHEDDEVICEPAGELENGTH Max Value */

#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2

#define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)

#define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)

#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
/** WAITMONITORINGTIME Max Ticks */

#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2

#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)

#define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)

#define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
/** DEVICESIZE Max Value */

#define GPMC_CONFIG1_DEVICESIZE_MAX     1

#define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)

#define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)

#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)

#define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)

#define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)

#define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))

#define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))

#define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))

#define GPMC_CONFIG7_CSVALID		(1 << 6)


#define GPMC_CONFIG7_BASEADDRESS_MASK	0x3f

#define GPMC_CONFIG7_CSVALID_MASK	BIT(6)

#define GPMC_CONFIG7_MASKADDRESS_OFFSET	8

#define GPMC_CONFIG7_MASKADDRESS_MASK	(0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
/* All CONFIG7 bits except reserved bits */

#define GPMC_CONFIG7_MASK		(GPMC_CONFIG7_BASEADDRESS_MASK | \
                                         GPMC_CONFIG7_CSVALID_MASK |     \
                                         GPMC_CONFIG7_MASKADDRESS_MASK)


#define GPMC_DEVICETYPE_NOR		0

#define GPMC_DEVICETYPE_NAND		2

#define GPMC_CONFIG_WRITEPROTECT	0x00000010

#define WR_RD_PIN_MONITORING		0x00600000

/* ECC commands */

#define GPMC_ECC_READ		0 
/* Reset Hardware ECC for read */

#define GPMC_ECC_WRITE		1 
/* Reset Hardware ECC for write */

#define GPMC_ECC_READSYN	2 
/* Reset before syndrom is read back */


#define	GPMC_NR_NAND_IRQS	2 
/* number of NAND specific IRQs */


enum gpmc_clk_domain {
	
GPMC_CD_FCLK,
	
GPMC_CD_CLK
};


struct gpmc_cs_data {
	
const char *name;


#define GPMC_CS_RESERVED	(1 << 0)
	
u32 flags;

	
struct resource mem;
};

/* Structure to save gpmc cs context */

struct gpmc_cs_config {
	
u32 config1;
	
u32 config2;
	
u32 config3;
	
u32 config4;
	
u32 config5;
	
u32 config6;
	
u32 config7;
	
int is_valid;
};

/*
 * Structure to save/restore gpmc context
 * to support core off on OMAP3
 */

struct omap3_gpmc_regs {
	
u32 sysconfig;
	
u32 irqenable;
	
u32 timeout_ctrl;
	
u32 config;
	
u32 prefetch_config1;
	
u32 prefetch_config2;
	
u32 prefetch_control;
	
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};


struct gpmc_device {
	
struct device *dev;
	
int irq;
	
struct irq_chip irq_chip;
	
struct gpio_chip gpio_chip;
	
int nirqs;
};


static struct irq_domain *gpmc_irq_domain;


static struct resource	gpmc_mem_root;

static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
/* Define chip-selects as reserved by default until probe completes */

static unsigned int gpmc_cs_num = GPMC_CS_NUM;

static unsigned int gpmc_nr_waitpins;


static resource_size_t phys_base, mem_size;

static unsigned gpmc_capability;

static void __iomem *gpmc_base;


static struct clk *gpmc_l3_clk;

static irqreturn_t gpmc_handle_irq(int irq, void *dev);


static void gpmc_write_reg(int idx, u32 val) { writel_relaxed(val, gpmc_base + idx); }

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static u32 gpmc_read_reg(int idx) { return readl_relaxed(gpmc_base + idx); }

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void gpmc_cs_write_reg(int cs, int idx, u32 val) { void __iomem *reg_addr; reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; writel_relaxed(val, reg_addr); }

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static u32 gpmc_cs_read_reg(int cs, int idx) { void __iomem *reg_addr; reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; return readl_relaxed(reg_addr); }

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/* TODO: Add support for gpmc_fck to clock framework and use it */
static unsigned long gpmc_get_fclk_period(void) { unsigned long rate = clk_get_rate(gpmc_l3_clk); rate /= 1000; rate = 1000000000 / rate; /* In picoseconds */ return rate; }

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/** * gpmc_get_clk_period - get period of selected clock domain in ps * @cs Chip Select Region. * @cd Clock Domain. * * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup * prior to calling this function with GPMC_CD_CLK. */
static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) { unsigned long tick_ps = gpmc_get_fclk_period(); u32 l; int div; switch (cd) { case GPMC_CD_CLK: /* get current clk divider */ l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); div = (l & 0x03) + 1; /* get GPMC_CLK period */ tick_ps *= div; break; case GPMC_CD_FCLK: /* FALL-THROUGH */ default: break; } return tick_ps; }

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static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, enum gpmc_clk_domain cd) { unsigned long tick_ps; /* Calculate in picosecs to yield more exact results */ tick_ps = gpmc_get_clk_period(cs, cd); return (time_ns * 1000 + tick_ps - 1) / tick_ps; }

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static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) { return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); }

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static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) { unsigned long tick_ps; /* Calculate in picosecs to yield more exact results */ tick_ps = gpmc_get_fclk_period(); return (time_ps + tick_ps - 1) / tick_ps; }

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static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, enum gpmc_clk_domain cd) { return ticks * gpmc_get_clk_period(cs, cd) / 1000; }

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unsigned int gpmc_ticks_to_ns(unsigned int ticks) { return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); }

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static unsigned int gpmc_ticks_to_ps(unsigned int ticks) { return ticks * gpmc_get_fclk_period(); }

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static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) { unsigned long ticks = gpmc_ps_to_ticks(time_ps); return ticks * gpmc_get_fclk_period(); }

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static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) { u32 l; l = gpmc_cs_read_reg(cs, reg); if (value) l |= mask; else l &= ~mask; gpmc_cs_write_reg(cs, reg, l); }

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static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) { gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_TIME_PARA_GRAN, p->time_para_granularity); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, p->cycle2cyclesamecsen); gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, p->cycle2cyclediffcsen); }

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#ifdef CONFIG_OMAP_GPMC_DEBUG /** * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. * @cs: Chip Select Region * @reg: GPMC_CS_CONFIGn register offset. * @st_bit: Start Bit * @end_bit: End Bit. Must be >= @st_bit. * @ma:x Maximum parameter value (before optional @shift). * If 0, maximum is as high as @st_bit and @end_bit allow. * @name: DTS node name, w/o "gpmc," * @cd: Clock Domain of timing parameter. * @shift: Parameter value left shifts @shift, which is then printed instead of value. * @raw: Raw Format Option. * raw format: gpmc,name = <value> * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/ * Where x ns -- y ns result in the same tick value. * When @max is exceeded, "invalid" is printed inside comment. * @noval: Parameter values equal to 0 are not printed. * @return: Specified timing parameter (after optional @shift). * */
static int get_gpmc_timing_reg( /* timing specifiers */ int cs, int reg, int st_bit, int end_bit, int max, const char *name, const enum gpmc_clk_domain cd, /* value transform */ int shift, /* format specifiers */ bool raw, bool noval) { u32 l; int nr_bits; int mask; bool invalid; l = gpmc_cs_read_reg(cs, reg); nr_bits = end_bit - st_bit + 1; mask = (1 << nr_bits) - 1; l = (l >> st_bit) & mask; if (!max) max = mask; invalid = l > max; if (shift) l = (shift << l); if (noval && (l == 0)) return 0; if (!raw) { /* DTS tick format for timings in ns */ unsigned int time_ns; unsigned int time_ns_min = 0; if (l) time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", name, time_ns, time_ns_min, time_ns, l, invalid ? "; invalid " : " "); } else { /* raw format */ pr_info("gpmc,%s = <%u>;%s\n", name, l, invalid ? " /* invalid */" : ""); } return l; }

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#define GPMC_PRINT_CONFIG(cs, config) \ pr_info("cs%i %s: 0x%08x\n", cs, #config, \ gpmc_cs_read_reg(cs, config)) #define GPMC_GET_RAW(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) #define GPMC_GET_TICKS(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
static void gpmc_show_regs(int cs, const char *desc) { pr_info("gpmc cs%i %s:\n", cs, desc); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); }

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/* * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, * see commit c9fb809. */
static void gpmc_cs_show_timings(int cs, const char *desc) { gpmc_show_regs(cs, desc); pr_info("gpmc cs%i access configuration:\n", cs); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, "burst-length"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); pr_info("gpmc cs%i timings configuration:\n", cs); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); if (gpmc_capability & GPMC_HAS_MUX_AAD) { GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, "adv-aad-mux-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, "adv-aad-mux-wr-off-ns"); } GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); if (gpmc_capability & GPMC_HAS_MUX_AAD) { GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); } GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, GPMC_CONFIG1_WAITMONITORINGTIME_MAX, "wait-monitoring-ns", GPMC_CD_CLK); GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, "clk-activation-ns", GPMC_CD_FCLK); GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); }

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PersonTokensPropCommitsCommitProp
Tony Lindgren38972.04%233.33%
Neil Armstrong7113.15%116.67%
Afzal Mohammed6512.04%116.67%
Robert ABEL152.78%233.33%
Total540100.00%6100.00%

#else
static inline void gpmc_cs_show_timings(int cs, const char *desc) { }

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PersonTokensPropCommitsCommitProp
Tony Lindgren964.29%150.00%
Juha Yrjölä535.71%150.00%
Total14100.00%2100.00%

#endif /** * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER * prior to calling this function with @cd equal to GPMC_CD_CLK. * * @cs: Chip Select Region. * @reg: GPMC_CS_CONFIGn register offset. * @st_bit: Start Bit * @end_bit: End Bit. Must be >= @st_bit. * @max: Maximum parameter value. * If 0, maximum is as high as @st_bit and @end_bit allow. * @time: Timing parameter in ns. * @cd: Timing parameter clock domain. * @name: Timing parameter name. * @return: 0 on success, -1 on error. */
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, int time, enum gpmc_clk_domain cd, const char *name) { u32 l; int ticks, mask, nr_bits; if (time == 0) ticks = 0; else ticks = gpmc_ns_to_clk_ticks(time, cs, cd); nr_bits = end_bit - st_bit + 1; mask = (1 << nr_bits) - 1; if (!max) max = mask; if (ticks > max) { pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", __func__, cs, name, time, ticks, max); return -1; } l = gpmc_cs_read_reg(cs, reg); #ifdef CONFIG_OMAP_GPMC_DEBUG pr_info( "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, (l >> st_bit) & mask, time); #endif l &= ~(mask << st_bit); l |= ticks << st_bit; gpmc_cs_write_reg(cs, reg, l); return 0; }

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PersonTokensPropCommitsCommitProp
Juha Yrjölä12363.40%112.50%
Robert ABEL3216.49%450.00%
Roger Quadros2211.34%112.50%
David Brownell168.25%112.50%
Tony Lindgren10.52%112.50%
Total194100.00%8100.00%

#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ t->field, (cd), #field) < 0) \ return -1 #define GPMC_SET_ONE(reg, st, end, field) \ GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) /** * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. * read --> don't sample bus too early * write --> data is longer on bus * * Formula: * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) * / waitmonitoring_ticks) * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by * div <= 0 check. * * @wait_monitoring: WAITMONITORINGTIME in ns. * @return: -1 on failure to scale, else proper divider > 0. */
static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) { int div = gpmc_ns_to_ticks(wait_monitoring); div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; if (div > 4) return -1; if (div <= 0) div = 1; return div; }

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PersonTokensPropCommitsCommitProp
Robert ABEL3670.59%150.00%
Juha Yrjölä1529.41%150.00%
Total51100.00%2100.00%

/** * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. * @sync_clk: GPMC_CLK period in ps. * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. * Else, returns -1. */
int gpmc_calc_divider(unsigned int sync_clk) { int div = gpmc_ps_to_ticks(sync_clk); if (div > 4) return -1; if (div <= 0) div = 1; return div; }

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Juha Yrjölä2357.50%133.33%
Robert ABEL1640.00%133.33%
David Brownell12.50%133.33%
Total40100.00%3100.00%

/** * gpmc_cs_set_timings - program timing parameters for Chip Select Region. * @cs: Chip Select Region. * @t: GPMC timing parameters. * @s: GPMC timing settings. * @return: 0 on success, -1 on error. */
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, const struct gpmc_settings *s) { int div; u32 l; div = gpmc_calc_divider(t->sync_clk); if (div < 0) return div; /* * See if we need to change the divider for waitmonitoringtime. * * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for * pure asynchronous accesses, i.e. both read and write asynchronous. * However, only do so if WAITMONITORINGTIME is actually used, i.e. * either WAITREADMONITORING or WAITWRITEMONITORING is set. * * This statement must not change div to scale async WAITMONITORINGTIME * to protect mixed synchronous and asynchronous accesses. * * We raise an error later if WAITMONITORINGTIME does not fit. */ if (!s->sync_read && !s->sync_write && (s->wait_on_read || s->wait_on_write) ) { div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); if (div < 0) { pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", __func__, t->wait_monitoring ); return -1; } } GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3,