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Release 4.14 drivers/pwm/pwm-rockchip.c

Directory: drivers/pwm
/*
 * PWM driver for Rockchip SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>


#define PWM_CTRL_TIMER_EN	(1 << 0)

#define PWM_CTRL_OUTPUT_EN	(1 << 3)


#define PWM_ENABLE		(1 << 0)

#define PWM_CONTINUOUS		(1 << 1)

#define PWM_DUTY_POSITIVE	(1 << 3)

#define PWM_DUTY_NEGATIVE	(0 << 3)

#define PWM_INACTIVE_NEGATIVE	(0 << 4)

#define PWM_INACTIVE_POSITIVE	(1 << 4)

#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)

#define PWM_OUTPUT_LEFT		(0 << 5)

#define PWM_LOCK_EN		(1 << 6)

#define PWM_LP_DISABLE		(0 << 8)


struct rockchip_pwm_chip {
	
struct pwm_chip chip;
	
struct clk *clk;
	
struct clk *pclk;
	
const struct rockchip_pwm_data *data;
	
void __iomem *base;
};


struct rockchip_pwm_regs {
	
unsigned long duty;
	
unsigned long period;
	
unsigned long cntr;
	
unsigned long ctrl;
};


struct rockchip_pwm_data {
	
struct rockchip_pwm_regs regs;
	
unsigned int prescaler;
	
bool supports_polarity;
	
bool supports_lock;
	
u32 enable_conf;
};


static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) { return container_of(c, struct rockchip_pwm_chip, chip); }

Contributors

PersonTokensPropCommitsCommitProp
Beniamino Galvani25100.00%1100.00%
Total25100.00%1100.00%


static void rockchip_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); u32 enable_conf = pc->data->enable_conf; unsigned long clk_rate; u64 tmp; u32 val; int ret; ret = clk_enable(pc->pclk); if (ret) return; clk_rate = clk_get_rate(pc->clk); tmp = readl_relaxed(pc->base + pc->data->regs.period); tmp *= pc->data->prescaler * NSEC_PER_SEC; state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); tmp = readl_relaxed(pc->base + pc->data->regs.duty); tmp *= pc->data->prescaler * NSEC_PER_SEC; state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); val = readl_relaxed(pc->base + pc->data->regs.ctrl); if (pc->data->supports_polarity) state->enabled = ((val & enable_conf) != enable_conf) ? false : true; else state->enabled = ((val & enable_conf) == enable_conf) ? true : false; if (pc->data->supports_polarity) { if (!(val & PWM_DUTY_POSITIVE)) state->polarity = PWM_POLARITY_INVERSED; } clk_disable(pc->pclk); }

Contributors

PersonTokensPropCommitsCommitProp
Boris Brezillon15964.63%133.33%
David Wu8735.37%266.67%
Total246100.00%3100.00%


static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); unsigned long period, duty; u64 clk_rate, div; u32 ctrl; clk_rate = clk_get_rate(pc->clk); /* * Since period and duty cycle registers have a width of 32 * bits, every possible input period can be obtained using the * default prescaler value for all practical clock rate values. */ div = clk_rate * state->period; period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); div = clk_rate * state->duty_cycle; duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); /* * Lock the period and duty of previous configuration, then * change the duty and period, that would not be effective. */ ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); if (pc->data->supports_lock) { ctrl |= PWM_LOCK_EN; writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); } writel(period, pc->base + pc->data->regs.period); writel(duty, pc->base + pc->data->regs.duty); if (pc->data->supports_polarity) { ctrl &= ~PWM_POLARITY_MASK; if (state->polarity == PWM_POLARITY_INVERSED) ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; else ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; } /* * Unlock and set polarity at the same time, * the configuration of duty, period and polarity * would be effective together at next period. */ if (pc->data->supports_lock) ctrl &= ~PWM_LOCK_EN; writel(ctrl, pc->base + pc->data->regs.ctrl); }

Contributors

PersonTokensPropCommitsCommitProp
David Wu13553.78%350.00%
Beniamino Galvani8835.06%116.67%
Caesar Wang228.76%116.67%
Boris Brezillon62.39%116.67%
Total251100.00%6100.00%


static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, bool enable) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); u32 enable_conf = pc->data->enable_conf; int ret; u32 val; if (enable) { ret = clk_enable(pc->clk); if (ret) return ret; } val = readl_relaxed(pc->base + pc->data->regs.ctrl); if (enable) val |= enable_conf; else val &= ~enable_conf; writel_relaxed(val, pc->base + pc->data->regs.ctrl); if (!enable) clk_disable(pc->clk); return 0; }

Contributors

PersonTokensPropCommitsCommitProp
David Wu12496.12%360.00%
Caesar Wang32.33%120.00%
Beniamino Galvani21.55%120.00%
Total129100.00%5100.00%


static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); struct pwm_state curstate; bool enabled; int ret = 0; ret = clk_enable(pc->pclk); if (ret) return ret; pwm_get_state(pwm, &curstate); enabled = curstate.enabled; if (state->polarity != curstate.polarity && enabled && !pc->data->supports_lock) { ret = rockchip_pwm_enable(chip, pwm, false); if (ret) goto out; enabled = false; } rockchip_pwm_config(chip, pwm, state); if (state->enabled != enabled) { ret = rockchip_pwm_enable(chip, pwm, state->enabled); if (ret) goto out; } /* * Update the state with the real hardware, which can differ a bit * because of period/duty_cycle approximation. */ rockchip_pwm_get_state(chip, pwm, state); out: clk_disable(pc->pclk); return ret; }

Contributors

PersonTokensPropCommitsCommitProp
David Wu10257.63%555.56%
Boris Brezillon5128.81%111.11%
Beniamino Galvani169.04%111.11%
Caesar Wang42.26%111.11%
Douglas Anderson42.26%111.11%
Total177100.00%9100.00%

static const struct pwm_ops rockchip_pwm_ops = { .get_state = rockchip_pwm_get_state, .apply = rockchip_pwm_apply, .owner = THIS_MODULE, }; static const struct rockchip_pwm_data pwm_data_v1 = { .regs = { .duty = 0x04, .period = 0x08, .cntr = 0x00, .ctrl = 0x0c, }, .prescaler = 2, .supports_polarity = false, .supports_lock = false, .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, }; static const struct rockchip_pwm_data pwm_data_v2 = { .regs = { .duty = 0x08, .period = 0x04, .cntr = 0x00, .ctrl = 0x0c, }, .prescaler = 1, .supports_polarity = true, .supports_lock = false, .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | PWM_CONTINUOUS, }; static const struct rockchip_pwm_data pwm_data_vop = { .regs = { .duty = 0x08, .period = 0x04, .cntr = 0x0c, .ctrl = 0x00, }, .prescaler = 1, .supports_polarity = true, .supports_lock = false, .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | PWM_CONTINUOUS, }; static const struct rockchip_pwm_data pwm_data_v3 = { .regs = { .duty = 0x08, .period = 0x04, .cntr = 0x00, .ctrl = 0x0c, }, .prescaler = 1, .supports_polarity = true, .supports_lock = true, .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | PWM_CONTINUOUS, }; static const struct of_device_id rockchip_pwm_dt_ids[] = { { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
static int rockchip_pwm_probe(struct platform_device *pdev) { const struct of_device_id *id; struct rockchip_pwm_chip *pc; struct resource *r; int ret, count; id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); if (!id) return -EINVAL; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); if (!pc) return -ENOMEM; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); pc->base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(pc->base)) return PTR_ERR(pc->base); pc->clk = devm_clk_get(&pdev->dev, "pwm"); if (IS_ERR(pc->clk)) { pc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(pc->clk)) { ret = PTR_ERR(pc->clk); if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret); return ret; } } count = of_count_phandle_with_args(pdev->dev.of_node, "clocks", "#clock-cells"); if (count == 2) pc->pclk = devm_clk_get(&pdev->dev, "pclk"); else pc->pclk = pc->clk; if (IS_ERR(pc->pclk)) { ret = PTR_ERR(pc->pclk); if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret); return ret; } ret = clk_prepare_enable(pc->clk); if (ret) { dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret); return ret; } ret = clk_prepare(pc->pclk); if (ret) { dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret); goto err_clk; } platform_set_drvdata(pdev, pc); pc->data = id->data; pc->chip.dev = &pdev->dev; pc->chip.ops = &rockchip_pwm_ops; pc->chip.base = -1; pc->chip.npwm = 1; if (pc->data->supports_polarity) { pc->chip.of_xlate = of_pwm_xlate_with_flags; pc->chip.of_pwm_n_cells = 3; } ret = pwmchip_add(&pc->chip); if (ret < 0) { clk_unprepare(pc->clk); dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); goto err_pclk; } /* Keep the PWM clk enabled if the PWM appears to be up and running. */ if (!pwm_is_enabled(pc->chip.pwms)) clk_disable(pc->clk); return 0; err_pclk: clk_unprepare(pc->pclk); err_clk: clk_disable_unprepare(pc->clk); return ret; }

Contributors

PersonTokensPropCommitsCommitProp
Beniamino Galvani22043.05%114.29%
David Wu20940.90%228.57%
Caesar Wang356.85%114.29%
Douglas Anderson254.89%114.29%
Boris Brezillon224.31%228.57%
Total511100.00%7100.00%


static int rockchip_pwm_remove(struct platform_device *pdev) { struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); /* * Disable the PWM clk before unpreparing it if the PWM device is still * running. This should only happen when the last PWM user left it * enabled, or when nobody requested a PWM that was previously enabled * by the bootloader. * * FIXME: Maybe the core should disable all PWM devices in * pwmchip_remove(). In this case we'd only have to call * clk_unprepare() after pwmchip_remove(). * */ if (pwm_is_enabled(pc->chip.pwms)) clk_disable(pc->clk); clk_unprepare(pc->pclk); clk_unprepare(pc->clk); return pwmchip_remove(&pc->chip); }

Contributors

PersonTokensPropCommitsCommitProp
Beniamino Galvani3758.73%133.33%
Boris Brezillon1930.16%133.33%
David Wu711.11%133.33%
Total63100.00%3100.00%

static struct platform_driver rockchip_pwm_driver = { .driver = { .name = "rockchip-pwm", .of_match_table = rockchip_pwm_dt_ids, }, .probe = rockchip_pwm_probe, .remove = rockchip_pwm_remove, }; module_platform_driver(rockchip_pwm_driver); MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); MODULE_DESCRIPTION("Rockchip SoC PWM driver"); MODULE_LICENSE("GPL v2");

Overall Contributors

PersonTokensPropCommitsCommitProp
David Wu79241.10%750.00%
Beniamino Galvani49425.64%17.14%
Caesar Wang30615.88%17.14%
Boris Brezillon28214.63%428.57%
Douglas Anderson532.75%17.14%
Total1927100.00%14100.00%
Directory: drivers/pwm
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