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Release 4.14 drivers/rapidio/devices/tsi721_dma.c

/*
 * DMA Engine support for Tsi721 PCIExpress-to-SRIO bridge
 *
 * Copyright (c) 2011-2014 Integrated Device Technology, Inc.
 * Alexandre Bounine <alexandre.bounine@idt.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */

#include <linux/io.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/kfifo.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include "../../dma/dmaengine.h"

#include "tsi721.h"

#ifdef CONFIG_PCI_MSI
static irqreturn_t tsi721_bdma_msix(int irq, void *ptr);
#endif
static int tsi721_submit_sg(struct tsi721_tx_desc *desc);


static unsigned int dma_desc_per_channel = 128;
module_param(dma_desc_per_channel, uint, S_IRUGO);
MODULE_PARM_DESC(dma_desc_per_channel,
		 "Number of DMA descriptors per channel (default: 128)");


static unsigned int dma_txqueue_sz = 16;
module_param(dma_txqueue_sz, uint, S_IRUGO);
MODULE_PARM_DESC(dma_txqueue_sz,
		 "DMA Transactions Queue Size (default: 16)");


static u8 dma_sel = 0x7f;
module_param(dma_sel, byte, S_IRUGO);
MODULE_PARM_DESC(dma_sel,
		 "DMA Channel Selection Mask (default: 0x7f = all)");


static inline struct tsi721_bdma_chan *to_tsi721_chan(struct dma_chan *chan) { return container_of(chan, struct tsi721_bdma_chan, dchan); }

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static inline struct tsi721_device *to_tsi721(struct dma_device *ddev) { return container_of(ddev, struct rio_mport, dma)->priv; }

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static inline struct tsi721_tx_desc *to_tsi721_desc(struct dma_async_tx_descriptor *txd) { return container_of(txd, struct tsi721_tx_desc, txd); }

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static int tsi721_bdma_ch_init(struct tsi721_bdma_chan *bdma_chan, int bd_num) { struct tsi721_dma_desc *bd_ptr; struct device *dev = bdma_chan->dchan.device->dev; u64 *sts_ptr; dma_addr_t bd_phys; dma_addr_t sts_phys; int sts_size; #ifdef CONFIG_PCI_MSI struct tsi721_device *priv = to_tsi721(bdma_chan->dchan.device); #endif tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d", bdma_chan->id); /* * Allocate space for DMA descriptors * (add an extra element for link descriptor) */ bd_ptr = dma_zalloc_coherent(dev, (bd_num + 1) * sizeof(struct tsi721_dma_desc), &bd_phys, GFP_ATOMIC); if (!bd_ptr) return -ENOMEM; bdma_chan->bd_num = bd_num; bdma_chan->bd_phys = bd_phys; bdma_chan->bd_base = bd_ptr; tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d descriptors @ %p (phys = %pad)", bdma_chan->id, bd_ptr, &bd_phys); /* Allocate space for descriptor status FIFO */ sts_size = ((bd_num + 1) >= TSI721_DMA_MINSTSSZ) ? (bd_num + 1) : TSI721_DMA_MINSTSSZ; sts_size = roundup_pow_of_two(sts_size); sts_ptr = dma_zalloc_coherent(dev, sts_size * sizeof(struct tsi721_dma_sts), &sts_phys, GFP_ATOMIC); if (!sts_ptr) { /* Free space allocated for DMA descriptors */ dma_free_coherent(dev, (bd_num + 1) * sizeof(struct tsi721_dma_desc), bd_ptr, bd_phys); bdma_chan->bd_base = NULL; return -ENOMEM; } bdma_chan->sts_phys = sts_phys; bdma_chan->sts_base = sts_ptr; bdma_chan->sts_size = sts_size; tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d desc status FIFO @ %p (phys = %pad) size=0x%x", bdma_chan->id, sts_ptr, &sts_phys, sts_size); /* Initialize DMA descriptors ring using added link descriptor */ bd_ptr[bd_num].type_id = cpu_to_le32(DTYPE3 << 29); bd_ptr[bd_num].next_lo = cpu_to_le32((u64)bd_phys & TSI721_DMAC_DPTRL_MASK); bd_ptr[bd_num].next_hi = cpu_to_le32((u64)bd_phys >> 32); /* Setup DMA descriptor pointers */ iowrite32(((u64)bd_phys >> 32), bdma_chan->regs + TSI721_DMAC_DPTRH); iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK), bdma_chan->regs + TSI721_DMAC_DPTRL); /* Setup descriptor status FIFO */ iowrite32(((u64)sts_phys >> 32), bdma_chan->regs + TSI721_DMAC_DSBH); iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK), bdma_chan->regs + TSI721_DMAC_DSBL); iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size), bdma_chan->regs + TSI721_DMAC_DSSZ); /* Clear interrupt bits */ iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INT); ioread32(bdma_chan->regs + TSI721_DMAC_INT); #ifdef CONFIG_PCI_MSI /* Request interrupt service if we are in MSI-X mode */ if (priv->flags & TSI721_USING_MSIX) { int rc, idx; idx = TSI721_VECT_DMA0_DONE + bdma_chan->id; rc = request_irq(priv->msix[idx].vector, tsi721_bdma_msix, 0, priv->msix[idx].irq_name, (void *)bdma_chan); if (rc) { tsi_debug(DMA, &bdma_chan->dchan.dev->device, "Unable to get MSI-X for DMAC%d-DONE", bdma_chan->id); goto err_out; } idx = TSI721_VECT_DMA0_INT + bdma_chan->id; rc = request_irq(priv->msix[idx].vector, tsi721_bdma_msix, 0, priv->msix[idx].irq_name, (void *)bdma_chan); if (rc) { tsi_debug(DMA, &bdma_chan->dchan.dev->device, "Unable to get MSI-X for DMAC%d-INT", bdma_chan->id); free_irq( priv->msix[TSI721_VECT_DMA0_DONE + bdma_chan->id].vector, (void *)bdma_chan); } err_out: if (rc) { /* Free space allocated for DMA descriptors */ dma_free_coherent(dev, (bd_num + 1) * sizeof(struct tsi721_dma_desc), bd_ptr, bd_phys); bdma_chan->bd_base = NULL; /* Free space allocated for status descriptors */ dma_free_coherent(dev, sts_size * sizeof(struct tsi721_dma_sts), sts_ptr, sts_phys); bdma_chan->sts_base = NULL; return -EIO; } } #endif /* CONFIG_PCI_MSI */ /* Toggle DMA channel initialization */ iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL); ioread32(bdma_chan->regs + TSI721_DMAC_CTL); bdma_chan->wr_count = bdma_chan->wr_count_next = 0; bdma_chan->sts_rdptr = 0; udelay(10); return 0; }

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static int tsi721_bdma_ch_free(struct tsi721_bdma_chan *bdma_chan) { u32 ch_stat; #ifdef CONFIG_PCI_MSI struct tsi721_device *priv = to_tsi721(bdma_chan->dchan.device); #endif if (bdma_chan->bd_base == NULL) return 0; /* Check if DMA channel still running */ ch_stat = ioread32(bdma_chan->regs + TSI721_DMAC_STS); if (ch_stat & TSI721_DMAC_STS_RUN) return -EFAULT; /* Put DMA channel into init state */ iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL); #ifdef CONFIG_PCI_MSI if (priv->flags & TSI721_USING_MSIX) { free_irq(priv->msix[TSI721_VECT_DMA0_DONE + bdma_chan->id].vector, (void *)bdma_chan); free_irq(priv->msix[TSI721_VECT_DMA0_INT + bdma_chan->id].vector, (void *)bdma_chan); } #endif /* CONFIG_PCI_MSI */ /* Free space allocated for DMA descriptors */ dma_free_coherent(bdma_chan->dchan.device->dev, (bdma_chan->bd_num + 1) * sizeof(struct tsi721_dma_desc), bdma_chan->bd_base, bdma_chan->bd_phys); bdma_chan->bd_base = NULL; /* Free space allocated for status FIFO */ dma_free_coherent(bdma_chan->dchan.device->dev, bdma_chan->sts_size * sizeof(struct tsi721_dma_sts), bdma_chan->sts_base, bdma_chan->sts_phys); bdma_chan->sts_base = NULL; return 0; }

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static void tsi721_bdma_interrupt_enable(struct tsi721_bdma_chan *bdma_chan, int enable) { if (enable) { /* Clear pending BDMA channel interrupts */ iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INT); ioread32(bdma_chan->regs + TSI721_DMAC_INT); /* Enable BDMA channel interrupts */ iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INTE); } else { /* Disable BDMA channel interrupts */ iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE); /* Clear pending BDMA channel interrupts */ iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INT); } }

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static bool tsi721_dma_is_idle(struct tsi721_bdma_chan *bdma_chan) { u32 sts; sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS); return ((sts & TSI721_DMAC_STS_RUN) == 0); }

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void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan) { /* Disable BDMA channel interrupts */ iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE); if (bdma_chan->active) tasklet_hi_schedule(&bdma_chan->tasklet); }

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#ifdef CONFIG_PCI_MSI /** * tsi721_omsg_msix - MSI-X interrupt handler for BDMA channels * @irq: Linux interrupt number * @ptr: Pointer to interrupt-specific data (BDMA channel structure) * * Handles BDMA channel interrupts signaled using MSI-X. */
static irqreturn_t tsi721_bdma_msix(int irq, void *ptr) { struct tsi721_bdma_chan *bdma_chan = ptr; if (bdma_chan->active) tasklet_hi_schedule(&bdma_chan->tasklet); return IRQ_HANDLED; }

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#endif /* CONFIG_PCI_MSI */ /* Must be called with the spinlock held */
static void tsi721_start_dma(struct tsi721_bdma_chan *bdma_chan) { if (!tsi721_dma_is_idle(bdma_chan)) { tsi_err(&bdma_chan->dchan.dev->device, "DMAC%d Attempt to start non-idle channel", bdma_chan->id); return; } if (bdma_chan->wr_count == bdma_chan->wr_count_next) { tsi_err(&bdma_chan->dchan.dev->device, "DMAC%d Attempt to start DMA with no BDs ready %d", bdma_chan->id, task_pid_nr(current)); return; } tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d (wrc=%d) %d", bdma_chan->id, bdma_chan->wr_count_next, task_pid_nr(current)); iowrite32(bdma_chan->wr_count_next, bdma_chan->regs + TSI721_DMAC_DWRCNT); ioread32(bdma_chan->regs + TSI721_DMAC_DWRCNT); bdma_chan->wr_count = bdma_chan->wr_count_next; }

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static int tsi721_desc_fill_init(struct tsi721_tx_desc *desc, struct tsi721_dma_desc *bd_ptr, struct scatterlist *sg, u32 sys_size) { u64 rio_addr; if (bd_ptr == NULL) return -EINVAL; /* Initialize DMA descriptor */ bd_ptr->type_id = cpu_to_le32((DTYPE1 << 29) | (desc->rtype << 19) | desc->destid); bd_ptr->bcount = cpu_to_le32(((desc->rio_addr & 0x3) << 30) | (sys_size << 26)); rio_addr = (desc->rio_addr >> 2) | ((u64)(desc->rio_addr_u & 0x3) << 62); bd_ptr->raddr_lo = cpu_to_le32(rio_addr & 0xffffffff); bd_ptr->raddr_hi = cpu_to_le32(rio_addr >> 32); bd_ptr->t1.bufptr_lo = cpu_to_le32( (u64)sg_dma_address(sg) & 0xffffffff); bd_ptr->t1.bufptr_hi = cpu_to_le32((u64)sg_dma_address(sg) >> 32); bd_ptr->t1.s_dist = 0; bd_ptr->t1.s_size = 0; return 0; }

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static int tsi721_desc_fill_end(struct tsi721_dma_desc *bd_ptr, u32 bcount, bool interrupt) { if (bd_ptr == NULL) return -EINVAL; /* Update DMA descriptor */ if (interrupt) bd_ptr->type_id |= cpu_to_le32(TSI721_DMAD_IOF); bd_ptr->bcount |= cpu_to_le32(bcount & TSI721_DMAD_BCOUNT1); return 0; }

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static void tsi721_dma_tx_err(struct tsi721_bdma_chan *bdma_chan, struct tsi721_tx_desc *desc) { struct dma_async_tx_descriptor *txd = &desc->txd; dma_async_tx_callback callback = txd->callback; void *param = txd->callback_param; list_move(&desc->desc_node, &bdma_chan->free_list); if (callback) callback(param); }

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static void tsi721_clr_stat(struct tsi721_bdma_chan *bdma_chan) { u32 srd_ptr; u64 *sts_ptr; int i, j; /* Check and clear descriptor status FIFO entries */ srd_ptr = bdma_chan->sts_rdptr; sts_ptr = bdma_chan->sts_base; j = srd_ptr * 8; while (sts_ptr[j]) { for (i = 0; i < 8 && sts_ptr[j]; i++, j++) sts_ptr[j] = 0; ++srd_ptr; srd_ptr %= bdma_chan->sts_size; j = srd_ptr * 8; } iowrite32(srd_ptr, bdma_chan->regs + TSI721_DMAC_DSRP); bdma_chan->sts_rdptr = srd_ptr; }

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/* Must be called with the channel spinlock held */
static int tsi721_submit_sg(struct tsi721_tx_desc *desc) { struct dma_chan *dchan = desc->txd.chan; struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan); u32 sys_size; u64 rio_addr; dma_addr_t next_addr; u32 bcount; struct scatterlist *sg; unsigned int i; int err = 0; struct tsi721_dma_desc *bd_ptr = NULL; u32 idx, rd_idx; u32 add_count = 0; struct device *ch_dev = &dchan->dev->device; if (!tsi721_dma_is_idle(bdma_chan)) { tsi_err(ch_dev, "DMAC%d ERR: Attempt to use non-idle channel", bdma_chan->id); return -EIO; } /* * Fill DMA channel's hardware buffer descriptors. * (NOTE: RapidIO destination address is limited to 64 bits for now) */ rio_addr = desc->rio_addr; next_addr = -1; bcount = 0; sys_size = dma_to_mport(dchan->device)->sys_size; rd_idx = ioread32(bdma_chan->regs + TSI721_DMAC_DRDCNT); rd_idx %= (bdma_chan->bd_num + 1); idx = bdma_chan->wr_count_next % (bdma_chan->bd_num + 1); if (idx == bdma_chan->bd_num) { /* wrap around link descriptor */ idx = 0; add_count++; } tsi_debug(DMA, ch_dev, "DMAC%d BD ring status: rdi=%d wri=%d", bdma_chan->id, rd_idx, idx); for_each_sg(desc->sg, sg, desc->sg_len, i) { tsi_debug(DMAV, ch_dev, "DMAC%d sg%d/%d addr: 0x%llx len: %d", bdma_chan->id, i, desc->sg_len, (unsigned long long)sg_dma_address(sg), sg_dma_len(sg)); if (sg_dma_len(sg) > TSI721_BDMA_MAX_BCOUNT) { tsi_err(ch_dev, "DMAC%d SG entry %d is too large", bdma_chan->id, i); err = -EINVAL; break; } /* * If this sg entry forms contiguous block with previous one, * try to merge it into existing DMA descriptor */ if (next_addr == sg_dma_address(sg) && bcount + sg_dma_len(sg) <= TSI721_BDMA_MAX_BCOUNT) { /* Adjust byte count of the descriptor */ bcount += sg_dma_len(sg); goto entry_done; } else if (next_addr != -1) { /* Finalize descriptor using total byte count value */ tsi721_desc_fill_end(bd_ptr, bcount, 0); tsi_debug(DMAV, ch_dev, "DMAC%d prev desc final len: %d", bdma_chan->id, bcount); } desc->rio_addr = rio_addr; if (i && idx == rd_idx) { tsi_debug(DMAV, ch_dev, "DMAC%d HW descriptor ring is full @ %d", bdma_chan->id, i); desc->sg = sg; desc->sg_len -= i; break; } bd_ptr = &((struct tsi721_dma_desc *)bdma_chan->bd_base)[idx]; err = tsi721_desc_fill_init(desc, bd_ptr, sg, sys_size); if (err) { tsi_err(ch_dev, "Failed to build desc: err=%d", err); break; } tsi_debug(DMAV, ch_dev, "DMAC%d bd_ptr = %p did=%d raddr=0x%llx", bdma_chan->id, bd_ptr, desc->destid, desc->rio_addr); next_addr = sg_dma_address(sg); bcount = sg_dma_len(sg); add_count++; if (++idx == bdma_chan->bd_num) { /* wrap around link descriptor */ idx = 0; add_count++; } entry_done: if (sg_is_last(sg)) { tsi721_desc_fill_end(bd_ptr, bcount, 0); tsi_debug(DMAV, ch_dev, "DMAC%d last desc final len: %d", bdma_chan->id, bcount); desc->sg_len = 0; } else { rio_addr += sg_dma_len(sg); next_addr += sg_dma_len(sg); } } if (!err) bdma_chan->wr_count_next += add_count; return err; }

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static void tsi721_advance_work(struct tsi721_bdma_chan *bdma_chan, struct tsi721_tx_desc *desc) { int err; tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d", bdma_chan->id); if (!tsi721_dma_is_idle(bdma_chan)) return; /* * If there is no data transfer in progress, fetch new descriptor from * the pending queue. */ if (desc == NULL && bdma_chan->active_tx == NULL && !list_empty(&bdma_chan->queue)) { desc = list_first_entry(&bdma_chan->queue, struct tsi721_tx_desc, desc_node); list_del_init((&desc->desc_node)); bdma_chan->active_tx = desc; } if (desc) { err = tsi721_submit_sg(desc); if (!err) tsi721_start_dma(bdma_chan); else { tsi721_dma_tx_err(bdma_chan, desc); tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d ERR: tsi721_submit_sg failed with err=%d", bdma_chan->id, err); } } tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d Exit", bdma_chan->id); }

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static void tsi721_dma_tasklet(unsigned long data) { struct tsi721_bdma_chan *bdma_chan = (struct tsi721_bdma_chan *)data; u32 dmac_int, dmac_sts; dmac_int = ioread32(bdma_chan->regs + TSI721_DMAC_INT); tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d_INT = 0x%x", bdma_chan->id, dmac_int); /* Clear channel interrupts */ iowrite32(dmac_int, bdma_chan->regs + TSI721_DMAC_INT); if (dmac_int & TSI721_DMAC_INT_ERR) { int i = 10000; struct tsi721_tx_desc *desc; desc = bdma_chan->active_tx; dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS); tsi_err(&bdma_chan->dchan.dev->device, "DMAC%d_STS = 0x%x did=%d raddr=0x%llx", bdma_chan->id, dmac_sts, desc->destid, desc->rio_addr); /* Re-initialize DMA channel if possible */ if ((dmac_sts & TSI721_DMAC_STS_ABORT) == 0) goto err_out; tsi721_clr_stat(bdma_chan); spin_lock(&bdma_chan->lock); /* Put DMA channel into init state */ iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL); do { udelay(1); dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS); i--; } while ((dmac_sts & TSI721_DMAC_STS_ABORT) && i); if (dmac_sts & TSI721_DMAC_STS_ABORT) { tsi_err(&bdma_chan->dchan.dev->device, "Failed to re-initiate DMAC%d", bdma_chan->id); spin_unlock(&bdma_chan->lock); goto err_out; } /* Setup DMA descriptor pointers */ iowrite32(((u64)bdma_chan->bd_phys >> 32), bdma_chan->regs + TSI721_DMAC_DPTRH); iowrite32(((u64)bdma_chan->bd_phys & TSI721_DMAC_DPTRL_MASK), bdma_chan->regs + TSI721_DMAC_DPTRL); /* Setup descriptor status FIFO */ iowrite32(((u64)bdma_chan->sts_phys >> 32), bdma_chan->regs + TSI721_DMAC_DSBH); iowrite32(((u64)bdma_chan->sts_phys & TSI721_DMAC_DSBL_MASK), bdma_chan->regs + TSI721_DMAC_DSBL); iowrite32