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Release 4.14 drivers/spmi/spmi-pmic-arb.c

Directory: drivers/spmi
/*
 * Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/bitmap.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spmi.h>

/* PMIC Arbiter configuration registers */

#define PMIC_ARB_VERSION		0x0000

#define PMIC_ARB_VERSION_V2_MIN		0x20010000

#define PMIC_ARB_VERSION_V3_MIN		0x30000000

#define PMIC_ARB_VERSION_V5_MIN		0x50000000

#define PMIC_ARB_INT_EN			0x0004

/* PMIC Arbiter channel registers offsets */

#define PMIC_ARB_CMD			0x00

#define PMIC_ARB_CONFIG			0x04

#define PMIC_ARB_STATUS			0x08

#define PMIC_ARB_WDATA0			0x10

#define PMIC_ARB_WDATA1			0x14

#define PMIC_ARB_RDATA0			0x18

#define PMIC_ARB_RDATA1			0x1C

/* Mapping Table */

#define SPMI_MAPPING_TABLE_REG(N)	(0x0B00 + (4 * (N)))

#define SPMI_MAPPING_BIT_INDEX(X)	(((X) >> 18) & 0xF)

#define SPMI_MAPPING_BIT_IS_0_FLAG(X)	(((X) >> 17) & 0x1)

#define SPMI_MAPPING_BIT_IS_0_RESULT(X)	(((X) >> 9) & 0xFF)

#define SPMI_MAPPING_BIT_IS_1_FLAG(X)	(((X) >> 8) & 0x1)

#define SPMI_MAPPING_BIT_IS_1_RESULT(X)	(((X) >> 0) & 0xFF)


#define SPMI_MAPPING_TABLE_TREE_DEPTH	16	
/* Maximum of 16-bits */

#define PMIC_ARB_MAX_PPID		BIT(12) 
/* PPID is 12bit */

#define PMIC_ARB_APID_VALID		BIT(15)

#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg)	((reg) & BIT(24))

#define INVALID_EE				0xFF

/* Ownership Table */

#define SPMI_OWNERSHIP_TABLE_REG(N)	(0x0700 + (4 * (N)))

#define SPMI_OWNERSHIP_PERIPH2OWNER(X)	((X) & 0x7)

/* Channel Status fields */

enum pmic_arb_chnl_status {
	
PMIC_ARB_STATUS_DONE	= BIT(0),
	
PMIC_ARB_STATUS_FAILURE	= BIT(1),
	
PMIC_ARB_STATUS_DENIED	= BIT(2),
	
PMIC_ARB_STATUS_DROPPED	= BIT(3),
};

/* Command register fields */

#define PMIC_ARB_CMD_MAX_BYTE_COUNT	8

/* Command Opcodes */

enum pmic_arb_cmd_op_code {
	
PMIC_ARB_OP_EXT_WRITEL = 0,
	
PMIC_ARB_OP_EXT_READL = 1,
	
PMIC_ARB_OP_EXT_WRITE = 2,
	
PMIC_ARB_OP_RESET = 3,
	
PMIC_ARB_OP_SLEEP = 4,
	
PMIC_ARB_OP_SHUTDOWN = 5,
	
PMIC_ARB_OP_WAKEUP = 6,
	
PMIC_ARB_OP_AUTHENTICATE = 7,
	
PMIC_ARB_OP_MSTR_READ = 8,
	
PMIC_ARB_OP_MSTR_WRITE = 9,
	
PMIC_ARB_OP_EXT_READ = 13,
	
PMIC_ARB_OP_WRITE = 14,
	
PMIC_ARB_OP_READ = 15,
	
PMIC_ARB_OP_ZERO_WRITE = 16,
};

/*
 * PMIC arbiter version 5 uses different register offsets for read/write vs
 * observer channels.
 */

enum pmic_arb_channel {
	
PMIC_ARB_CHANNEL_RW,
	
PMIC_ARB_CHANNEL_OBS,
};

/* Maximum number of support PMIC peripherals */

#define PMIC_ARB_MAX_PERIPHS		512

#define PMIC_ARB_TIMEOUT_US		100

#define PMIC_ARB_MAX_TRANS_BYTES	(8)


#define PMIC_ARB_APID_MASK		0xFF

#define PMIC_ARB_PPID_MASK		0xFFF

/* interrupt enable bit */

#define SPMI_PIC_ACC_ENABLE_BIT		BIT(0)


#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
	((((slave_id) & 0xF)   << 28) | \
        (((periph_id) & 0xFF)  << 20) | \
        (((irq_id)    & 0x7)   << 16) | \
        (((apid)      & 0x1FF) << 0))


#define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)

#define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)

#define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)

#define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)

struct pmic_arb_ver_ops;


struct apid_data {
	
u16		ppid;
	
u8		write_ee;
	
u8		irq_ee;
};

/**
 * spmi_pmic_arb - SPMI PMIC Arbiter object
 *
 * @rd_base:            on v1 "core", on v2 "observer" register base off DT.
 * @wr_base:            on v1 "core", on v2 "chnls"    register base off DT.
 * @intr:               address of the SPMI interrupt control registers.
 * @cnfg:               address of the PMIC Arbiter configuration registers.
 * @lock:               lock to synchronize accesses.
 * @channel:            execution environment channel to use for accesses.
 * @irq:                PMIC ARB interrupt.
 * @ee:                 the current Execution Environment
 * @min_apid:           minimum APID (used for bounding IRQ search)
 * @max_apid:           maximum APID
 * @mapping_table:      in-memory copy of PPID -> APID mapping table.
 * @domain:             irq domain object for PMIC IRQ domain
 * @spmic:              SPMI controller object
 * @ver_ops:            version dependent operations.
 * @ppid_to_apid        in-memory copy of PPID -> APID mapping table.
 */

struct spmi_pmic_arb {
	
void __iomem		*rd_base;
	
void __iomem		*wr_base;
	
void __iomem		*intr;
	
void __iomem		*cnfg;
	
void __iomem		*core;
	
resource_size_t		core_size;
	
raw_spinlock_t		lock;
	
u8			channel;
	
int			irq;
	
u8			ee;
	
u16			min_apid;
	
u16			max_apid;
	
u32			*mapping_table;
	DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
	
struct irq_domain	*domain;
	
struct spmi_controller	*spmic;
	
const struct pmic_arb_ver_ops *ver_ops;
	
u16			*ppid_to_apid;
	
u16			last_apid;
	
struct apid_data	apid_data[PMIC_ARB_MAX_PERIPHS];
};

/**
 * pmic_arb_ver: version dependent functionality.
 *
 * @ver_str:            version string.
 * @ppid_to_apid:       finds the apid for a given ppid.
 * @non_data_cmd:       on v1 issues an spmi non-data command.
 *                      on v2 no HW support, returns -EOPNOTSUPP.
 * @offset:             on v1 offset of per-ee channel.
 *                      on v2 offset of per-ee and per-ppid channel.
 * @fmt_cmd:            formats a GENI/SPMI command.
 * @owner_acc_status:   on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 *                      on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
 * @acc_enable:         on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 *                      on v2 address of SPMI_PIC_ACC_ENABLEn.
 * @irq_status:         on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 *                      on v2 address of SPMI_PIC_IRQ_STATUSn.
 * @irq_clear:          on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 *                      on v2 address of SPMI_PIC_IRQ_CLEARn.
 * @apid_map_offset:    offset of PMIC_ARB_REG_CHNLn
 */

struct pmic_arb_ver_ops {
	
const char *ver_str;
	
int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
	/* spmi commands (read_cmd, write_cmd, cmd) functionality */
	
int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
			enum pmic_arb_channel ch_type);
	
u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
	
int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
	/* Interrupts controller functionality (offset of PIC registers) */
	
void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
					  u16 n);
	
void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
	
void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
	
void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
	
u32 (*apid_map_offset)(u16 n);
};


static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb, u32 offset, u32 val) { writel_relaxed(val, pmic_arb->wr_base + offset); }

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Kenneth Heitke2068.97%125.00%
Gilad Avidov620.69%125.00%
Kiran Gunda26.90%125.00%
Abhijeet Dharmapurikar13.45%125.00%
Total29100.00%4100.00%


static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb, u32 offset, u32 val) { writel_relaxed(val, pmic_arb->rd_base + offset); }

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Gilad Avidov2172.41%125.00%
Kenneth Heitke517.24%125.00%
Kiran Gunda26.90%125.00%
Abhijeet Dharmapurikar13.45%125.00%
Total29100.00%4100.00%

/** * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf * @bc: byte count -1. range: 0..3 * @reg: register's address * @buf: output parameter, length must be bc + 1 */
static void pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc) { u32 data = __raw_readl(pmic_arb->rd_base + reg); memcpy(buf, &data, (bc & 3) + 1); }

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Kenneth Heitke4183.67%125.00%
Stephen Boyd48.16%125.00%
Kiran Gunda36.12%125.00%
Abhijeet Dharmapurikar12.04%125.00%
Total49100.00%4100.00%

/** * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register * @bc: byte-count -1. range: 0..3. * @reg: register's address. * @buf: buffer to write. length must be bc + 1. */
static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf, u32 reg, u8 bc) { u32 data = 0; memcpy(&data, buf, (bc & 3) + 1); __raw_writel(data, pmic_arb->wr_base + reg); }

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Kenneth Heitke4583.33%125.00%
Kiran Gunda814.81%250.00%
Abhijeet Dharmapurikar11.85%125.00%
Total54100.00%4100.00%


static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, void __iomem *base, u8 sid, u16 addr, enum pmic_arb_channel ch_type) { struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); u32 status = 0; u32 timeout = PMIC_ARB_TIMEOUT_US; u32 offset; int rc; rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type); if (rc < 0) return rc; offset = rc; offset += PMIC_ARB_STATUS; while (timeout--) { status = readl_relaxed(base + offset); if (status & PMIC_ARB_STATUS_DONE) { if (status & PMIC_ARB_STATUS_DENIED) { dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n", __func__, status); return -EPERM; } if (status & PMIC_ARB_STATUS_FAILURE) { dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n", __func__, status); return -EIO; } if (status & PMIC_ARB_STATUS_DROPPED) { dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n", __func__, status); return -EIO; } return 0; } udelay(1); } dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n", __func__, status); return -ETIMEDOUT; }

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Kenneth Heitke15873.83%114.29%
Gilad Avidov2310.75%114.29%
Stephen Boyd177.94%114.29%
Kiran Gunda94.21%228.57%
David Collins62.80%114.29%
Abhijeet Dharmapurikar10.47%114.29%
Total214100.00%7100.00%


static int pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) { struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); unsigned long flags; u32 cmd; int rc; u32 offset; rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; offset = rc; cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); raw_spin_lock_irqsave(&pmic_arb->lock, flags); pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, PMIC_ARB_CHANNEL_RW); raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); return rc; }

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PersonTokensPropCommitsCommitProp
Kenneth Heitke9264.34%114.29%
Gilad Avidov2215.38%114.29%
Kiran Gunda139.09%228.57%
Stephen Boyd117.69%114.29%
David Collins42.80%114.29%
Abhijeet Dharmapurikar10.70%114.29%
Total143100.00%7100.00%


static int pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) { return -EOPNOTSUPP; }

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/* Non-data command */
static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) { struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); /* Check for valid non-data command */ if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) return -EINVAL; return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); }

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Kiran Gunda22.86%133.33%
Abhijeet Dharmapurikar11.43%133.33%
Total70100.00%3100.00%


static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); unsigned long flags; u8 bc = len - 1; u32 cmd; int rc; u32 offset; rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_OBS); if (rc < 0) return rc; offset = rc; if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested", PMIC_ARB_MAX_TRANS_BYTES, len); return -EINVAL; } /* Check the opcode */ if (opc >= 0x60 && opc <= 0x7F) opc = PMIC_ARB_OP_READ; else if (opc >= 0x20 && opc <= 0x2F) opc = PMIC_ARB_OP_EXT_READ; else if (opc >= 0x38 && opc <= 0x3F) opc = PMIC_ARB_OP_EXT_READL; else return -EINVAL; cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); raw_spin_lock_irqsave(&pmic_arb->lock, flags); pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr, PMIC_ARB_CHANNEL_OBS); if (rc) goto done; pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, min_t(u8, bc, 3)); if (bc > 3) pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1, bc - 4); done: raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); return rc; }

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Kenneth Heitke21375.27%114.29%
Gilad Avidov3612.72%114.29%
Kiran Gunda186.36%228.57%
Stephen Boyd113.89%114.29%
David Collins41.41%114.29%
Abhijeet Dharmapurikar10.35%114.29%
Total283100.00%7100.00%


static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, const u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); unsigned long flags; u8 bc = len - 1; u32 cmd; int rc; u32 offset; rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; offset = rc; if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested", PMIC_ARB_MAX_TRANS_BYTES, len); return -EINVAL; } /* Check the opcode */ if (opc >= 0x40 && opc <= 0x5F) opc = PMIC_ARB_OP_WRITE; else if (opc <= 0x0F) opc = PMIC_ARB_OP_EXT_WRITE; else if (opc >= 0x30 && opc <= 0x37) opc = PMIC_ARB_OP_EXT_WRITEL; else if (opc >= 0x80) opc = PMIC_ARB_OP_ZERO_WRITE; else return -EINVAL; cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); /* Write data to FIFOs */ raw_spin_lock_irqsave(&pmic_arb->lock, flags); pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, min_t(u8, bc, 3)); if (bc > 3) pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1, bc - 4); /* Start the transaction */ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr, PMIC_ARB_CHANNEL_RW); raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); return rc; }

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Kenneth Heitke21073.94%114.29%
Gilad Avidov4014.08%114.29%
Kiran Gunda186.34%228.57%
Stephen Boyd113.87%114.29%
David Collins41.41%114.29%
Abhijeet Dharmapurikar10.35%114.29%
Total284100.00%7100.00%

enum qpnpint_regs { QPNPINT_REG_RT_STS = 0x10, QPNPINT_REG_SET_TYPE = 0x11, QPNPINT_REG_POLARITY_HIGH = 0x12, QPNPINT_REG_POLARITY_LOW = 0x13, QPNPINT_REG_LATCHED_CLR = 0x14, QPNPINT_REG_EN_SET = 0x15, QPNPINT_REG_EN_CLR = 0x16, QPNPINT_REG_LATCHED_STS = 0x18, }; struct spmi_pmic_arb_qpnpint_type { u8 type; /* 1 -> edge */ u8 polarity_high; u8 polarity_low; } __packed; /* Simplified accessor functions for irqchip callbacks */
static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, size_t len) { struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d); u8 sid = hwirq_to_sid(d->hwirq); u8 per = hwirq_to_per(d->hwirq); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, (per << 8) + reg, buf, len)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n", d->irq); }

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Julia Cartwright5863.04%120.00%
Kenneth Heitke2426.09%120.00%
Kiran Gunda55.43%120.00%
Abhijeet Dharmapurikar55.43%240.00%
Total92100.00%5100.00%


static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) { struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d); u8 sid = hwirq_to_sid(d->hwirq); u8 per = hwirq_to_per(d->hwirq); if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid, (per << 8) + reg, buf, len)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n", d->irq); }

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Julia Cartwright7177.17%120.00%
Kenneth Heitke1111.96%120.00%
Abhijeet Dharmapurikar55.43%240.00%
Kiran Gunda55.43%120.00%
Total92100.00%5100.00%


static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) { u16 ppid = pmic_arb->apid_data[apid].ppid; u8 sid = ppid >> 8; u8 per = ppid & 0xFF; u8 irq_mask = BIT(id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", irq_mask, ppid); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", irq_mask, ppid); }

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Kiran Gunda95.96%250.00%
Total151100.00%4100.00%


static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) { unsigned int irq; u32 status; int id; u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF; u8 per = pmic_arb->apid_data[apid].ppid & 0xFF; status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid)); while (status) { id = ffs(status) - 1; status &= ~BIT(id); irq = irq_find_mapping(pmic_arb->domain, spec_to_hwirq(sid, per, id, apid)); if (irq == 0) { cleanup_irq(pmic_arb, apid, id); continue; } generic_handle_irq(irq); } }

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Julia Cartwright6748.55%114.29%
Abhijeet Dharmapurikar5942.75%342.86%
Kiran Gunda96.52%228.57%
Gilad Avidov32.17%114.29%
Total138100.00%7100.00%


static void pmic_arb_chained_irq(struct irq_desc *desc) { struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc); const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; struct irq_chip *chip = irq_desc_get_chip(desc); int first = pmic_arb->min_apid >> 5; int last = pmic_arb->max_apid >> 5; u8 ee = pmic_arb->ee; u32 status, enable; int i, id, apid; chained_irq_enter(chip, desc); for (i = first; i <= last; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); while (status) { id = ffs(status) - 1; status &= ~BIT(id); apid = id + i * 32; enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) periph_interrupt(pmic_arb, apid); } } chained_irq_exit(chip, desc); }

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Julia Cartwright11664.09%114.29%
Abhijeet Dharmapurikar3318.23%228.57%
Kiran Gunda2513.81%228.57%
Jiang Liu42.21%114.29%
Gilad Avidov31.66%114.29%
Total181100.00%7100.00%


static void qpnpint_irq_ack(struct irq_data *d) { struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d); u8 irq = hwirq_to_irq(d->hwirq); u16 apid = hwirq_to_apid(d->hwirq); u8 data; writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); data = BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); }

Contributors

PersonTokensPropCommitsCommitProp
Julia Cartwright6174.39%116.67%
Abhijeet Dharmapurikar1214.63%233.33%
Kiran Gunda67.32%233.33%
Gilad Avidov33.66%116.67%
Total82100.00%6100.00%


static void qpnpint_irq_mask(struct irq_data *d) { u8 irq = hwirq_to_irq(d->hwirq); u8 data = BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); }

Contributors

PersonTokensPropCommitsCommitProp
Julia Cartwright3380.49%120.00%
Abhijeet Dharmapurikar717.07%360.00%
Kiran Gunda12.44%120.00%
Total41100.00%5100.00%


static void qpnpint_irq_unmask(struct irq_data *d) { struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d); const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; u8 irq = hwirq_to_irq(d->hwirq); u16 apid = hwirq_to_apid(d->hwirq); u8 buf[2]; writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, ver_ops->acc_enable(pmic_arb, apid)); qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); if (!(buf[0] & BIT(irq))) { /* * Since the interrupt is currently disabled, write to both the * LATCHED_CLR and EN_SET registers so that a spurious interrupt * cannot be triggered when the interrupt is enabled */ buf[0] = BIT(irq); buf[1] = BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); } }

Contributors

PersonTokensPropCommitsCommitProp
Abhijeet Dharmapurikar6749.26%450.00%
Julia Cartwright5137.50%112.50%
Kiran Gunda1511.03%225.00%
Gilad Avidov32.21%112.50%
Total136100.00%8100.00%


static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct spmi_pmic_arb_qpnpint_type type; irq_flow_handler_t flow_handler; u8 irq = hwirq_to_irq(d->hwirq); qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type.type |= BIT(irq); if (flow_type & IRQF_TRIGGER_RISING) type.polarity_high |= BIT(irq); if (flow_type & IRQF_TRIGGER_FALLING) type.polarity_low |= BIT(irq); flow_handler = handle_edge_irq; } else { if ((flow_type & (IRQF_TRIGGER_HIGH)) && (flow_type & (IRQF_TRIGGER_LOW))) return