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Release 4.14 drivers/vfio/pci/vfio_pci_config.c

Directory: drivers/vfio/pci
/*
 * VFIO PCI config space virtualization
 *
 * Copyright (C) 2012 Red Hat, Inc.  All rights reserved.
 *     Author: Alex Williamson <alex.williamson@redhat.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Derived from original vfio:
 * Copyright 2010 Cisco Systems, Inc.  All rights reserved.
 * Author: Tom Lyon, pugs@cisco.com
 */

/*
 * This code handles reading and writing of PCI configuration registers.
 * This is hairy because we want to allow a lot of flexibility to the
 * user driver, but cannot trust it with all of the config fields.
 * Tables determine which fields can be read and written, as well as
 * which fields are 'virtualized' - special actions and translations to
 * make it appear to the user that he has control, when in fact things
 * must be negotiated with the underlying OS.
 */

#include <linux/fs.h>
#include <linux/pci.h>
#include <linux/uaccess.h>
#include <linux/vfio.h>
#include <linux/slab.h>

#include "vfio_pci_private.h"

/* Fake capability ID for standard config space */

#define PCI_CAP_ID_BASIC	0


#define is_bar(offset)	\
	((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
         (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))

/*
 * Lengths of PCI Config Capabilities
 *   0: Removed from the user visible capability list
 *   FF: Variable length
 */

static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
	[PCI_CAP_ID_BASIC]	= PCI_STD_HEADER_SIZEOF, /* pci config header */
	[PCI_CAP_ID_PM]		= PCI_PM_SIZEOF,
	[PCI_CAP_ID_AGP]	= PCI_AGP_SIZEOF,
	[PCI_CAP_ID_VPD]	= PCI_CAP_VPD_SIZEOF,
	[PCI_CAP_ID_SLOTID]	= 0,		/* bridge - don't care */
	[PCI_CAP_ID_MSI]	= 0xFF,		/* 10, 14, 20, or 24 */
	[PCI_CAP_ID_CHSWP]	= 0,		/* cpci - not yet */
	[PCI_CAP_ID_PCIX]	= 0xFF,		/* 8 or 24 */
	[PCI_CAP_ID_HT]		= 0xFF,		/* hypertransport */
	[PCI_CAP_ID_VNDR]	= 0xFF,		/* variable */
	[PCI_CAP_ID_DBG]	= 0,		/* debug - don't care */
	[PCI_CAP_ID_CCRC]	= 0,		/* cpci - not yet */
	[PCI_CAP_ID_SHPC]	= 0,		/* hotswap - not yet */
	[PCI_CAP_ID_SSVID]	= 0,		/* bridge - don't care */
	[PCI_CAP_ID_AGP3]	= 0,		/* AGP8x - not yet */
	[PCI_CAP_ID_SECDEV]	= 0,		/* secure device not yet */
	[PCI_CAP_ID_EXP]	= 0xFF,		/* 20 or 44 */
	[PCI_CAP_ID_MSIX]	= PCI_CAP_MSIX_SIZEOF,
	[PCI_CAP_ID_SATA]	= 0xFF,
	[PCI_CAP_ID_AF]		= PCI_CAP_AF_SIZEOF,
};

/*
 * Lengths of PCIe/PCI-X Extended Config Capabilities
 *   0: Removed or masked from the user visible capability list
 *   FF: Variable length
 */

static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
	[PCI_EXT_CAP_ID_ERR]	=	PCI_ERR_ROOT_COMMAND,
	[PCI_EXT_CAP_ID_VC]	=	0xFF,
	[PCI_EXT_CAP_ID_DSN]	=	PCI_EXT_CAP_DSN_SIZEOF,
	[PCI_EXT_CAP_ID_PWR]	=	PCI_EXT_CAP_PWR_SIZEOF,
	[PCI_EXT_CAP_ID_RCLD]	=	0,	/* root only - don't care */
	[PCI_EXT_CAP_ID_RCILC]	=	0,	/* root only - don't care */
	[PCI_EXT_CAP_ID_RCEC]	=	0,	/* root only - don't care */
	[PCI_EXT_CAP_ID_MFVC]	=	0xFF,
	[PCI_EXT_CAP_ID_VC9]	=	0xFF,	/* same as CAP_ID_VC */
	[PCI_EXT_CAP_ID_RCRB]	=	0,	/* root only - don't care */
	[PCI_EXT_CAP_ID_VNDR]	=	0xFF,
	[PCI_EXT_CAP_ID_CAC]	=	0,	/* obsolete */
	[PCI_EXT_CAP_ID_ACS]	=	0xFF,
	[PCI_EXT_CAP_ID_ARI]	=	PCI_EXT_CAP_ARI_SIZEOF,
	[PCI_EXT_CAP_ID_ATS]	=	PCI_EXT_CAP_ATS_SIZEOF,
	[PCI_EXT_CAP_ID_SRIOV]	=	PCI_EXT_CAP_SRIOV_SIZEOF,
	[PCI_EXT_CAP_ID_MRIOV]	=	0,	/* not yet */
	[PCI_EXT_CAP_ID_MCAST]	=	PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
	[PCI_EXT_CAP_ID_PRI]	=	PCI_EXT_CAP_PRI_SIZEOF,
	[PCI_EXT_CAP_ID_AMD_XXX] =	0,	/* not yet */
	[PCI_EXT_CAP_ID_REBAR]	=	0xFF,
	[PCI_EXT_CAP_ID_DPA]	=	0xFF,
	[PCI_EXT_CAP_ID_TPH]	=	0xFF,
	[PCI_EXT_CAP_ID_LTR]	=	PCI_EXT_CAP_LTR_SIZEOF,
	[PCI_EXT_CAP_ID_SECPCI]	=	0,	/* not yet */
	[PCI_EXT_CAP_ID_PMUX]	=	0,	/* not yet */
	[PCI_EXT_CAP_ID_PASID]	=	0,	/* not yet */
};

/*
 * Read/Write Permission Bits - one bit for each bit in capability
 * Any field can be read if it exists, but what is read depends on
 * whether the field is 'virtualized', or just pass thru to the
 * hardware.  Any virtualized field is also virtualized for writes.
 * Writes are only permitted if they have a 1 bit here.
 */

struct perm_bits {
	
u8	*virt;		/* read/write virtual data, not hw */
	
u8	*write;		/* writeable bits */
	
int	(*readfn)(struct vfio_pci_device *vdev, int pos, int count,
			  struct perm_bits *perm, int offset, __le32 *val);
	
int	(*writefn)(struct vfio_pci_device *vdev, int pos, int count,
			   struct perm_bits *perm, int offset, __le32 val);
};


#define	NO_VIRT		0

#define	ALL_VIRT	0xFFFFFFFFU

#define	NO_WRITE	0

#define	ALL_WRITE	0xFFFFFFFFU


static int vfio_user_config_read(struct pci_dev *pdev, int offset, __le32 *val, int count) { int ret = -EINVAL; u32 tmp_val = 0; switch (count) { case 1: { u8 tmp; ret = pci_user_read_config_byte(pdev, offset, &tmp); tmp_val = tmp; break; } case 2: { u16 tmp; ret = pci_user_read_config_word(pdev, offset, &tmp); tmp_val = tmp; break; } case 4: ret = pci_user_read_config_dword(pdev, offset, &tmp_val); break; } *val = cpu_to_le32(tmp_val); return ret; }

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static int vfio_user_config_write(struct pci_dev *pdev, int offset, __le32 val, int count) { int ret = -EINVAL; u32 tmp_val = le32_to_cpu(val); switch (count) { case 1: ret = pci_user_write_config_byte(pdev, offset, tmp_val); break; case 2: ret = pci_user_write_config_word(pdev, offset, tmp_val); break; case 4: ret = pci_user_write_config_dword(pdev, offset, tmp_val); break; } return ret; }

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static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 *val) { __le32 virt = 0; memcpy(val, vdev->vconfig + pos, count); memcpy(&virt, perm->virt + offset, count); /* Any non-virtualized bits? */ if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { struct pci_dev *pdev = vdev->pdev; __le32 phys_val = 0; int ret; ret = vfio_user_config_read(pdev, pos, &phys_val, count); if (ret) return ret; *val = (phys_val & ~virt) | (*val & virt); } return count; }

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static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 val) { __le32 virt = 0, write = 0; memcpy(&write, perm->write + offset, count); if (!write) return count; /* drop, no writable bits */ memcpy(&virt, perm->virt + offset, count); /* Virtualized and writable bits go to vconfig */ if (write & virt) { __le32 virt_val = 0; memcpy(&virt_val, vdev->vconfig + pos, count); virt_val &= ~(write & virt); virt_val |= (val & (write & virt)); memcpy(vdev->vconfig + pos, &virt_val, count); } /* Non-virtualzed and writable bits go to hardware */ if (write & ~virt) { struct pci_dev *pdev = vdev->pdev; __le32 phys_val = 0; int ret; ret = vfio_user_config_read(pdev, pos, &phys_val, count); if (ret) return ret; phys_val &= ~(write & ~virt); phys_val |= (val & (write & ~virt)); ret = vfio_user_config_write(pdev, pos, phys_val, count); if (ret) return ret; } return count; }

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/* Allow direct read from hardware, except for capability next pointer */
static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 *val) { int ret; ret = vfio_user_config_read(vdev->pdev, pos, val, count); if (ret) return ret; if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ if (offset < 4) memcpy(val, vdev->vconfig + pos, count); } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ if (offset == PCI_CAP_LIST_ID && count > 1) memcpy(val, vdev->vconfig + pos, min(PCI_CAP_FLAGS, count)); else if (offset == PCI_CAP_LIST_NEXT) memcpy(val, vdev->vconfig + pos, 1); } return count; }

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/* Raw access skips any kind of virtualization */
static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 val) { int ret; ret = vfio_user_config_write(vdev->pdev, pos, val, count); if (ret) return ret; return count; }

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static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 *val) { int ret; ret = vfio_user_config_read(vdev->pdev, pos, val, count); if (ret) return ret; return count; }

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/* Virt access uses only virtualization */
static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 val) { memcpy(vdev->vconfig + pos, &val, count); return count; }

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static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 *val) { memcpy(val, vdev->vconfig + pos, count); return count; }

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/* Default capability regions to read-only, no-virtualization */ static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } }; static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } }; /* * Default unassigned regions to raw read-write access. Some devices * require this to function as they hide registers between the gaps in * config space (be2net). Like MMIO and I/O port registers, we have * to trust the hardware isolation. */ static struct perm_bits unassigned_perms = { .readfn = vfio_raw_config_read, .writefn = vfio_raw_config_write }; static struct perm_bits virt_perms = { .readfn = vfio_virt_config_read, .writefn = vfio_virt_config_write };
static void free_perm_bits(struct perm_bits *perm) { kfree(perm->virt); kfree(perm->write); perm->virt = NULL; perm->write = NULL; }

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static int alloc_perm_bits(struct perm_bits *perm, int size) { /* * Round up all permission bits to the next dword, this lets us * ignore whether a read/write exceeds the defined capability * structure. We can do this because: * - Standard config space is already dword aligned * - Capabilities are all dword aligned (bits 0:1 of next reserved) * - Express capabilities defined as dword aligned */ size = round_up(size, 4); /* * Zero state is * - All Readable, None Writeable, None Virtualized */ perm->virt = kzalloc(size, GFP_KERNEL); perm->write = kzalloc(size, GFP_KERNEL); if (!perm->virt || !perm->write) { free_perm_bits(perm); return -ENOMEM; } perm->readfn = vfio_default_config_read; perm->writefn = vfio_default_config_write; return 0; }

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/* * Helper functions for filling in permission tables */
static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) { p->virt[off] = virt; p->write[off] = write; }

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/* Handle endian-ness - pci and tables are little-endian */
static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) { *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); *(__le16 *)(&p->write[off]) = cpu_to_le16(write); }

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/* Handle endian-ness - pci and tables are little-endian */
static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) { *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); *(__le32 *)(&p->write[off]) = cpu_to_le32(write); }

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/* * Restore the *real* BARs after we detect a FLR or backdoor reset. * (backdoor = some device specific technique that we didn't catch) */
static void vfio_bar_restore(struct vfio_pci_device *vdev) { struct pci_dev *pdev = vdev->pdev; u32 *rbar = vdev->rbar; u16 cmd; int i; if (pdev->is_virtfn) return; pr_info("%s: %s reset recovery - restoring bars\n", __func__, dev_name(&pdev->dev)); for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) pci_user_write_config_dword(pdev, i, *rbar); pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); if (vdev->nointx) { pci_user_read_config_word(pdev, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_INTX_DISABLE; pci_user_write_config_word(pdev, PCI_COMMAND, cmd); } }

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static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) { unsigned long flags = pci_resource_flags(pdev, bar); u32 val; if (flags & IORESOURCE_IO) return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); val = PCI_BASE_ADDRESS_SPACE_MEMORY; if (flags & IORESOURCE_PREFETCH) val |= PCI_BASE_ADDRESS_MEM_PREFETCH; if (flags & IORESOURCE_MEM_64) val |= PCI_BASE_ADDRESS_MEM_TYPE_64; return cpu_to_le32(val); }

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/* * Pretend we're hardware and tweak the values of the *virtual* PCI BARs * to reflect the hardware capabilities. This implements BAR sizing. */
static void vfio_bar_fixup(struct vfio_pci_device *vdev) { struct pci_dev *pdev = vdev->pdev; int i; __le32 *bar; u64 mask; bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { if (!pci_resource_start(pdev, i)) { *bar = 0; /* Unmapped by host = unimplemented to user */ continue; } mask = ~(pci_resource_len(pdev, i) - 1); *bar &= cpu_to_le32((u32)mask); *bar |= vfio_generate_bar_flags(pdev, i); if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { bar++; *bar &= cpu_to_le32((u32)(mask >> 32)); i++; } } bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; /* * NB. REGION_INFO will have reported zero size if we weren't able * to read the ROM, but we still return the actual BAR size here if * it exists (or the shadow ROM space). */ if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); mask |= PCI_ROM_ADDRESS_ENABLE; *bar &= cpu_to_le32((u32)mask); } else if (pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW) { mask = ~(0x20000 - 1); mask |= PCI_ROM_ADDRESS_ENABLE; *bar &= cpu_to_le32((u32)mask); } else *bar = 0; vdev->bardirty = false; }

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static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 *val) { if (is_bar(offset)) /* pos == offset for basic config */ vfio_bar_fixup(vdev); count = vfio_default_config_read(vdev, pos, count, perm, offset, val); /* Mask in virtual memory enable for SR-IOV devices */ if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); u32 tmp_val = le32_to_cpu(*val); tmp_val |= cmd & PCI_COMMAND_MEMORY; *val = cpu_to_le32(tmp_val); } return count; }

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/* Test whether BARs match the value we think they should contain */
static bool vfio_need_bar_restore(struct vfio_pci_device *vdev) { int i = 0, pos = PCI_BASE_ADDRESS_0, ret; u32 bar; for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) { if (vdev->rbar[i]) { ret = pci_user_read_config_dword(vdev->pdev, pos, &bar); if (ret || vdev->rbar[i] != bar) return true; } } return false; }

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static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 val) { struct pci_dev *pdev = vdev->pdev; __le16 *virt_cmd; u16 new_cmd = 0; int ret; virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; if (offset == PCI_COMMAND) { bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; u16 phys_cmd; ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); if (ret) return ret; new_cmd = le32_to_cpu(val); phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); phys_io = !!(phys_cmd & PCI_COMMAND_IO); virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); new_io = !!(new_cmd & PCI_COMMAND_IO); /* * If the user is writing mem/io enable (new_mem/io) and we * think it's already enabled (virt_mem/io), but the hardware * shows it disabled (phys_mem/io, then the device has * undergone some kind of backdoor reset and needs to be * restored before we allow it to enable the bars. * SR-IOV devices will trigger this, but we catch them later */ if ((new_mem && virt_mem && !phys_mem) || (new_io && virt_io && !phys_io) || vfio_need_bar_restore(vdev)) vfio_bar_restore(vdev); } count = vfio_default_config_write(vdev, pos, count, perm, offset, val); if (count < 0) return count; /* * Save current memory/io enable bits in vconfig to allow for * the test above next time. */ if (offset == PCI_COMMAND) { u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; *virt_cmd &= cpu_to_le16(~mask); *virt_cmd |= cpu_to_le16(new_cmd & mask); } /* Emulate INTx disable */ if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { bool virt_intx_disable; virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_INTX_DISABLE); if (virt_intx_disable && !vdev->virq_disabled) { vdev->virq_disabled = true; vfio_pci_intx_mask(vdev); } else if (!virt_intx_disable && vdev->virq_disabled) { vdev->virq_disabled = false; vfio_pci_intx_unmask(vdev); } } if (is_bar(offset)) vdev->bardirty = true; return count; }

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/* Permissions for the Basic PCI Header */
static int __init init_pci_cap_basic_perm(struct perm_bits *perm) { if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) return -ENOMEM; perm->readfn = vfio_basic_config_read; perm->writefn = vfio_basic_config_write; /* Virtualized for SR-IOV functions, which just have FFFF */ p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); /* * Virtualize INTx disable, we use it internally for interrupt * control and can emulate it for non-PCI 2.3 devices. */ p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); /* Virtualize capability list, we might want to skip/disable */ p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); /* No harm to write */ p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); /* Virtualize all bars, can't touch the real ones */ p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); /* Allow us to adjust capability chain */ p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); /* Sometimes used by sw, just virtualize */ p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); /* Virtualize interrupt pin to allow hiding INTx */ p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); return 0; }

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static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, int count, struct perm_bits *perm, int offset, __le32 val) { count = vfio_default_config_write(vdev, pos, count, perm, offset, val); if (count < 0) return count; if (offset == PCI_PM_CTRL) { pci_power_t state; switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { case 0: state = PCI_D0; break; case 1: state = PCI_D1; break; case 2: state = PCI_D2; break; case 3: state = PCI_D3hot; break; } pci_set_power_state(vdev->pdev