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Release 4.14 drivers/vme/bridges/vme_ca91cx42.c

/*
 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
 *
 * Author: Martyn Welch <martyn.welch@ge.com>
 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
 *
 * Based on work by Tom Armistead and Ajit Prem
 * Copyright 2004 Motorola Inc.
 *
 * Derived from ca91c042.c by Michael Wyrick
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/module.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/vme.h>

#include "../vme_bridge.h"
#include "vme_ca91cx42.h"

static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
static void ca91cx42_remove(struct pci_dev *);

/* Module parameters */

static int geoid;


static const char driver_name[] = "vme_ca91cx42";


static const struct pci_device_id ca91cx42_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
	{ },
};

MODULE_DEVICE_TABLE(pci, ca91cx42_ids);


static struct pci_driver ca91cx42_driver = {
	.name = driver_name,
	.id_table = ca91cx42_ids,
	.probe = ca91cx42_probe,
	.remove = ca91cx42_remove,
};


static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) { wake_up(&bridge->dma_queue); return CA91CX42_LINT_DMA; }

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Martyn Welch22100.00%3100.00%
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static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) { int i; u32 serviced = 0; for (i = 0; i < 4; i++) { if (stat & CA91CX42_LINT_LM[i]) { /* We only enable interrupts if the callback is set */ bridge->lm_callback[i](bridge->lm_data[i]); serviced |= CA91CX42_LINT_LM[i]; } } return serviced; }

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Martyn Welch6993.24%375.00%
Aaron Sierra56.76%125.00%
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/* XXX This needs to be split into 4 queues */
static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) { wake_up(&bridge->mbox_queue); return CA91CX42_LINT_MBOX; }

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Martyn Welch25100.00%3100.00%
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static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) { wake_up(&bridge->iack_queue); return CA91CX42_LINT_SW_IACK; }

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Martyn Welch22100.00%3100.00%
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static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge) { int val; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; val = ioread32(bridge->base + DGCS); if (!(val & 0x00000800)) { dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA " "Read Error DGCS=%08X\n", val); } return CA91CX42_LINT_VERR; }

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static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge) { int val; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; val = ioread32(bridge->base + DGCS); if (!(val & 0x00000800)) dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA " "Read Error DGCS=%08X\n", val); return CA91CX42_LINT_LERR; }

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static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge, int stat) { int vec, i, serviced = 0; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; for (i = 7; i > 0; i--) { if (stat & (1 << i)) { vec = ioread32(bridge->base + CA91CX42_V_STATID[i]) & 0xff; vme_irq_handler(ca91cx42_bridge, i, vec); serviced |= (1 << i); } } return serviced; }

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Martyn Welch97100.00%4100.00%
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static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) { u32 stat, enable, serviced = 0; struct vme_bridge *ca91cx42_bridge; struct ca91cx42_driver *bridge; ca91cx42_bridge = ptr; bridge = ca91cx42_bridge->driver_priv; enable = ioread32(bridge->base + LINT_EN); stat = ioread32(bridge->base + LINT_STAT); /* Only look at unmasked interrupts */ stat &= enable; if (unlikely(!stat)) return IRQ_NONE; if (stat & CA91CX42_LINT_DMA) serviced |= ca91cx42_DMA_irqhandler(bridge); if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | CA91CX42_LINT_LM3)) serviced |= ca91cx42_LM_irqhandler(bridge, stat); if (stat & CA91CX42_LINT_MBOX) serviced |= ca91cx42_MB_irqhandler(bridge, stat); if (stat & CA91CX42_LINT_SW_IACK) serviced |= ca91cx42_IACK_irqhandler(bridge); if (stat & CA91CX42_LINT_VERR) serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge); if (stat & CA91CX42_LINT_LERR) serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge); if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | CA91CX42_LINT_VIRQ7)) serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat); /* Clear serviced interrupts */ iowrite32(serviced, bridge->base + LINT_STAT); return IRQ_HANDLED; }

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Martyn Welch21399.53%480.00%
Vincent Bossier10.47%120.00%
Total214100.00%5100.00%


static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) { int result, tmp; struct pci_dev *pdev; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; /* Need pdev */ pdev = to_pci_dev(ca91cx42_bridge->parent); /* Disable interrupts from PCI to VME */ iowrite32(0, bridge->base + VINT_EN); /* Disable PCI interrupts */ iowrite32(0, bridge->base + LINT_EN); /* Clear Any Pending PCI Interrupts */ iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED, driver_name, ca91cx42_bridge); if (result) { dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", pdev->irq); return result; } /* Ensure all interrupts are mapped to PCI Interrupt 0 */ iowrite32(0, bridge->base + LINT_MAP0); iowrite32(0, bridge->base + LINT_MAP1); iowrite32(0, bridge->base + LINT_MAP2); /* Enable DMA, mailbox & LM Interrupts */ tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 | CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK | CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA; iowrite32(tmp, bridge->base + LINT_EN); return 0; }

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Martyn Welch18499.46%375.00%
Geliang Tang10.54%125.00%
Total185100.00%4100.00%


static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, struct pci_dev *pdev) { struct vme_bridge *ca91cx42_bridge; /* Disable interrupts from PCI to VME */ iowrite32(0, bridge->base + VINT_EN); /* Disable PCI interrupts */ iowrite32(0, bridge->base + LINT_EN); /* Clear Any Pending PCI Interrupts */ iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge, driver_priv); free_irq(pdev->irq, ca91cx42_bridge); }

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Martyn Welch6073.17%375.00%
Wei Yongjun2226.83%125.00%
Total82100.00%4100.00%


static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level) { u32 tmp; tmp = ioread32(bridge->base + LINT_STAT); if (tmp & (1 << level)) return 0; else return 1; }

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Vincent Bossier45100.00%1100.00%
Total45100.00%1100.00%

/* * Set up an VME interrupt */
static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, int sync) { struct pci_dev *pdev; u32 tmp; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; /* Enable IRQ level */ tmp = ioread32(bridge->base + LINT_EN); if (state == 0) tmp &= ~CA91CX42_LINT_VIRQ[level]; else tmp |= CA91CX42_LINT_VIRQ[level]; iowrite32(tmp, bridge->base + LINT_EN); if ((state == 0) && (sync != 0)) { pdev = to_pci_dev(ca91cx42_bridge->parent); synchronize_irq(pdev->irq); } }

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Martyn Welch11498.28%466.67%
Geliang Tang10.86%116.67%
Emilio G. Cota10.86%116.67%
Total116100.00%6100.00%


static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, int statid) { u32 tmp; struct ca91cx42_driver *bridge; bridge = ca91cx42_bridge->driver_priv; /* Universe can only generate even vectors */ if (statid & 1) return -EINVAL; mutex_lock(&bridge->vme_int); tmp = ioread32(bridge->base + VINT_EN); /* Set Status/ID */ iowrite32(statid << 24, bridge->base + STATID); /* Assert VMEbus IRQ */ tmp = tmp | (1 << (level + 24)); iowrite32(tmp, bridge->base + VINT_EN); /* Wait for IACK */ wait_event_interruptible(bridge->iack_queue, ca91cx42_iack_received(bridge, level)); /* Return interrupt to low state */ tmp = ioread32(bridge->base + VINT_EN); tmp = tmp & ~(1 << (level + 24)); iowrite32(tmp, bridge->base + VINT_EN); mutex_unlock(&bridge->vme_int); return 0; }

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Martyn Welch15895.76%466.67%
Vincent Bossier63.64%116.67%
Emilio G. Cota10.61%116.67%
Total165100.00%6100.00%


static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, unsigned long long vme_base, unsigned long long size, dma_addr_t pci_base, u32 aspace, u32 cycle) { unsigned int i, addr = 0, granularity; unsigned int temp_ctl = 0; unsigned int vme_bound, pci_offset; struct vme_bridge *ca91cx42_bridge; struct ca91cx42_driver *bridge; ca91cx42_bridge = image->parent; bridge = ca91cx42_bridge->driver_priv; i = image->number; switch (aspace) { case VME_A16: addr |= CA91CX42_VSI_CTL_VAS_A16; break; case VME_A24: addr |= CA91CX42_VSI_CTL_VAS_A24; break; case VME_A32: addr |= CA91CX42_VSI_CTL_VAS_A32; break; case VME_USER1: addr |= CA91CX42_VSI_CTL_VAS_USER1; break; case VME_USER2: addr |= CA91CX42_VSI_CTL_VAS_USER2; break; case VME_A64: case VME_CRCSR: case VME_USER3: case VME_USER4: default: dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); return -EINVAL; break; } /* * Bound address is a valid address for the window, adjust * accordingly */ vme_bound = vme_base + size; pci_offset = pci_base - vme_base; if ((i == 0) || (i == 4)) granularity = 0x1000; else granularity = 0x10000; if (vme_base & (granularity - 1)) { dev_err(ca91cx42_bridge->parent, "Invalid VME base " "alignment\n"); return -EINVAL; } if (vme_bound & (granularity - 1)) { dev_err(ca91cx42_bridge->parent, "Invalid VME bound " "alignment\n"); return -EINVAL; } if (pci_offset & (granularity - 1)) { dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset " "alignment\n"); return -EINVAL; } /* Disable while we are mucking around */ temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); temp_ctl &= ~CA91CX42_VSI_CTL_EN; iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); /* Setup mapping */ iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); /* Setup address space */ temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; temp_ctl |= addr; /* Setup cycle types */ temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M); if (cycle & VME_SUPER) temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR; if (cycle & VME_USER) temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV; if (cycle & VME_PROG) temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM; if (cycle & VME_DATA) temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA; /* Write ctl reg without enable */ iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); if (enabled) temp_ctl |= CA91CX42_VSI_CTL_EN; iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); return 0; }

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Martyn Welch44699.78%583.33%
Emilio G. Cota10.22%116.67%
Total447100.00%6100.00%


static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, unsigned long long *vme_base, unsigned long long *size, dma_addr_t *pci_base, u32 *aspace, u32 *cycle) { unsigned int i, granularity = 0, ctl = 0; unsigned long long vme_bound, pci_offset; struct ca91cx42_driver *bridge; bridge = image->parent->driver_priv; i = image->number; if ((i == 0) || (i == 4)) granularity = 0x1000; else granularity = 0x10000; /* Read Registers */ ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); *pci_base = (dma_addr_t)*vme_base + pci_offset; *size = (unsigned long long)((vme_bound - *vme_base) + granularity); *enabled = 0; *aspace = 0; *cycle = 0; if (ctl & CA91CX42_VSI_CTL_EN) *enabled = 1; if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) *aspace = VME_A16; if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) *aspace = VME_A24; if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) *aspace = VME_A32; if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) *aspace = VME_USER1; if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) *aspace = VME_USER2; if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) *cycle |= VME_SUPER; if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) *cycle |= VME_USER; if (ctl & CA91CX42_VSI_CTL_PGM_PGM) *cycle |= VME_PROG; if (ctl & CA91CX42_VSI_CTL_PGM_DATA) *cycle |= VME_DATA; return 0; }

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Martyn Welch33499.40%466.67%
Augusto Mecking Caringi10.30%116.67%
Emilio G. Cota10.30%116.67%
Total336100.00%6100.00%

/* * Allocate and map PCI Resource */
static int ca91cx42_alloc_resource(struct vme_master_resource *image, unsigned long long size) { unsigned long long existing_size; int retval = 0; struct pci_dev *pdev; struct vme_bridge *ca91cx42_bridge; ca91cx42_bridge = image->parent; /* Find pci_dev container of dev */ if (ca91cx42_bridge->parent == NULL) { dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n"); return -EINVAL; } pdev = to_pci_dev(ca91cx42_bridge->parent); existing_size = (unsigned long long)(image->bus_resource.end - image->bus_resource.start); /* If the existing size is OK, return */ if (existing_size == (size - 1)) return 0; if (existing_size != 0) { iounmap(image->kern_base); image->kern_base = NULL; kfree(image->bus_resource.name); release_resource(&image->bus_resource); memset(&image->bus_resource, 0, sizeof(struct resource)); } if (image->bus_resource.name == NULL) { image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); if (image->bus_resource.name == NULL) { dev_err(ca91cx42_bridge->parent, "Unable to allocate " "memory for resource name\n"); retval = -ENOMEM; goto err_name; } } sprintf((char *)image->bus_resource.name, "%s.%d", ca91cx42_bridge->name, image->number); image->bus_resource.start = 0; image->bus_resource.end = (unsigned long)size; image->bus_resource.flags = IORESOURCE_MEM; retval = pci_bus_alloc_resource(pdev->bus, &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM, 0, NULL, NULL); if (retval) { dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " "resource for window %d size 0x%lx start 0x%lx\n", image->number, (unsigned long)size, (unsigned long)image->bus_resource.start); goto err_resource; } image->kern_base = ioremap_nocache( image->bus_resource.start, size); if (image->kern_base == NULL) { dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n"); retval = -ENOMEM; goto err_remap; } return 0; err_remap: release_resource(&image->bus_resource); err_resource: kfree(image->bus_resource.name); memset(&image->bus_resource, 0, sizeof(struct resource)); err_name: return retval; }

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Martyn Welch42199.29%562.50%
Dmitry Kalinkin10.24%112.50%
Geliang Tang10.24%112.50%
Julia Lawall10.24%112.50%
Total424100.00%8100.00%

/* * Free and unmap PCI Resource */
static void ca91cx42_free_resource(struct vme_master_resource *image) { iounmap(image->kern_base); image->kern_base = NULL; release_resource(&image->bus_resource); kfree(image->bus_resource.name); memset(&image->bus_resource, 0, sizeof(struct resource)); }

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Martyn Welch57100.00%3100.00%
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static int ca91cx42_master_set(struct vme_master_resource *image, int enabled, unsigned long long vme_base, unsigned long long size, u32 aspace, u32 cycle, u32 dwidth) { int retval = 0; unsigned int i, granularity = 0; unsigned int temp_ctl = 0; unsigned long long pci_bound, vme_offset, pci_base; struct vme_bridge *ca91cx42_bridge; struct ca91cx42_driver *bridge; ca91cx42_bridge = image->parent; bridge = ca91cx42_bridge->driver_priv; i = image->number; if ((i == 0) || (i == 4)) granularity = 0x1000; else granularity = 0x10000; /* Verify input data */ if (vme_base & (granularity - 1)) { dev_err(ca91cx42_bridge->parent, "Invalid VME Window " "alignment\n"); retval = -EINVAL; goto err_window; } if (size & (granularity - 1)) { dev_err(ca91cx42_bridge->parent, "Invalid VME Window " "alignment\n"); retval = -EINVAL; goto err_window; } spin_lock(&image->lock); /* * Let's allocate the resource here rather than further up the stack as * it avoids pushing loads of bus dependent stuff up the stack */ retval = ca91cx42_alloc_resource(image, size); if (retval) { spin_unlock(&image->lock); dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " "for resource name\n"); retval = -ENOMEM; goto err_res; } pci_base = (unsigned long long)image->bus_resource.start; /* * Bound address is a valid address for the window, adjust * according to window granularity. */ pci_bound = pci_base + size; vme_offset = vme_base - pci_base; /* Disable while we are mucking around */ temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); temp_ctl &= ~CA91CX42_LSI_CTL_EN; iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); /* Setup cycle types */ temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M; if (cycle & VME_BLT) temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT; if (cycle & VME_MBLT) temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT; /* Setup data width */ temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M; switch (dwidth) { case VME_D8: temp_ctl |= CA91CX42_LSI_CTL_VDW_D8; break; case VME_D16: temp_ctl |= CA91CX42_LSI_CTL_VDW_D16; break; case VME_D32: temp_ctl |= CA91CX42_LSI_CTL_VDW_D32; break; case VME_D64: temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; break; default: spin_unlock(&image->lock); dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); retval = -EINVAL; goto err_dwidth; break; } /* Setup address space */ temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M; switch (aspace)</