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Release 4.14 drivers/vme/bridges/vme_tsi148.c

/*
 * Support for the Tundra TSI148 VME-PCI Bridge Chip
 *
 * Author: Martyn Welch <martyn.welch@ge.com>
 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
 *
 * Based on work by Tom Armistead and Ajit Prem
 * Copyright 2004 Motorola Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/byteorder/generic.h>
#include <linux/vme.h>

#include "../vme_bridge.h"
#include "vme_tsi148.h"

static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
static void tsi148_remove(struct pci_dev *);


/* Module parameter */

static bool err_chk;

static int geoid;


static const char driver_name[] = "vme_tsi148";


static const struct pci_device_id tsi148_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
	{ },
};

MODULE_DEVICE_TABLE(pci, tsi148_ids);


static struct pci_driver tsi148_driver = {
	.name = driver_name,
	.id_table = tsi148_ids,
	.probe = tsi148_probe,
	.remove = tsi148_remove,
};


static void reg_join(unsigned int high, unsigned int low, unsigned long long *variable) { *variable = (unsigned long long)high << 32; *variable |= (unsigned long long)low; }

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static void reg_split(unsigned long long variable, unsigned int *high, unsigned int *low) { *low = (unsigned int)variable & 0xFFFFFFFF; *high = (unsigned int)(variable >> 32); }

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/* * Wakes up DMA queue. */
static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, int channel_mask) { u32 serviced = 0; if (channel_mask & TSI148_LCSR_INTS_DMA0S) { wake_up(&bridge->dma_queue[0]); serviced |= TSI148_LCSR_INTC_DMA0C; } if (channel_mask & TSI148_LCSR_INTS_DMA1S) { wake_up(&bridge->dma_queue[1]); serviced |= TSI148_LCSR_INTC_DMA1C; } return serviced; }

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/* * Wake up location monitor queue */
static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) { int i; u32 serviced = 0; for (i = 0; i < 4; i++) { if (stat & TSI148_LCSR_INTS_LMS[i]) { /* We only enable interrupts if the callback is set */ bridge->lm_callback[i](bridge->lm_data[i]); serviced |= TSI148_LCSR_INTC_LMC[i]; } } return serviced; }

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/* * Wake up mail box queue. * * XXX This functionality is not exposed up though API. */
static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) { int i; u32 val; u32 serviced = 0; struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; for (i = 0; i < 4; i++) { if (stat & TSI148_LCSR_INTS_MBS[i]) { val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); dev_err(tsi148_bridge->parent, "VME Mailbox %d received" ": 0x%x\n", i, val); serviced |= TSI148_LCSR_INTC_MBC[i]; } } return serviced; }

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/* * Display error & status message when PERR (PCI) exception interrupt occurs. */
static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) { struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " "attributes: %08x\n", ioread32be(bridge->base + TSI148_LCSR_EDPAU), ioread32be(bridge->base + TSI148_LCSR_EDPAL), ioread32be(bridge->base + TSI148_LCSR_EDPAT)); dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " "completion reg: %08x\n", ioread32be(bridge->base + TSI148_LCSR_EDPXA), ioread32be(bridge->base + TSI148_LCSR_EDPXS)); iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); return TSI148_LCSR_INTC_PERRC; }

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/* * Save address and status when VME error interrupt occurs. */
static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) { unsigned int error_addr_high, error_addr_low; unsigned long long error_addr; u32 error_attrib; int error_am; struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); error_am = (error_attrib & TSI148_LCSR_VEAT_AM_M) >> 8; reg_join(error_addr_high, error_addr_low, &error_addr); /* Check for exception register overflow (we have lost error data) */ if (error_attrib & TSI148_LCSR_VEAT_VEOF) { dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " "Occurred\n"); } if (err_chk) vme_bus_error_handler(tsi148_bridge, error_addr, error_am); else dev_err(tsi148_bridge->parent, "VME Bus Error at address: 0x%llx, attributes: %08x\n", error_addr, error_attrib); /* Clear Status */ iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); return TSI148_LCSR_INTC_VERRC; }

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/* * Wake up IACK queue. */
static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) { wake_up(&bridge->iack_queue); return TSI148_LCSR_INTC_IACKC; }

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/* * Calling VME bus interrupt callback if provided. */
static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) { int vec, i, serviced = 0; struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; for (i = 7; i > 0; i--) { if (stat & (1 << i)) { /* * Note: Even though the registers are defined as * 32-bits in the spec, we only want to issue 8-bit * IACK cycles on the bus, read from offset 3. */ vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); vme_irq_handler(tsi148_bridge, i, vec); serviced |= (1 << i); } } return serviced; }

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/* * Top level interrupt handler. Clears appropriate interrupt status bits and * then calls appropriate sub handler(s). */
static irqreturn_t tsi148_irqhandler(int irq, void *ptr) { u32 stat, enable, serviced = 0; struct vme_bridge *tsi148_bridge; struct tsi148_driver *bridge; tsi148_bridge = ptr; bridge = tsi148_bridge->driver_priv; /* Determine which interrupts are unmasked and set */ enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); stat = ioread32be(bridge->base + TSI148_LCSR_INTS); /* Only look at unmasked interrupts */ stat &= enable; if (unlikely(!stat)) return IRQ_NONE; /* Call subhandlers as appropriate */ /* DMA irqs */ if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) serviced |= tsi148_DMA_irqhandler(bridge, stat); /* Location monitor irqs */ if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) serviced |= tsi148_LM_irqhandler(bridge, stat); /* Mail box irqs */ if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); /* PCI bus error */ if (stat & TSI148_LCSR_INTS_PERRS) serviced |= tsi148_PERR_irqhandler(tsi148_bridge); /* VME bus error */ if (stat & TSI148_LCSR_INTS_VERRS) serviced |= tsi148_VERR_irqhandler(tsi148_bridge); /* IACK irq */ if (stat & TSI148_LCSR_INTS_IACKS) serviced |= tsi148_IACK_irqhandler(bridge); /* VME bus irqs */ if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | TSI148_LCSR_INTS_IRQ1S)) serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); /* Clear serviced interrupts */ iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); return IRQ_HANDLED; }

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static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) { int result; unsigned int tmp; struct pci_dev *pdev; struct tsi148_driver *bridge; pdev = to_pci_dev(tsi148_bridge->parent); bridge = tsi148_bridge->driver_priv; result = request_irq(pdev->irq, tsi148_irqhandler, IRQF_SHARED, driver_name, tsi148_bridge); if (result) { dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " "vector %02X\n", pdev->irq); return result; } /* Enable and unmask interrupts */ tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO | TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO | TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO | TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | TSI148_LCSR_INTEO_IACKEO; /* This leaves the following interrupts masked. * TSI148_LCSR_INTEO_VIEEO * TSI148_LCSR_INTEO_SYSFLEO * TSI148_LCSR_INTEO_ACFLEO */ /* Don't enable Location Monitor interrupts here - they will be * enabled when the location monitors are properly configured and * a callback has been attached. * TSI148_LCSR_INTEO_LM0EO * TSI148_LCSR_INTEO_LM1EO * TSI148_LCSR_INTEO_LM2EO * TSI148_LCSR_INTEO_LM3EO */ /* Don't enable VME interrupts until we add a handler, else the board * will respond to it and we don't want that unless it knows how to * properly deal with it. * TSI148_LCSR_INTEO_IRQ7EO * TSI148_LCSR_INTEO_IRQ6EO * TSI148_LCSR_INTEO_IRQ5EO * TSI148_LCSR_INTEO_IRQ4EO * TSI148_LCSR_INTEO_IRQ3EO * TSI148_LCSR_INTEO_IRQ2EO * TSI148_LCSR_INTEO_IRQ1EO */ iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); return 0; }

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static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge, struct pci_dev *pdev) { struct tsi148_driver *bridge = tsi148_bridge->driver_priv; /* Turn off interrupts */ iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); /* Clear all interrupts */ iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); /* Detach interrupt handler */ free_irq(pdev->irq, tsi148_bridge); }

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/* * Check to see if an IACk has been received, return true (1) or false (0). */
static int tsi148_iack_received(struct tsi148_driver *bridge) { u32 tmp; tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); if (tmp & TSI148_LCSR_VICR_IRQS) return 0; else return 1; }

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/* * Configure VME interrupt */
static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, int state, int sync) { struct pci_dev *pdev; u32 tmp; struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; /* We need to do the ordering differently for enabling and disabling */ if (state == 0) { tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); if (sync != 0) { pdev = to_pci_dev(tsi148_bridge->parent); synchronize_irq(pdev->irq); } } else { tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); } }

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/* * Generate a VME bus interrupt at the requested level & vector. Wait for * interrupt to be acked. */
static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid) { u32 tmp; struct tsi148_driver *bridge; bridge = tsi148_bridge->driver_priv; mutex_lock(&bridge->vme_int); /* Read VICR register */ tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); /* Set Status/ID */ tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | (statid & TSI148_LCSR_VICR_STID_M); iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* Assert VMEbus IRQ */ tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* XXX Consider implementing a timeout? */ wait_event_interruptible(bridge->iack_queue, tsi148_iack_received(bridge)); mutex_unlock(&bridge->vme_int); return 0; }

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/* * Initialize a slave window with the requested attributes. */
static int tsi148_slave_set(struct vme_slave_resource *image, int enabled, unsigned long long vme_base, unsigned long long size, dma_addr_t pci_base, u32 aspace, u32 cycle) { unsigned int i, addr = 0, granularity = 0; unsigned int temp_ctl = 0; unsigned int vme_base_low, vme_base_high; unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; struct vme_bridge *tsi148_bridge; struct tsi148_driver *bridge; tsi148_bridge = image->parent; bridge = tsi148_bridge->driver_priv; i = image->number; switch (aspace) { case VME_A16: granularity = 0x10; addr |= TSI148_LCSR_ITAT_AS_A16; break; case VME_A24: granularity = 0x1000; addr |= TSI148_LCSR_ITAT_AS_A24; break; case VME_A32: granularity = 0x10000; addr |= TSI148_LCSR_ITAT_AS_A32; break; case VME_A64: granularity = 0x10000; addr |= TSI148_LCSR_ITAT_AS_A64; break; default: dev_err(tsi148_bridge->parent, "Invalid address space\n"); return -EINVAL; break; } /* Convert 64-bit variables to 2x 32-bit variables */ reg_split(vme_base, &vme_base_high, &vme_base_low); /* * Bound address is a valid address for the window, adjust * accordingly */ vme_bound = vme_base + size - granularity; reg_split(vme_bound, &vme_bound_high, &vme_bound_low); pci_offset = (unsigned long long)pci_base - vme_base; reg_split(pci_offset, &pci_offset_high, &pci_offset_low); if (vme_base_low & (granularity - 1)) { dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); return -EINVAL; } if (vme_bound_low & (granularity - 1)) { dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); return -EINVAL; } if (pci_offset_low & (granularity - 1)) { dev_err(tsi148_bridge->parent, "Invalid PCI Offset " "alignment\n"); return -EINVAL; } /* Disable while we are mucking around */ temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); temp_ctl &= ~TSI148_LCSR_ITAT_EN; iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); /* Setup mapping */ iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); /* Setup 2eSST speeds */ temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { case VME_2eSST160: temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; break; case VME_2eSST267: temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; break; case VME_2eSST320: temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; break; } /* Setup cycle types */ temp_ctl &= ~(0x1F << 7); if (cycle & VME_BLT) temp_ctl |= TSI148_LCSR_ITAT_BLT; if (cycle & VME_MBLT) temp_ctl |= TSI148_LCSR_ITAT_MBLT; if (cycle & VME_2eVME) temp_ctl |= TSI148_LCSR_ITAT_2eVME; if (cycle & VME_2eSST) temp_ctl |= TSI148_LCSR_ITAT_2eSST; if (cycle & VME_2eSSTB) temp_ctl |= TSI148_LCSR_ITAT_2eSSTB; /* Setup address space */ temp_ctl &= ~TSI148_LCSR_ITAT_AS_M; temp_ctl |= addr; temp_ctl &= ~0xF; if (cycle & VME_SUPER) temp_ctl |= TSI148_LCSR_ITAT_SUPR ; if (cycle & VME_USER) temp_ctl |= TSI148_LCSR_ITAT_NPRIV; if (cycle & VME_PROG) temp_ctl |= TSI148_LCSR_ITAT_PGM; if (cycle & VME_DATA) temp_ctl |= TSI148_LCSR_ITAT_DATA; /* Write ctl reg without enable */ iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); if (enabled) temp_ctl |= TSI148_LCSR_ITAT_EN; iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); return 0; }

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Total641100.00%5100.00%

/* * Get slave window configuration. */
static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, unsigned long long *vme_base, unsigned long long *size, dma_addr_t *pci_base, u32 *aspace, u32 *cycle) { unsigned int i, granularity = 0, ctl = 0; unsigned int vme_base_low, vme_base_high; unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; struct tsi148_driver *bridge; bridge = image->parent->driver_priv; i = image->number; /* Read registers */ ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); /* Convert 64-bit variables to 2x 32-bit variables */ reg_join(vme_base_high, vme_base_low, vme_base); reg_join(vme_bound_high, vme_bound_low, &vme_bound); reg_join(pci_offset_high, pci_offset_low, &pci_offset); *pci_base = (dma_addr_t)(*vme_base + pci_offset); *enabled = 0; *aspace = 0; *cycle = 0; if (ctl & TSI148_LCSR_ITAT_EN) *enabled = 1; if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) { granularity = 0x10; *aspace |= VME_A16; } if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) { granularity = 0x1000; *aspace |= VME_A24; } if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) { granularity = 0x10000; *aspace |= VME_A32; } if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) { granularity = 0x10000; *aspace |= VME_A64; } /* Need granularity before we set the size */ *size = (unsigned long long)((vme_bound - *vme_base) + granularity); if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160) *cycle |= VME_2eSST160; if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267) *cycle |= VME_2eSST267; if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320) *cycle |= VME_2eSST320; if (ctl & TSI148_LCSR_ITAT_BLT) *cycle |= VME_BLT; if (ctl & TSI148_LCSR_ITAT_MBLT) *cycle |= VME_MBLT; if (ctl & TSI148_LCSR_ITAT_2eVME) *cycle |= VME_2eVME; if (ctl & TSI148_LCSR_ITAT_2eSST) *cycle |= VME_2eSST; if (ctl & TSI148_LCSR_ITAT_2eSSTB) *cycle |= VME_2eSSTB; if (ctl & TSI148_LCSR_ITAT_SUPR) *cycle |= VME_SUPER; if (ctl & TSI148_LCSR_ITAT_NPRIV) *cycle |= VME_USER; if (ctl & TSI148_LCSR_ITAT_PGM) *cycle |= VME_PROG; if (ctl & TSI148_LCSR_ITAT_DATA) *cycle |= VME_DATA; return 0; }

Contributors

PersonTokensPropCommitsCommitProp
Martyn Welch52298.86%360.00%
Joe Schultz50.95%120.00%
Emilio G. Cota10.19%120.00%
Total528100.00%5100.00%

/* * Allocate and map PCI Resource */
static int tsi148_alloc_resource(struct vme_master_resource *image, unsigned long long size) { unsigned long long existing_size; int retval = 0; struct pci_dev *pdev; struct vme_bridge *tsi148_bridge; tsi148_bridge = image->parent; pdev = to_pci_dev(tsi148_bridge->parent); existing_size = (unsigned long long)(image->bus_resource.end - image->bus_resource.start); /* If the existing size is OK, return */ if ((size != 0) && (existing_size == (size - 1))) return 0; if (existing_size != 0) { iounmap(image->kern_base); image->kern_base = NULL; kfree(image->bus_resource.name); release_resource(&image->bus_resource); memset(&