Release 4.16 arch/x86/kernel/process.c

// SPDX-License-Identifier: GPL-2.0

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/sched/idle.h>
#include <linux/sched/debug.h>
#include <linux/sched/task.h>
#include <linux/sched/task_stack.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/pm.h>
#include <linux/tick.h>
#include <linux/random.h>
#include <linux/user-return-notifier.h>
#include <linux/dmi.h>
#include <linux/utsname.h>
#include <linux/stackprotector.h>
#include <linux/cpuidle.h>
#include <trace/events/power.h>
#include <linux/hw_breakpoint.h>
#include <asm/cpu.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <linux/uaccess.h>
#include <asm/mwait.h>
#include <asm/fpu/internal.h>
#include <asm/debugreg.h>
#include <asm/nmi.h>
#include <asm/tlbflush.h>
#include <asm/mce.h>
#include <asm/vm86.h>
#include <asm/switch_to.h>
#include <asm/desc.h>
#include <asm/prctl.h>

/*
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 * no more per-task TSS's. The TSS size is kept cacheline-aligned
 * so they are allowed to end up in the .data..cacheline_aligned
 * section. Since TSS's are completely CPU-local, we want them
 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 */
__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
	.x86_tss = {
		/*
                 * .sp0 is only used when entering ring 0 from a lower
                 * privilege level.  Since the init task never runs anything
                 * but ring 0 code, there is no need for a valid value here.
                 * Poison it.
                 */
		.sp0 = (1UL << (BITS_PER_LONG-1)) + 1,

#ifdef CONFIG_X86_64
		/*
                 * .sp1 is cpu_current_top_of_stack.  The init task never
                 * runs user code, but cpu_current_top_of_stack should still
                 * be well defined before the first context switch.
                 */
		.sp1 = TOP_OF_INIT_STACK,
#endif

#ifdef CONFIG_X86_32
		.ss0 = __KERNEL_DS,
		.ss1 = __KERNEL_CS,
		.io_bitmap_base	= INVALID_IO_BITMAP_OFFSET,
#endif
	 },
#ifdef CONFIG_X86_32
	 /*
          * Note that the .io_bitmap member must be extra-big. This is because
          * the CPU will access an additional byte beyond the end of the IO
          * permission bitmap. The extra byte must be all 1 bits, and must
          * be within the limit.
          */
	.io_bitmap		= { [0 ... IO_BITMAP_LONGS] = ~0 },
#endif
};
EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);

DEFINE_PER_CPU(bool, __tss_limit_invalid);
EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);

/*
 * this gets called so that we can store lazy state into memory and copy the
 * current task into the new thread.
 */


int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	memcpy(dst, src, arch_task_struct_size);
#ifdef CONFIG_VM86
	dst->thread.vm86 = NULL;
#endif

	return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
}

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/*
 * Free current thread data structures etc..
 */


void exit_thread(struct task_struct *tsk)
{
	struct thread_struct *t = &tsk->thread;
	unsigned long *bp = t->io_bitmap_ptr;
	struct fpu *fpu = &t->fpu;

	if (bp) {
		struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
                 * Careful, clear this in the TSS too:
                 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	free_vm86(t);

	fpu__drop(fpu);
}

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void flush_thread(void)
{
	struct task_struct *tsk = current;

	flush_ptrace_hw_breakpoint(tsk);
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));

	fpu__clear(&tsk->thread.fpu);
}

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void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
                 * Must flip the CPU state synchronously with
                 * TIF_NOTSC in the current running context.
                 */
		cr4_set_bits(X86_CR4_TSD);
	preempt_enable();
}

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static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
                 * Must flip the CPU state synchronously with
                 * TIF_NOTSC in the current running context.
                 */
		cr4_clear_bits(X86_CR4_TSD);
	preempt_enable();
}

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int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

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int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

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DEFINE_PER_CPU(u64, msr_misc_features_shadow);



static void set_cpuid_faulting(bool on)
{
	u64 msrval;

	msrval = this_cpu_read(msr_misc_features_shadow);
	msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
	msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
	this_cpu_write(msr_misc_features_shadow, msrval);
	wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
}

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static void disable_cpuid(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOCPUID)) {
		/*
                 * Must flip the CPU state synchronously with
                 * TIF_NOCPUID in the current running context.
                 */
		set_cpuid_faulting(true);
	}
	preempt_enable();
}

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static void enable_cpuid(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOCPUID)) {
		/*
                 * Must flip the CPU state synchronously with
                 * TIF_NOCPUID in the current running context.
                 */
		set_cpuid_faulting(false);
	}
	preempt_enable();
}

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static int get_cpuid_mode(void)
{
	return !test_thread_flag(TIF_NOCPUID);
}

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static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
{
	if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
		return -ENODEV;

	if (cpuid_enabled)
		enable_cpuid();
	else
		disable_cpuid();

	return 0;
}

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/*
 * Called immediately after a successful exec.
 */


void arch_setup_new_exec(void)
{
	/* If cpuid was previously disabled for this task, re-enable it. */
	if (test_thread_flag(TIF_NOCPUID))
		enable_cpuid();
}

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static inline void switch_to_bitmap(struct tss_struct *tss,
				    struct thread_struct *prev,
				    struct thread_struct *next,
				    unsigned long tifp, unsigned long tifn)
{
	if (tifn & _TIF_IO_BITMAP) {
		/*
                 * Copy the relevant range of the IO bitmap.
                 * Normally this is 128 bytes or less:
                 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
		/*
                 * Make sure that the TSS limit is correct for the CPU
                 * to notice the IO bitmap.
                 */
		refresh_tss_limit();
	} else if (tifp & _TIF_IO_BITMAP) {
		/*
                 * Clear any possible leftover bits:
                 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
}

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void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;
	unsigned long tifp, tifn;

	prev = &prev_p->thread;
	next = &next_p->thread;

	tifn = READ_ONCE(task_thread_info(next_p)->flags);
	tifp = READ_ONCE(task_thread_info(prev_p)->flags);
	switch_to_bitmap(tss, prev, next, tifp, tifn);

	propagate_user_return_notify(prev_p, next_p);

	if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
	    arch_has_block_step()) {
		unsigned long debugctl, msk;

		rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
		debugctl &= ~DEBUGCTLMSR_BTF;
		msk = tifn & _TIF_BLOCKSTEP;
		debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
		wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
	}

	if ((tifp ^ tifn) & _TIF_NOTSC)
		cr4_toggle_bits_irqsoff(X86_CR4_TSD);

	if ((tifp ^ tifn) & _TIF_NOCPUID)
		set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
}

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/*
 * Idle related variables and functions
 */

unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
EXPORT_SYMBOL(boot_option_idle_override);


static void (*x86_idle)(void);

#ifndef CONFIG_SMP


static inline void play_dead(void)
{
	BUG();
}
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#endif



void arch_cpu_idle_enter(void)
{
	tsc_verify_tsc_adjust(false);
	local_touch_nmi();
}

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void arch_cpu_idle_dead(void)
{
	play_dead();
}

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/*
 * Called from the generic idle code.
 */


void arch_cpu_idle(void)
{
	x86_idle();
}

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/*
 * We use this if we don't have any better idle routine..
 */


void __cpuidle default_idle(void)
{
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	safe_halt();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
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#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

#ifdef CONFIG_XEN


bool xen_set_default_idle(void)
{
	bool ret = !!x86_idle;

	x86_idle = default_idle;

	return ret;
}
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#endif



void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
         * Remove this CPU:
         */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();
	mcheck_cpu_clear(this_cpu_ptr(&cpu_info));

	/*
         * Use wbinvd on processors that support SME. This provides support
         * for performing a successful kexec when going from SME inactive
         * to SME active (or vice-versa). The cache must be cleared so that
         * if there are entries with the same physical address, both with and
         * without the encryption bit, they don't race each other when flushed
         * and potentially end up with the wrong entry being committed to
         * memory.
         */
	if (boot_cpu_has(X86_FEATURE_SME))
		native_wbinvd();
	for (;;) {
		/*
                 * Use native_halt() so that memory contents don't change
                 * (stack usage and variables) after possibly issuing the
                 * native_wbinvd() above.
                 */
		native_halt();
	}
}

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/*
 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 * states (local apic timer and TSC stop).
 */


static void amd_e400_idle(void)
{
	/*
         * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
         * gets set after static_cpu_has() places have been converted via
         * alternatives.
         */
	if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
		default_idle();
		return;
	}

	tick_broadcast_enter();

	default_idle();

	/*
         * The switch back from broadcast mode needs to be called with
         * interrupts disabled.
         */
	local_irq_disable();
	tick_broadcast_exit();
	local_irq_enable();
}

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/*
 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 * We can't rely on cpuidle installing MWAIT, because it will not load
 * on systems that support only C1 -- so the boot default must be MWAIT.
 *
 * Some AMD machines are the opposite, they depend on using HALT.
 *
 * So for default C1, which is used during boot until cpuidle loads,
 * use MWAIT-C1 on Intel HW that has it, else use HALT.
 */


static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return 0;

	if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
		return 0;

	return 1;
}

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/*
 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 * with interrupts enabled and no flags, which is backwards compatible with the
 * original MWAIT implementation.
 */


static __cpuidle void mwait_idle(void)
{
	if (!current_set_polling_and_test()) {
		trace_cpu_idle_rcuidle(1, smp_processor_id());
		if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
			mb(); /* quirk */
			clflush((void *)&current_thread_info()->flags);
			mb(); /* quirk */
		}

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		if (!need_resched())
			__sti_mwait(0, 0);
		else
			local_irq_enable();
		trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
	} else {
		local_irq_enable();
	}
	__current_clr_polling();
}

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void select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
#endif
	if (x86_idle || boot_option_idle_override == IDLE_POLL)
		return;

	if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
		pr_info("using AMD E400 aware idle routine\n");
		x86_idle = amd_e400_idle;
	} else if (prefer_mwait_c1_over_halt(c)) {
		pr_info("using mwait in idle threads\n");
		x86_idle = mwait_idle;
	} else
		x86_idle = default_idle;
}

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void amd_e400_c1e_apic_setup(void)
{
	if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
		pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
		local_irq_disable();
		tick_broadcast_force();
		local_irq_enable();
	}
}

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void __init arch_post_acpi_subsys_init(void)
{
	u32 lo, hi;

	if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
		return;

	/*
         * AMD E400 detection needs to happen after ACPI has been enabled. If
         * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
         * MSR_K8_INT_PENDING_MSG.
         */
	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
	if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
		return;

	boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);

	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
		mark_tsc_unstable("TSC halt in AMD C1E");
	pr_info("System has AMD C1E enabled\n");
}

Contributors
Person
Tokens
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Commits
CommitProp
Thomas Gleixner
65
100.00%
1
100.00%
Total
65
100.00%
1
100.00%



static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		pr_info("using polling idle threads\n");
		boot_option_idle_override = IDLE_POLL;
		cpu_idle_poll_ctrl(true);
	} else if (!strcmp(str, "halt")) {
		/*
                 * When the boot option of idle=halt is added, halt is
                 * forced to be used for CPU idle. In such case CPU C2/C3
                 * won't be used again.
                 * To continue to load the CPU idle driver, don't touch
                 * the boot_option_idle_override.
                 */
		x86_idle = default_idle;
		boot_option_idle_override = IDLE_HALT;
	} else if (!strcmp(str, "nomwait")) {
		/*
                 * If the boot option of "idle=nomwait" is added,
                 * it means that mwait will be disabled for CPU C2/C3
                 * states. In such case it won't touch the variable
                 * of boot_option_idle_override.
                 */
		boot_option_idle_override = IDLE_NOMWAIT;
	} else
		return -1;

	return 0;
}
Contributors
Person
Tokens
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Commits
CommitProp
Peter Zijlstra
42
44.68%
1
12.50%
Yakui Zhao
27
28.72%
2
25.00%
Cyrill V. Gorcunov
9
9.57%
1
12.50%
Thomas Renninger
8
8.51%
1
12.50%
Thomas Gleixner
5
5.32%
1
12.50%
Joe Perches
2
2.13%
1
12.50%
Len Brown
1
1.06%
1
12.50%
Total
94
100.00%
8
100.00%

early_param("idle", idle_setup);



unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

Contributors
Person
Tokens
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CommitProp
Américo Wang
36
100.00%
1
100.00%
Total
36
100.00%
1
100.00%



unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	return randomize_page(mm->brk, 0x02000000);
}

Contributors
Person
Tokens
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Commits
CommitProp
Américo Wang
19
90.48%
1
50.00%
Jason Cooper
2
9.52%
1
50.00%
Total
21
100.00%
2
100.00%

/*
 * Called from fs/proc with a reference on @p to find the function
 * which called into schedule(). This needs to be done carefully
 * because the task might wake up and we might look at a stack
 * changing under us.
 */


unsigned long get_wchan(struct task_struct *p)
{
	unsigned long start, bottom, top, sp, fp, ip, ret = 0;
	int count = 0;

	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	if (!try_get_task_stack(p))
		return 0;

	start = (unsigned long)task_stack_page(p);
	if (!start)
		goto out;

	/*
         * Layout of the stack page:
         *
         * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
         * PADDING
         * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
         * stack
         * ----------- bottom = start
         *
         * The tasks stack pointer points at the location where the
         * framepointer is stored. The data on the stack is:
         * ... IP FP ... IP FP
         *
         * We need to read FP and IP, so we need to adjust the upper
         * bound by another unsigned long.
         */
	top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
	top -= 2 * sizeof(unsigned long);
	bottom = start;

	sp = READ_ONCE(p->thread.sp);
	if (sp < bottom || sp > top)
		goto out;

	fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
	do {
		if (fp < bottom || fp > top)
			goto out;
		ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
		if (!in_sched_functions(ip)) {
			ret = ip;
			goto out;
		}
		fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
	} while (count++ < 16 && p->state != TASK_RUNNING);

out:
	put_task_stack(p);
	return ret;
}

Contributors
Person
Tokens
Prop
Commits
CommitProp
Thomas Gleixner
186
78.81%
1
20.00%
Andrew Lutomirski
41
17.37%
2
40.00%
Brian Gerst
6
2.54%
1
20.00%
Andrey Ryabinin
3
1.27%
1
20.00%
Total
236
100.00%
5
100.00%



long do_arch_prctl_common(struct task_struct *task, int option,
			  unsigned long cpuid_enabled)
{
	switch (option) {
	case ARCH_GET_CPUID:
		return get_cpuid_mode();
	case ARCH_SET_CPUID:
		return set_cpuid_mode(task, cpuid_enabled);
	}

	return -EINVAL;
}
Contributors
Person
Tokens
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CommitProp
Kyle Huey
45
100.00%
2
100.00%
Total
45
100.00%
2
100.00%

Overall Contributors
Person
Tokens
Prop
Commits
CommitProp
Kyle Huey
432
21.28%
4
3.92%
Thomas Gleixner
403
19.85%
14
13.73%
Jeremy Fitzhardinge
298
14.68%
1
0.98%
Len Brown
153
7.54%
4
3.92%
Andrew Lutomirski
148
7.29%
11
10.78%
Peter Zijlstra
101
4.98%
3
2.94%
Américo Wang
58
2.86%
1
0.98%
Suresh B. Siddha
51
2.51%
3
2.94%
Richard Weinberger
35
1.72%
1
0.98%
Ingo Molnar
33
1.63%
11
10.78%
Borislav Petkov
30
1.48%
2
1.96%
Yakui Zhao
29
1.43%
2
1.96%
Ivan Vecera
28
1.38%
1
0.98%
Thomas Renninger
23
1.13%
3
2.94%
Rusty Russell
22
1.08%
3
2.94%
Konrad Rzeszutek Wilk
18
0.89%
1
0.98%
Tom Lendacky
17
0.84%
2
1.96%
JiSheng Zhang
16
0.79%
1
0.98%
Brian Gerst
15
0.74%
2
1.96%
Mike Galbraith
14
0.69%
1
0.98%
Ashok Raj
12
0.59%
1
0.98%
Joe Perches
12
0.59%
1
0.98%
Cyrill V. Gorcunov
9
0.44%
1
0.98%
Avi Kivity
8
0.39%
2
1.96%
Dave Hansen
6
0.30%
1
0.98%
Andi Kleen
6
0.30%
1
0.98%
Andy Isaacson
6
0.30%
1
0.98%
Linus Torvalds
5
0.25%
3
2.94%
Jaswinder Singh Rajput
5
0.25%
2
1.96%
Jiri Slaby
4
0.20%
1
0.98%
Paul Gortmaker
4
0.20%
1
0.98%
Frédéric Weisbecker
4
0.20%
1
0.98%
Arjan van de Ven
3
0.15%
2
1.96%
K.Prasad
3
0.15%
1
0.98%
Andrey Ryabinin
3
0.15%
1
0.98%
Steven Rostedt
2
0.10%
1
0.98%
Michael S. Tsirkin
2
0.10%
1
0.98%
Chris Metcalf
2
0.10%
1
0.98%
Andy Whitcroft
2
0.10%
1
0.98%
Jason Cooper
2
0.10%
1
0.98%
Huang Rui
1
0.05%
1
0.98%
Nick Desaulniers
1
0.05%
1
0.98%
Nadav Amit
1
0.05%
1
0.98%
Oleg Nesterov
1
0.05%
1
0.98%
Greg Kroah-Hartman
1
0.05%
1
0.98%
Marc Dionne
1
0.05%
1
0.98%
Total
2030
100.00%
102
100.00%
Directory: arch/x86/kernel

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