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Release 4.16 drivers/platform/chrome/cros_ec_lpc_mec.c

/*
 * cros_ec_lpc_mec - LPC variant I/O for Microchip EC
 *
 * Copyright (C) 2016 Google, Inc
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * This driver uses the Chrome OS EC byte-level message-based protocol for
 * communicating the keyboard state (which keys are pressed) from a keyboard EC
 * to the AP over some bus (such as i2c, lpc, spi).  The EC does debouncing,
 * but everything else (including deghosting) is done here.  The main
 * motivation for this is to keep the EC firmware as simple as possible, since
 * it cannot be easily upgraded and EC flash/IRAM space is relatively
 * expensive.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/cros_ec_commands.h>
#include <linux/mfd/cros_ec_lpc_mec.h>
#include <linux/mutex.h>
#include <linux/types.h>

/*
 * This mutex must be held while accessing the EMI unit. We can't rely on the
 * EC mutex because memmap data may be accessed without it being held.
 */

static struct mutex io_mutex;

/*
 * cros_ec_lpc_mec_emi_write_address
 *
 * Initialize EMI read / write at a given address.
 *
 * @addr:        Starting read / write address
 * @access_type: Type of access, typically 32-bit auto-increment
 */

static void cros_ec_lpc_mec_emi_write_address(u16 addr, enum cros_ec_lpc_mec_emi_access_mode access_type) { /* Address relative to start of EMI range */ addr -= MEC_EMI_RANGE_START; outb((addr & 0xfc) | access_type, MEC_EMI_EC_ADDRESS_B0); outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1); }

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/* * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port * * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request * @offset: Base read / write address * @length: Number of bytes to read / write * @buf: Destination / source buffer * * @return 8-bit checksum of all bytes read / written */
u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, unsigned int offset, unsigned int length, u8 *buf) { int i = 0; int io_addr; u8 sum = 0; enum cros_ec_lpc_mec_emi_access_mode access, new_access; /* * Long access cannot be used on misaligned data since reading B0 loads * the data register and writing B3 flushes. */ if (offset & 0x3 || length < 4) access = ACCESS_TYPE_BYTE; else access = ACCESS_TYPE_LONG_AUTO_INCREMENT; mutex_lock(&io_mutex); /* Initialize I/O at desired address */ cros_ec_lpc_mec_emi_write_address(offset, access); /* Skip bytes in case of misaligned offset */ io_addr = MEC_EMI_EC_DATA_B0 + (offset & 0x3); while (i < length) { while (io_addr <= MEC_EMI_EC_DATA_B3) { if (io_type == MEC_IO_READ) buf[i] = inb(io_addr++); else outb(buf[i], io_addr++); sum += buf[i++]; offset++; /* Extra bounds check in case of misaligned length */ if (i == length) goto done; } /* * Use long auto-increment access except for misaligned write, * since writing B3 triggers the flush. */ if (length - i < 4 && io_type == MEC_IO_WRITE) new_access = ACCESS_TYPE_BYTE; else new_access = ACCESS_TYPE_LONG_AUTO_INCREMENT; if (new_access != access || access != ACCESS_TYPE_LONG_AUTO_INCREMENT) { access = new_access; cros_ec_lpc_mec_emi_write_address(offset, access); } /* Access [B0, B3] on each loop pass */ io_addr = MEC_EMI_EC_DATA_B0; } done: mutex_unlock(&io_mutex); return sum; }

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EXPORT_SYMBOL(cros_ec_lpc_io_bytes_mec);
void cros_ec_lpc_mec_init(void) { mutex_init(&io_mutex); }

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EXPORT_SYMBOL(cros_ec_lpc_mec_init);
void cros_ec_lpc_mec_destroy(void) { mutex_destroy(&io_mutex); }

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EXPORT_SYMBOL(cros_ec_lpc_mec_destroy);

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