Release 4.17 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dc.h"
#include "core_types.h"
#include "dce112_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
/* include DCE11.2 register header files */
#include "dce/dce_11_2_d.h"
#include "dce/dce_11_2_sh_mask.h"
struct dce112_hw_seq_reg_offsets {
uint32_t crtc;
};
static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
/*******************************************************************************
* Private definitions
******************************************************************************/
static void dce112_init_pte(struct dc_context *ctx)
{
uint32_t addr;
uint32_t value = 0;
uint32_t chunk_int = 0;
uint32_t chunk_mul = 0;
addr = mmDVMM_PTE_REQ;
value = dm_read_reg(ctx, addr);
chunk_int = get_reg_field_value(
value,
DVMM_PTE_REQ,
HFLIP_PTEREQ_PER_CHUNK_INT);
chunk_mul = get_reg_field_value(
value,
DVMM_PTE_REQ,
HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
if (chunk_int != 0x4 || chunk_mul != 0x4) {
set_reg_field_value(
value,
255,
DVMM_PTE_REQ,
MAX_PTEREQ_TO_ISSUE);
set_reg_field_value(
value,
4,
DVMM_PTE_REQ,
HFLIP_PTEREQ_PER_CHUNK_INT);
set_reg_field_value(
value,
4,
DVMM_PTE_REQ,
HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
dm_write_reg(ctx, addr, value);
}
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Harry Wentland | 118 | 100.00% | 1 | 100.00% |
| Total | 118 | 100.00% | 1 | 100.00% |
static bool dce112_enable_display_power_gating(
struct dc *dc,
uint8_t controller_id,
struct dc_bios *dcb,
enum pipe_gating_control power_gating)
{
enum bp_result bp_result = BP_RESULT_OK;
enum bp_pipe_control_action cntl;
struct dc_context *ctx = dc->ctx;
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
return true;
if (power_gating == PIPE_GATING_CONTROL_INIT)
cntl = ASIC_PIPE_INIT;
else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
cntl = ASIC_PIPE_ENABLE;
else
cntl = ASIC_PIPE_DISABLE;
if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
bp_result = dcb->funcs->enable_disp_power_gating(
dcb, controller_id + 1, cntl);
/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
* by default when command table is called
*/
dm_write_reg(ctx,
HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
0);
}
if (power_gating != PIPE_GATING_CONTROL_ENABLE)
dce112_init_pte(ctx);
if (bp_result == BP_RESULT_OK)
return true;
else
return false;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Harry Wentland | 147 | 99.32% | 1 | 50.00% |
| Bhawanpreet Lakha | 1 | 0.68% | 1 | 50.00% |
| Total | 148 | 100.00% | 2 | 100.00% |
void dce112_hw_sequencer_construct(struct dc *dc)
{
/* All registers used by dce11.2 match those in dce11 in offset and
* structure
*/
dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Harry Wentland | 22 | 91.67% | 1 | 33.33% |
| Dave Airlie | 1 | 4.17% | 1 | 33.33% |
| Bhawanpreet Lakha | 1 | 4.17% | 1 | 33.33% |
| Total | 24 | 100.00% | 3 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Harry Wentland | 404 | 99.26% | 1 | 33.33% |
| Bhawanpreet Lakha | 2 | 0.49% | 1 | 33.33% |
| Dave Airlie | 1 | 0.25% | 1 | 33.33% |
| Total | 407 | 100.00% | 3 | 100.00% |
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