Release 4.17 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "vega10_thermal.h"
#include "vega10_hwmgr.h"
#include "vega10_ppsmc.h"
#include "vega10_inc.h"
#include "pp_soc15.h"
#include "pp_debug.h"
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
{
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
*current_rpm = smum_get_argument(hwmgr);
return 0;
}
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int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
struct phm_fan_speed_info *fan_speed_info)
{
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
fan_speed_info->supports_percent_read = true;
fan_speed_info->supports_percent_write = true;
fan_speed_info->min_percent = 0;
fan_speed_info->max_percent = 100;
if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
hwmgr->thermal_controller.fanInfo.
ucTachometerPulsesPerRevolution) {
fan_speed_info->supports_rpm_read = true;
fan_speed_info->supports_rpm_write = true;
fan_speed_info->min_rpm =
hwmgr->thermal_controller.fanInfo.ulMinRPM;
fan_speed_info->max_rpm =
hwmgr->thermal_controller.fanInfo.ulMaxRPM;
} else {
fan_speed_info->min_rpm = 0;
fan_speed_info->max_rpm = 0;
}
return 0;
}
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int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t *speed)
{
uint32_t current_rpm;
uint32_t percent = 0;
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
return -1;
if (hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM != 0)
percent = current_rpm * 100 /
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM;
*speed = percent > 100 ? 100 : percent;
return 0;
}
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int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
{
struct vega10_hwmgr *data = hwmgr->backend;
uint32_t tach_period;
uint32_t crystal_clock_freq;
int result = 0;
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return -1;
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
result = vega10_get_current_rpm(hwmgr, speed);
} else {
uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
tach_period =
CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_TACH_STATUS,
TACH_PERIOD);
if (tach_period == 0)
return -EINVAL;
crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
*speed = 60 * crystal_clock_freq * 10000 / tach_period;
}
return result;
}
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| Eric Huang | 126 | 88.11% | 1 | 33.33% |
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| Total | 143 | 100.00% | 3 | 100.00% |
/**
* Set Fan Speed Control to static mode,
* so that the user can decide what speed to use.
* @param hwmgr the address of the powerplay hardware manager.
* mode the fan control mode, 0 default, 1 by percent, 5, by RPM
* @exception Should always succeed.
*/
int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
uint32_t reg;
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
if (hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr->fan_ctrl_default_mode =
CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, FDO_PWM_MODE);
hwmgr->tmin =
CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, TMIN);
hwmgr->fan_ctrl_is_in_default_mode = false;
}
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, TMIN, 0));
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
return 0;
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 110 | 78.57% | 1 | 50.00% |
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| Total | 140 | 100.00% | 2 | 100.00% |
/**
* Reset Fan Speed Control to default mode.
* @param hwmgr the address of the powerplay hardware manager.
* @exception Should always succeed.
*/
int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
{
uint32_t reg;
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
if (!hwmgr->fan_ctrl_is_in_default_mode) {
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, FDO_PWM_MODE,
hwmgr->fan_ctrl_default_mode));
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, TMIN,
hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
hwmgr->fan_ctrl_is_in_default_mode = true;
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 88 | 84.62% | 1 | 50.00% |
| Tom St Denis | 16 | 15.38% | 1 | 50.00% |
| Total | 104 | 100.00% | 2 | 100.00% |
/**
* @fn vega10_enable_fan_control_feature
* @brief Enables the SMC Fan Control Feature.
*
* @param hwmgr - the address of the powerplay hardware manager.
* @return 0 on success. -1 otherwise.
*/
static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr, true,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
return -1);
data->smu_features[GNLD_FAN_CONTROL].enabled = true;
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 56 | 98.25% | 1 | 50.00% |
| Rex Zhu | 1 | 1.75% | 1 | 50.00% |
| Total | 57 | 100.00% | 2 | 100.00% |
static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr, false,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
return -1);
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 56 | 98.25% | 1 | 50.00% |
| Rex Zhu | 1 | 1.75% | 1 | 50.00% |
| Total | 57 | 100.00% | 2 | 100.00% |
int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return -1;
PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
"Attempt to Enable SMC FAN CONTROL Feature Failed!",
return -1);
return 0;
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 37 | 100.00% | 1 | 100.00% |
| Total | 37 | 100.00% | 1 | 100.00% |
int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return -1;
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
"Attempt to Disable SMC FAN CONTROL Feature Failed!",
return -1);
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 59 | 100.00% | 1 | 100.00% |
| Total | 59 | 100.00% | 1 | 100.00% |
/**
* Set Fan Speed in percent.
* @param hwmgr the address of the powerplay hardware manager.
* @param speed is the percentage value (0% - 100%) to be set.
* @exception Fails is the 100% setting appears to be 0.
*/
int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t speed)
{
uint32_t duty100;
uint32_t duty;
uint64_t tmp64;
uint32_t reg;
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
if (speed > 100)
speed = 100;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL1, FMAX_DUTY100);
if (duty100 == 0)
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
do_div(tmp64, 100);
duty = (uint32_t)tmp64;
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
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| Eric Huang | 156 | 90.70% | 1 | 33.33% |
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| Total | 172 | 100.00% | 3 | 100.00% |
/**
* Reset Fan Speed to default.
* @param hwmgr the address of the powerplay hardware manager.
* @exception Always succeeds.
*/
int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
{
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
else
return vega10_fan_ctrl_set_default_mode(hwmgr);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 39 | 90.70% | 1 | 33.33% |
| Tom St Denis | 4 | 9.30% | 2 | 66.67% |
| Total | 43 | 100.00% | 3 | 100.00% |
/**
* Set Fan Speed in RPM.
* @param hwmgr the address of the powerplay hardware manager.
* @param speed is the percentage value (min - max) to be set.
* @exception Fails is the speed not lie between min and max.
*/
int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
{
uint32_t tach_period;
uint32_t crystal_clock_freq;
int result = 0;
uint32_t reg;
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
return -1;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
if (!result) {
crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_TACH_STATUS, TACH_PERIOD,
tach_period));
}
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 145 | 89.51% | 1 | 25.00% |
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| Rex Zhu | 8 | 4.94% | 1 | 25.00% |
| Total | 162 | 100.00% | 4 | 100.00% |
/**
* Reads the remote temperature from the SIslands thermal controller.
*
* @param hwmgr The address of the hardware manager.
*/
int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
{
int temp;
uint32_t reg;
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS);
temp = cgs_read_register(hwmgr->device, reg);
temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
temp = temp & 0x1ff;
temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
return temp;
}
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| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 62 | 98.41% | 2 | 66.67% |
| Alex Deucher | 1 | 1.59% | 1 | 33.33% |
| Total | 63 | 100.00% | 3 | 100.00% |
/**
* Set the requested temperature range for high and low alert signals
*
* @param hwmgr The address of the hardware manager.
* @param range Temperature range to be programmed for
* high and low alert signals
* @exception PP_Result_BadInput if the input data is not valid.
*/
static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range)
{
int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
uint32_t val, reg;
if (low < range->min)
low = range->min;
if (high > range->max)
high = range->max;
if (low > high)
return -EINVAL;
reg = soc15_get_register_offset(THM_HWID, 0,
mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
val = cgs_read_register(hwmgr->device, reg);
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
(~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
(~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
cgs_write_register(hwmgr->device, reg, val);
return 0;
}
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| Eric Huang | 134 | 71.28% | 2 | 40.00% |
| Tom St Denis | 36 | 19.15% | 1 | 20.00% |
| Rex Zhu | 16 | 8.51% | 1 | 20.00% |
| Evan Quan | 2 | 1.06% | 1 | 20.00% |
| Total | 188 | 100.00% | 5 | 100.00% |
/**
* Programs thermal controller one-time setting registers
*
* @param hwmgr The address of the hardware manager.
*/
static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
{
uint32_t reg;
if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_TACH_CTRL, EDGE_PER_REV,
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
}
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
cgs_write_register(hwmgr->device, reg,
CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 101 | 86.32% | 1 | 50.00% |
| Tom St Denis | 16 | 13.68% | 1 | 50.00% |
| Total | 117 | 100.00% | 2 | 100.00% |
/**
* Enable thermal alerts on the RV770 thermal controller.
*
* @param hwmgr The address of the hardware manager.
*/
static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
uint32_t val = 0;
uint32_t reg;
if (data->smu_features[GNLD_FW_CTF].supported) {
if (data->smu_features[GNLD_FW_CTF].enabled)
printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to Enable FW CTF feature Failed!",
return -1);
data->smu_features[GNLD_FW_CTF].enabled = true;
}
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
cgs_write_register(hwmgr->device, reg, val);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 71 | 55.04% | 1 | 33.33% |
| Rex Zhu | 58 | 44.96% | 2 | 66.67% |
| Total | 129 | 100.00% | 3 | 100.00% |
/**
* Disable thermal alerts on the RV770 thermal controller.
* @param hwmgr The address of the hardware manager.
*/
int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = hwmgr->backend;
uint32_t reg;
if (data->smu_features[GNLD_FW_CTF].supported) {
if (!data->smu_features[GNLD_FW_CTF].enabled)
printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to disable FW CTF feature Failed!",
return -1);
data->smu_features[GNLD_FW_CTF].enabled = false;
}
reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
cgs_write_register(hwmgr->device, reg, 0);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 71 | 71.00% | 1 | 33.33% |
| Rex Zhu | 29 | 29.00% | 2 | 66.67% |
| Total | 100 | 100.00% | 3 | 100.00% |
/**
* Uninitialize the thermal controller.
* Currently just disables alerts.
* @param hwmgr The address of the hardware manager.
*/
int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
int result = vega10_thermal_disable_alert(hwmgr);
if (!hwmgr->thermal_controller.fanInfo.bNoFan)
vega10_fan_ctrl_set_default_mode(hwmgr);
return result;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 37 | 100.00% | 1 | 100.00% |
| Total | 37 | 100.00% | 1 | 100.00% |
/**
* Set up the fan table to control the fan using the SMC.
* @param hwmgr the address of the powerplay hardware manager.
* @param pInput the pointer to input data
* @param pOutput the pointer to output data
* @param pStorage the pointer to temporary storage
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{
int ret;
struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *table = &(data->smc_state_table.pp_table);
if (!data->smu_features[GNLD_FAN_CONTROL].supported)
return 0;
table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM;
table->FanThrottlingRpm = hwmgr->thermal_controller.
advanceFanControlParameters.usFanRPMMaxLimit;
table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
table->FanTargetTemperature = hwmgr->thermal_controller.
advanceFanControlParameters.usTMax;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget,
(uint32_t)table->FanTargetTemperature);
table->FanPwmMin = hwmgr->thermal_controller.
advanceFanControlParameters.usPWMMin * 255 / 100;
table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
advanceFanControlParameters.ulTargetGfxClk);
table->FanGainEdge = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainEdge;
table->FanGainHotspot = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainHotspot;
table->FanGainLiquid = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainLiquid;
table->FanGainVrVddc = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainVrVddc;
table->FanGainVrMvdd = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainVrMvdd;
table->FanGainPlx = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainPlx;
table->FanGainHbm = hwmgr->thermal_controller.
advanceFanControlParameters.usFanGainHbm;
table->FanZeroRpmEnable = hwmgr->thermal_controller.
advanceFanControlParameters.ucEnableZeroRPM;
table->FanStopTemp = hwmgr->thermal_controller.
advanceFanControlParameters.usZeroRPMStopTemperature;
table->FanStartTemp = hwmgr->thermal_controller.
advanceFanControlParameters.usZeroRPMStartTemperature;
ret = smum_smc_table_manager(hwmgr,
(uint8_t *)(&(data->smc_state_table.pp_table)),
PPTABLE, false);
if (ret)
pr_info("Failed to update Fan Control Table in PPTable!");
return ret;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 293 | 94.21% | 1 | 25.00% |
| Rex Zhu | 18 | 5.79% | 3 | 75.00% |
| Total | 311 | 100.00% | 4 | 100.00% |
/**
* Start the fan control on the SMC.
* @param hwmgr the address of the powerplay hardware manager.
* @param pInput the pointer to input data
* @param pOutput the pointer to output data
* @param pStorage the pointer to temporary storage
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
/* If the fantable setup has failed we could have disabled
* PHM_PlatformCaps_MicrocodeFanControl even after
* this function was included in the table.
* Make sure that we still think controlling the fan is OK.
*/
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_start_smc_fan_control(hwmgr);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 24 | 92.31% | 1 | 33.33% |
| Tom St Denis | 1 | 3.85% | 1 | 33.33% |
| Rex Zhu | 1 | 3.85% | 1 | 33.33% |
| Total | 26 | 100.00% | 3 | 100.00% |
int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range)
{
int ret = 0;
if (range == NULL)
return -EINVAL;
vega10_thermal_initialize(hwmgr);
ret = vega10_thermal_set_temperature_range(hwmgr, range);
if (ret)
return -EINVAL;
vega10_thermal_enable_alert(hwmgr);
/* We should restrict performance levels to low before we halt the SMC.
* On the other hand we are still in boot state when we do this
* so it would be pointless.
* If this assumption changes we have to revisit this table.
*/
ret = vega10_thermal_setup_fan_table(hwmgr);
if (ret)
return -EINVAL;
vega10_thermal_start_smc_fan_control(hwmgr);
return 0;
}Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 42 | 51.85% | 1 | 50.00% |
| Rex Zhu | 39 | 48.15% | 1 | 50.00% |
| Total | 81 | 100.00% | 2 | 100.00% |
;
int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
{
if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
vega10_fan_ctrl_set_default_mode(hwmgr);
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 36 | 100.00% | 1 | 100.00% |
| Total | 36 | 100.00% | 1 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Eric Huang | 2010 | 85.86% | 3 | 14.29% |
| Rex Zhu | 190 | 8.12% | 7 | 33.33% |
| Tom St Denis | 138 | 5.89% | 9 | 42.86% |
| Evan Quan | 2 | 0.09% | 1 | 4.76% |
| Alex Deucher | 1 | 0.04% | 1 | 4.76% |
| Total | 2341 | 100.00% | 21 | 100.00% |
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